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Maxim Integrated Products Inc.
120 San Gabriel Drive, Sunnyvale CA 94086
19-4615; Rev 0; 4/09 Product Specification Z86L81/86/98 28-Pin Low-Voltage Infrared Microcontrollers
19-4615; REV 0; 4/09 Maxim Integrated Products
120 San Gabriel Drive
Sunnyvale, CA 94086 United States 408-737-7600 www.maxim-ic.com Copyright © 2009 Maxim Integrated Products Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. Maxim retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All infor mation in this document, including descriptions of f eatures, functions, performance, technical specifications and avai lability, is subjec t to change without notice at any time. While the information furnis hed herein is held to be accurate and reliable, no responsibilit y will be assumed by Maxim for its use. Furthermore , the information contained herein does not c onvey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. Maxim is a registered trademark of Maxim Integrated Products, Inc. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders. Z8 is a registered trademark of Zilog, Inc. Crimzon is a registered trademark of Universal Electronics Inc.
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 iii Table of Contents
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09
Features
Table 1 shows the features of the Z86L81/86/98.
- Low power consumption–40 mW (typical)
- Three standby modes – Stop—2 A (typical) – Halt—0.8 mA (typical) – Low voltage
- Special architecture to automate both generation and reception of complex pulses or signals: – One programmable 8-bit counter/timer with two capture registers and two load registers – One programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair – Programmable input glitch filter for pulse reception
- Six priority interrupts – Three external – Two assigned to counter/timers – One low-voltage detection interrupt
- Low-voltage detection with flag
- Programmable watch-dog/power-on reset circuits
- Two independent comparators with programmable interrupt polarity
- Mask selectable transistor pull-ups on ports 0, 2, 3
Table 1. Features
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09
- Programmable mask options – Oscillator selection: RC oscillator or crystal/other clock source – Oscillator operational mode: normal high-frequency operation enabled or 32-KHz operation enabled – Port 0: 0–3 pull-ups – Port 0: 4–7 pull-ups – Port 2: 0–7 pull-ups – Port 3: pull-ups – Port 0: 0–3 mouse mode: normal mode (.5VDD input threshold) versus mouse mode (.4VDD input threshold) The mask option pull-up transistor has a typical equivalent resistance of 200 K±50% at VCC=3 V and 450 K±50% at VCC=2 V. Note:
reception, and internal key-scan pull-up transistors. peripheral, and battery-operated hand-held applications. consists of two additional register groups (F and D). process analog signals with separate reference voltages (Figure 9 on page 20). Power connections use the conventional descriptions listed in Table 2. Table 2. Power Connections
Figure 1. Counter/Timers Diagram
Figure 2. Functional Block Diagram
The pins are shown in Figure 3 and described in Table 3. Figure 3. 28-Pin DIP/SO IC/SSOP Pin Assignment Table 3. 28-Pin DIP , SOIC, and SSOP Pin Identification
19 P00 Input/Output Port 0 is Nibble Programmable
20 P01 Input/Output Port 0-3 can be configured as a
21 P02 Input/Output mouse/trackball input
23 P03 Input/Output
4 P04 Input/Output
5 P05 Input/Output
6 P06 Input/Output
7 P07 Input/Output
24 P20 Input/Output Port 2 pins are individually
25 P21 Input/Output configurable as input or output.
26 P22 Input/Output
27 P23 Input/Output
28 P24 Input/Output
1 P25 Input/Output
2 P26 Input/Output
3 P27 Input/Output
18 Pref1 Input Analog Ref Input
11 P31 Input IRQ2/Modulator input
12 P32 Input IRQ0
13 P33 Input IRQ1
14 P34 Output T8 output
15 P35 Output T16 output
17 P36 Output T8/T16 output
16 P37 Output
10 XTAL1 Input Crystal, Oscillator Clock
9 XTAL2 Output Crystal, Oscillator Clock
22 V SS Ground
Table 3. 28-Pin DIP , SOIC, and SSOP Pin Identification (Continued)
extended period might affect device reliability. Table 4. Absolute Maximum Ratings *Voltage on all pins with respect to GND.†See Ordering Information on page 82.
the referenced pin (see Figure 4). Figure 4. Test Load Diagram The capacitances are listed in Table 5. Table 5. Capacitance
Table 6 lists the DC characteristics. Table 6. DC Characteristics
3.6 V 7 V IIN <250 A
2.0 V 25 mV
3.6 V 25 mV
3.6 V –1 1 A VIN = 0 V, VCC
2.0 V 250 A at 32 kHz 1, 2, 3
3.6 V 850 A at 32 kHz 1, 2, 3
2.0 V 3 mA V IN = 0 V, VCC at
8.0 MHz
3.6 V 5 mA Same as above 1, 2
2.0 V 2 mA Clock Divide-by-16
3.6 V 4 mA Same as above 1, 2
2.0 V 8 A VIN = 0 V, VCC
3.6 V 10 A Same as above 4, 5, 8
2.0 V 500 A VIN = 0 V, VCC
3.6 V 800 A Same as above 4, 5, 8
3.6 V 5 20 ms
2.0 V 8 MHz max
- All outputs unloaded, inputs at rail.
- 32-kHz clock driver input.
- Same as note 1, except inputs at V
BO is measured at room temperature and typically is 1.6 V. VBO increases as the temperature decreases.
- WDT, Comparators, Low Voltage Detection, and ADC (i f applicable) are disabled. The IC might draw more cur-
rent if any of the about peripherals is enabled. Table 6. DC Characteristics (Continued)
Table 7. Additional Timing
8.0 MHz Stop-Mode
3.6 V 121 DC ns 1
2 TrC,TfC Clock Input Rise and
2.0 V 25 ns 1
3.6 V 25 ns 1
3.6 V 37 ns 1
4 TwTinL Timer Input
2.0 V 100 ns 1
3.6 V 70 ns 1
5 TwTinH Timer Input High
2.0 V 3TpC 1
3.6 V 3TpC 1
3.6 V 8TpC 1
7 TrTin,TfTin Timer Input Rise and
3.6 V 100 ns 1
2.0 V 100 ns 1,2
3.6 V 70 ns 1,2
2.0 V 5TpC 1,3
3.6 V 5TpC 1,3
9 TwIH Interrupt Request
2.0 V 5TpC 1,2
3.6 V 5TpC 1,2
10 Twsm Stop-Mode
2.0 V 12 ns
3.6 V 12 ns
11 Tost Oscillator
2.0 V 5TpC 4
3.6 V 5TpC 4
12 Twdt Watch-Dog Timer Delay Time
2.0 V 12 ms 5 0, 0
3.6 V 5 ms 5
2.0 V 25 ms 5 0, 1
3.6 V 10 ms 5
2.0 V 50 ms 5 1, 0
3.6 V 20 ms 5
2.0 V 200 ms 5 1, 1
3.6 V 80 ms 5
- Timing Reference uses 0.9 V CC for a logic 1 and 0.1 VCC for a logic 0.
- Interrupt request through Port 3 (P33–P31).
- Interrupt request through Port 3 (P30).
- For internal RC oscillator.
Table 7. Additional Timing (Continued)
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Pin Functions Standard Mode XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC net- work to the on-chip oscillator input. An external single-phase clock to the on-chip oscillator input is also an option. XTAL2 Crystal 2 (Time-Based Output) This pin connects a parallel-resonant crystal, ceramic resonant, LC, or RC net- work to the on-chip oscillator output. Port 0 (P07–P00) Port 0 is an 8-bit, bidirectional, CMOS-compatible port (see Figure 6). These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull or open drain controlled by bit D2 in the PCON register. If one or both nibbles are required for I/O operation, they must be configured by writ- ing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port. A mask option is available to program 0.4 V DD CMOS trip inputs on P00–P03. This option allows direct interface to mouse/trackball IR sensors. An optional pull-up transistor is available as a mask option on all Port 0 bits with nibble select. Internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. Note:
Figure 6. Port 0 Configuration
eight bits of Port 2 configured as inputs. Figure 7. Port 2 Configuration configured under software control for interrupt and output from the counter/timers.
Figure 8. Port 3 Configuration page 32). Other edge detect and IRQ modes are described in Table 8.
Table 8. Pin Assignments
Figure 9. Port 3 Counter/Timer Output Configuration
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Comparator Inputs In analog mode, P31 and P32 have a comparator front end. The comparator refer- ence is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding IRQ1 is diverted to the SMR sources (excluding P31, P32, and P33) as indicated in Figure 8 on page 18. In digital mode, P33 is used as D3 of the Port 3 input register, which then generates IRQ1. Comparators are powered down by entering Stop Mode. For P31–P33 to be used in a Stop-Mode Recovery source, these inputs must be placed into digital mode. Comparator Outputs These outputs can be programmed to be output on P34 and P37 through the PCON register. Functional Description The Z86L81/86/98 incorporates special functions to enhance the Z8’s functionality in consumer and battery-operated applications. Program Memory The Z86L81/86/98 family addresses 24/32/64 KB of internal program memory. The first twelve bytes are reserved for interrupt vectors. These locations contain the five 16-bit vectors, which correspond to the five available interrupts. RAM The Z86L81/86/98 device has 237 bytes of RAM, which make up the register file. See Figure 10. Note:
Figure 10. Program Memory Map (64 KB ROM)
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Expanded Register File The register file has been expanded to allow for additional system control regis- ters, and for mapping of additional peripheral devices into the register address area. The Z8 register address space R0 through R15 has been implemented as 16 banks, with 16 registers per bank. These register groups are known as the ERF (Expanded Register File). Bits 7–4 of register RP select the working register group. Bits 3–0 of register RP select the expanded register file bank. An expanded register bank is also referred to as an expanded register group (see Figure 11). Note:
Figure 11. Expanded Register File Architecture
0 UUUUUU0
0 UUUUUUU
1h to Fh exchanges the lower 16 registers to an expanded register bank. Figure 12. Register Pointer
register group 7 of bank 0 for access. Pointer addresses the starting location of the active working register group. Table 9. Expanded Register Group D
Figure 13. Register Pointer—Detail working registers and indirect addressing modes. whenever the internal stack is accessed. active working-register group.
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Register Description LVD (D) 0Ch. Low-Voltage Detection Register Bit 0 enables/disables the Low-Voltage Detection Circuit. Bit 1 flags if low voltage is detected. Interrupt 5 is triggered when the flag bit is set, given that IRQ5 is not masked. The LVD flag will be valid after enabling the detection for 20 S (design estimation, not tested in production). LVD does not work at STOP mode. It must be disabled during STOP mode in order to reduce current. HI8(D)0Bh This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register is used to hold the number of counts when the input signal is 1. L08(D)0Ah This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register is used to hold the number of counts when the input signal is 0. Field Bit Position Description LVD 765432-- Reserved No Effect LV flag set LV flag reset Enable LVD Disable LVD Note: *Default after POR Field Bit Position Description T8_Capture_HI 76543210 R W Captured Data No Effect Field Bit Position Description T8_Capture_L0 76543210 R W Captured Data No Effect Note:
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 HI16(D)09h This register holds the captured data from the output of the 16-bit Counter/ Timer16, while also holding the MS-Byte of the data. L016(D)08h This register holds the captured data from the output of the 16-bit Counter/ Timer16, while also holding the LS-Byte of the data. TC16H(D)07h Counter/Timer2 MS-Byte Hold Register. TC16L(D)06h Counter/Timer2 LS-Byte Hold Register. TC8H(D)05h Counter/Timer8 High Hold Register. Field Bit Position Description T16_Capture_HI 76543210 R W Captured Data No Effect Field Bit Position Description T16_Capture_LO 76543210 R W Captured Data No Effect Field Bit Position Description T16_Data_HI 76543210 R/W Data Field Bit Position Description T16_Data_LO 76543210 R/W Data Field Bit Position Description T8_Level_HI 76543210 R/W Data
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 TC8L(D)04h Counter/Timer8 Low Hold Register. CTR0 Counter/Timer8 Control Register Table 10 lists and briefly describes the fields for this register. T8 Enable This field enables T8 when set (written) to 1. Field Bit Position Description T8_Level_LO 76543210 R/W Data Table 10.CTR0 (D)00 Counter/Timer8 Control Register Field Bit Position Value Description W Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass W No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 T8 _Clock ---43--- R/W 0 0 0 1 1 0 1 1 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_MASK -----2-- R/W 0 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P34 as Port Output T8 Output on P34 Note: *Indicates the value upon Power-On Reset.
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Single/Modulo-N When set to 0 (modulo-N), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Timeout This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 should be written to its location. Writing a 1 is the only way to reset the Terminal Count status condition. Therefore, reset this bit before using/ enabling the counter/timers. The first clock of T8 might not feature complete clock width and can occur any time when enabled. Care must be taken when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers is ORed or ANDed with the designated value and then written back into the registers. Example When the status of bit 5 is 1, a timer reset condition occurs. T8 Clock This bit defines the frequency of the input signal to T8. Capture_INT_Mask Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask Set this bit to allow an interrupt when T8 has a timeout. P34_Out This bit defines whether P34 is used as a normal output pin or the T8 output. Caution: Note:
This register controls the functions in common with the T8 and T16. Table 11 lists and briefly describes the fields for this register. Table 11. CTR(D)01h Register Descriptions
4 SCLK Cycle
8 SCLK Cycle
the combined output of T8 and T16. T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1. Table 11. CTR(D)01h Register Descriptions (Continued)
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 measure ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D1. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Initial_T16 Out/Falling _Edge In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3, D2). When the counter is not enabled and this bit is set, T16_OUT is set to the opposite state of this bit. This measure ensures that when the clock is enabled, a transition occurs to the initial state set by CTR1, D0. In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Modifying CTR1, (D1 or D0) while the counters are enabled causes unpredictable output from T8/16_OUT. CTR2 Counter/Timer 16 Control Register Table 12 lists and briefly describes the fields for this register. Table 12.CTR2 (D)02h: Counter/Timer16 Control Register Field Bit Position Value Description W Counter Disabled Counter Enabled Stop Counter Enable Counter Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge Time_Out --5----- R W No Counter Timeout Counter Timeout Occurred No Effect Reset Flag to 0 Note:
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 T16_Enable This field enables T16 when set to 1. Single/Modulo-N In Transmit Mode, when set to 0, the counter reloads the initial value when termi- nal count is reached. When set to 1, the counter stops when the terminal count is reached. In Demodulation Mode, when set to 0, T16 captures and reloads on detection of all the edges. When set to 1, T16 captures and detects on the first edge, but ignores the subsequent edges. For details, see the description of T16 Demodula- tion Mode on page 45. Time_Out This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to this location. T16_Clock This bit defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask This bit is set to allow an interrupt when data is captured into LO16 and HI16. T16 _Clock ---43--- R/W 00 SCLK SCLK/2 SCLK/4 SCLK/8 Capture_INT_Mask -----2-- R/W 0 Disable Data Capture Int. Enable Data Capture Int. Enable Timeout Int. P35 as Port Output T16 Output on P35 Note: *Indicates the value upon Power-On Reset. Table 12.CTR2 (D)02h: Counter/Timer16 Control Register (Continued) Field Bit Position Value Description
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Counter_INT_Mask This bit is set to allow an interrupt when T16 times out. P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. SMR2 Stop-Mode Recovery Register 2 Table 13 lists and briefly describes the fields for this register. Counter/Timer Functional Blocks Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5– D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal that have a width less than specified (CTR1 D3, D2) are filtered out (see Figure 14). Table 13.SMR2(F)0Dh: Stop-Mode Recovery Register 2 Field Bit Position Value Description Low High Reserved --5----- 0 Reserved (Must be 0) Source ---432-- W 000* 001 010 011 100 101 110 111 A. POR Only B. NAND of P23–P20 C. NAND of P27–P20 D. NOR of P33–P31 E. NAND of P33–P31 F. NOR of P33-P31, P00, P07 G. NAND of P33-P31, P00, P07 H. NAND of P33-P31, P22–P20 Notes: * Indicates the value upon Power-On Reset
Figure 14. Glitch Filter Circuitry 1; if it is 1, T8_OUT is 0. See Figure 15.
Figure 15. Transmit Mode Flowchart
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). repeats the cycle. See Figure 16. Figure 16. 8-Bit Counter/Timer Circuits effect when they are loaded.
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 T8 Demodulation Mode Program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected during counting, the current value of T8 is complemented and put into one of the capture registers. If it is a positive edge, data is put into LO8, if negative edge, HI8. One of the edge detect status bits (CTR1, D1; D0) is set, and an inter- rupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, an interrupt can be generated if enabled (CTR0, D1), and T8 continues counting from FFh (see Figure 19 and Figure 20).
Figure 19. Demodulation Mode Count Capture Flowchart
Figure 20. Demodulation Mode Flowchart
gramming CTR1 D3, D2 to a 10 or 11. and a status bit (CTR2, D5) is set. See Figure 21. Figure 21. 16-Bit Counter/Timer Circuits effect when they are loaded.
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 This T16 mode is generally used to measure mark time, defined as the length of time between carrier signal bursts (marks). If D6 of CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A timeout of T8 causes T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 cap- tures and reloads on the next edge (rising, falling, or both depending on CTR1, D5; D4), thereby continuing to ignore subsequent edges. This T16 mode is generally used to measure mark time, defined as the length of time between carrier signal bursts (marks). If T16 reach 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2 D1). Ping-Pong Mode This operation mode is only valid in Transmit Mode. T8 and T16 must be pro- grammed in Single-Pass Mode (CTR0, D6, CTR2, D6) and Ping-Pong Mode must be programmed in CTR1, D3; D2. The user can begin the operation by enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled and T16 is enabled. T16_OUT switches to its initial value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops, T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2, D1). To stop the Ping- Pong operation, write 00 to bits D3 and D2 of CTR1. See Figure 24. Enabling Ping-Pong operation while the counter/timers are running might cause intermittent counter/timer function. Disable the counter/timers and then reset the status flags before instituting this operation. Note:
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 During Ping-Pong Mode The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) are set and cleared alter- nately by hardware. The timeout bits (CTR0 D5, CTR2 D5) are set every time the counter/timers reach the terminal count. Interrupts The Z86L81/86/98 features six different interrupts (Table 14). The interrupts are maskable and prioritized (Figure 26). The six sources are divided as follows: three sources are claimed by Port 3 lines P33–P31, two by the counter/timers, and one by LVD (Table 14). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests.
Figure 26. Interrupt Block Diagram
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 When more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle is activated when an interrupt request is granted. As a result, all subsequent interrupts are disabled, and the Program Counter and Status Flags are saved. The cycle then branches to the program memory vector location reserved for that interrupt. All Z86L81/86/98 interrupts are vectored through loca- tions in the program memory. This memory location, and the next byte, contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked, and the Interrupt Request register is polled to determine which of the interrupt requests require service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling, or both edge triggered; all are programmable by the user. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is indicated in Table 15. Table 14.Interrupt Types, Sources, and Vectors Name Source Vector Location Comments IRQ0 P32 0,1 External (P32), Rising Falling Edge Triggered IRQ1 P33 2,3 External (P33) , Falling Edge Triggered IRQ2 P31, T IN 4,5 External (P31), Rising Falling Edge Triggered IRQ3 T16 6,7 Internal IRQ4 T8 8,9 Internal IRQ5 LVD 10,11 Internal Table 15.IRQ Register* IRQ Interrupt Edge D7 D6 IRQ2(P31) IRQ0 (P32)
00 F F
01 F R
10 R F
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Clock The Z86L81/86/98 on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 Ohms. The Z86LXX on-chip oscillator can be driven with a low-cost RC network or other suit- able external clock source. For 32-kHz crystal operation, both an external feedback (Rf) and serial resistor (Rd) are required. See Figure 27. The crystal must be connected across XTAL1 and XTAL2 using the recommended capacitors (capacitance greater than or equal to 22 pF) from each pin to ground. The RC oscillator configuration is an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to ground (Figure 27). 11R / F R / F Notes: F = Falling Edge R = Rising Edge *In stop mode, the comparators are turned off. Table 15.IRQ Register* (Continued) IRQ Interrupt Edge
Figure 27. Oscillator Configuration tor circuit to stabilize before instruction execution begins.
- Power Fail to Power OK status, including Waking up from VBO Standby
- Stop-Mode Recovery (if D5 of SMR = 1)
- WDT Timeout The POR timer is a nominal 5 ms. Bit 5 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC, LC oscillators). C1XTAL1 XTAL2 XTAL1 XTAL2 XTAL1 XTAL2 XTAL1 XTAL2 XTAL1 XTAL2 L R Rf Rd Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * f = 8 MHz * Preliminary value including pin parasitics External Clock32 kHz XTAL C1 = 20 pF, C = 33 pF Rd = 56 - 470K Rf = 10 M RC @ 3V VCC (TYP) C1 = 33 pF * R = 1K * LC C1, C2 = 22 pF L = 130 H * f = 3 MHz *
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 HALT HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/ timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP This instruction turns off the internal clock and external crystal oscillation, thereby reducing the standby current to 10 A or less. STOP Mode is terminated only by a reset (such as WDT timeout), POR, SMR, or external reset. This termination causes the processor to restart the application program at address 000Ch. In order to enter STOP (or HALT) mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. Execute a NOP (Op Code = FFh) imme- diately before the appropriate sleep instruction, as follows: FF NOP ; clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT Mode Port Configuration Register (PCON) The PCON register (Figure 28) configures the comparator output on Port 3. It is located in the expanded register 2 at Bank F, location 00.
Figure 28. Port Configuration Register (PCON) (Write Only) push-pull, and a 0 sets the output to open-drain. Mode Recovery (Figure 29). All bits are write only except bit 7, which is read only. Mode Recovery signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not.
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Figure 29. Stop-Mode Recovery Register sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0.
0 OFF * *
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
0 OFF
1 ON *
0 Low *
1 High
0 POR *
1 Stop Recovery * *
Figure 30. SCLK Circuit
Figure 31. Stop-Mode Recovery Source
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Any Port 2 bit defined as an output drives the corresponding input to the default state to allow the remaining inputs to control the AND/OR function. Refer to SMR2 register on page 58 for other recover sources. Stop-Mode Recovery Delay Select (D5) This bit, if low, disables the 5 ms RESET delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the “fast” wake up is selected, the Stop- Mode Recovery source must be kept active for at least 5 TpC. Stop-Mode Recovery Edge Select (D6) A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Z86L81/86/98 from STOP Mode. A 0 indicates Low level recovery. The default is 0 on POR. Cold or Warm Start (D7) This bit is read only, and it is set to 1 when the device is recovered from stop mode. The bit is set to 0 when the device reset is other than Stop Mode Recovery (SMR). Stop-Mode Recovery Register 2 (SMR2) This register determines the mode of Stop-Mode Recovery for SMR2 (Figure 32). Table 16.Stop-Mode Recovery Source SMR:432 Operation D4 D3 D2 Description of Action 0 0 0 POR and/or external reset recovery
001 R e s e r v e d
1 1 0 Logical NOR of P20 through P23 1 1 1 Logical NOR of P20 through P27 Note:
Figure 32. Stop-Mode Recovery Register 2 ((0F) DH:D2–D4, D6 Write Only)
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
nal count. The WDT must initially be enabled by executing the WDT instruction. organized as shown in Figure 33. Figure 33. Watch-Dog Timer Mode Register (Write Only)
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 WDT Time Select (D0, D1) Selects the WDT time period. It is configured as indicated in Table 17. WDTMR During HALT (D2) This bit determines whether or not the WDT is active during HALT Mode. A 1 indi- cates active during HALT. The default is 1. See Figure 34. Table 17.WDT Time Select* D1 D0 Timeout of Internal RC OSC 00 5 m s m i n 0 1 10 ms min 1 0 20 ms min 1 1 80 ms min Note: *TpC = XTAL clock cycle. The default on reset is 10 ms.
Figure 34. Resets and WDT This bit determines whether or not the WDT is active during STOP Mode. during STOP . The default is 1. configuration of this bit is 0, which selects the RC oscillator.
- CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers upon a Low-to-High input translation.
5 Clock Filter *CLR2 18 Clock RESET
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Mask Selectable Options There are seven Mask Selectable Options to choose from based on ROM code requirements. These are listed in Table 18. Brown-Out Voltage/Standby An on-chip Voltage Comparator checks that the VCC is at the required level for correct operation of the device. Reset is globally driven when VCC falls below VBO. A small further drop in VCC causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. Typical Low-Voltage power consumpion in this Low Voltage Standby mode (ILV) is about 20 A. If the VCC is allowed to stay above Vram, the RAM content is preserved. When the power level is returned to above VBO, the device performs a POR and functions normally. Low-Voltage Detection and Flag A Low-Voltage Detection circuit can be used optionally when the voltage decreases to VLVD. Expanded Register Bank 0Dh register 0Ch bit 0 and 1 are used for this option. Bit D0 is used to enable/disable this function. Bit D1 is the status flag bit of the LVD. Table 18.Mask Selectable Options RC/Other RC/XTAL 32 kHz XTAL On/Off Port 04-07 Pull-Ups On/Off Port 00-03 Pull-Ups On/Off Port 20-27 Pull-Ups On/Off Port 3 Pull-Ups On/Off Port0: 0-3 Mouse Mode 0.4 V DD Trip On/Off
Figure 35. T8 Control Register ((0D) OH: Read/Write Except Where Noted)
0 P34 as Port Output *
1 Timer8 Output
0 Disable T8 Timeout Interrupt
1 Enable T8 Timeout Interrupt
0 Disable T8 Data Capture Interrupt
1 Enable T8 Data Capture Interrupt
00 SCLK on T8
01 SCLK/2 on T8
10 SCLK/4 on T8
11 SCLK/8 on T8
0 Modulo-N
1 Single Pass
Figure 36. T8 and T16 Common Control Functions ((0D) 1h: Read/Write)
1 T16_OUT is 1 initially
1 T8_OUT is 1 initially
0 P36 as Port Output *
1 P36 as T8/T16_OUT
0 P31 as Demodulator Input
1 P20 as Demodulator Input
0 Transmit Mode *
1 Demodulation Mode
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09 Care must be taken in differentiating Transmit Mode from Demodulation Mode. Depending on which of these two modes is operating, the CTR1 bit has different functions. Changing from one mode to another cannot be done without disabling the counter/timers. Notes:
Figure 37. T16 Control Register ((0D) 2h: Read/Write Except Where Noted)
0 P35 is Port Output *
1 P35 is TC16 Output
0 Disable T16 Timeout Interrupt
1 Enable T16 Timeout Interrupt
0 Disable T16 Data Capture Interrupt
1 Enable T16 Data Capture Interrupt
0 Modulo-N for T16
0 Single Pass for T16
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
Figure 38. Low-Voltage Detection
Figure 39. Stop-Mode Recovery Register ((0F) 0Bh: D6–D0=Write Only, D7=Read
0 OFF *
Figure 40. Stop-Mode Recovery Register 2 ((0F) 0Dh:D2–D4, D6 Write Only) Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
Figure 41. Watch-Dog Timer Register ((0F) 0Fh: Write Only)
Figure 42. Port Configuration Register (PCON) ((0F) 0h: Write Only) Figure 43. Port 2 Mode Register (F6h: Write Only)
0 P34, P37 Standard Output *
0 Defines bit as OUTPUT
1 Defines bit as INPUT *
Figure 44. Port 3 Mode Register (F7h: Write Only)
Figure 45. Port 0 and 1 Mode Register (F8h: Write Only)
Figure 46. Interrupt Priority Register (F9h: Write Only)
000 Reserved
001 C > A > B
010 A > B >C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
Figure 47. Interrupt Request Register (FAh: Read/Write) Figure 48. Interrupt Mask Register (FBh: Read/Write)
1 Enables IRQ5–IRQ0
0 Master Interrupt Disable *
1 Master Interrupt Enable * *
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09
Package Information
Package information is shown in Figure 53, Figure 54, and Figure 55. Figure 53. 28-Pin DIP Package Diagram coordinate for chip-on-board assembly.
Figure 54. 28-Pin SOIC Package Diagram
Figure 55. 28-Pin SSOP Package Diagram
28-Pin Low-Voltage Infrared Microcontrollers 19-4615; Rev 0; 4/09
Ordering Information
For fast results, contact your local Maxim sales office for assistance in ordering the part required. Example Z86L81/86/98—8.0 MHz 28-Pin DIP Z86L8108PSC Z86L8608PSC Z86L9808PSC 28-Pin SOIC Z86L8108SSC Z86L8608SSC Z86L9808SSC 28-Pin SSOP Z86L8108HSC Z86L8608HSC Z86L9808HSC Die Form Please contact Maxim. Codes Package P = Plastic DIP S = SOIC (Small Outline Integrated Circuit) H = SSOP (Shrink Small Outline Package) Temperature S = 0 °C to +70 °C Speed 8 = 8.0 MHz Environmental C = Plastic Standard G = Lead Free Z 86L98 08 P S C is a Z86L98, 8 MHz, DIP , 0 °C to 70 °C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Maxim Prefix