Z86E09

Z86E0208PSC ETC | Alldatasheet

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ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008 PS004602-0401 PRELIMINARY Product Specification Z86E02/E04/E08/E09 General-Purpose OTP MCU with 14 I/O LInes

This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www .ZiLOG.com ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. Document Disclaimer © 2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY T a b le of Contents iii Table of Contents

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY T a b le of Contents iv

Table 10. AC Electrical Characteristics—STANDARD Mode and Temperature 26 Table 11. AC Electrical Timing—STANDARD Mode at Extended Temperature 27 Table 12. AC Electrical Timing—LOW NOISE Mode at Standard Temperature 28 Table 13. AC Electrical Timing—LOW NOISE Mode at Extended Temperature 30 Table 17. Typical Frequency vs. RC Values—VCC

nomically desirable with masked ROM versions. under software control to provide timing, status signals, or parallel I/O.

14 Input/Output Lines

Table 1. Z86E02/E04/E08/E09 Features

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Architectural Overview On-Chip Oscillator that accepts Crystal, Ceramic Resonance, LC, RC, or External Clock Clock-Free WDT Reset Low-Power Consumption (50mW typical) Fast Instruction Pointer (1 µ s @ 12 MHz) RAM Bytes (125) All Signals with an overline, “ ”, are active Low, for example: B/W (WORD is active Low); B/W (BYTE is active Low, only). Power connections follow conventional descriptions, as noted below: Connection Circuit Device Power V CC V DD Ground GND V SS Note:

Figure 1. Functional Block Diagram

Figure 2. EPROM Programming Mode Block Diagram

Figure 3. 18-Pin DIP/SOIC Configuration, STANDARD Mode Table 2. 18-Pin DIP/SOIC Pin Identification, STANDARD Mode

1 P24 Port 2, Pin 4 Input/Output

2 P25 Port 2, Pin 5 Input/Output

3 P26 Port 2, Pin 6 Input/Output

4 P27 Port 2, Pin 7 Input/Output

8 P31 Port 3, Pin 1, AN1 Input

9 P32 Port 3, Pin 2, AN2 Input

10 P33 Port 3, Pin 3, REF Input

11 P00 Port 0, Pin 0 Input/Output

12 P01 Port 0, Pin 1 Input/Output

13 P02 Port 0, Pin 2 Input/Output

14 GND Ground

15 P20 Port 2, Pin 0 Input/Output

16 P21 Port 2, Pin 1 Input/Output

17 P22 Port 2, Pin 2 Input/Output

18 P23 Port 2, Pin 3 Input/Output

Table 2. 18-Pin DIP/SOIC Pin Identification, STANDARD Mode (Continued)

Figure 4. 18-Pin DIP/SOIC Configuration, EPROM Mode Table 3. 18-Pin DIP/SOIC Pin Identification, EPROM Mode

1 D4 Data 4 Input/Output

2 D5 Data 5 Input/Output

3 D6 Data 6 Input/Output

4 D7 Data 7 Input/Output

6 NC No Connection

8 OE Output Enable Input

9 EPM EPROM Program Mode Input

11 CLEAR Clear Clock Input

12 CLOCK Address Input

15 D0 Data 0 Input/Output

16 D1 Data 1 Input/Output

17 D2 Data 2 Input/Output

18 D3 Data 3 Input/Output

Figure 5. 20-Pin SSOP Pin Configuration, STANDARD Mode Table 4. 20-Pin SSOP Pin Identification, STANDARD Mode

9 P31 Port 3, Pin 1, AN1 Input

10 P32 Port 3, Pin 2, AN2 Input

11 P33 Port 3, Pin 3, REF Input

12 P00 Port 0, Pin 0 Input/Output

13 P01 Port 0, Pin 1 Input/Output

14 P02 Port 0, Pin 2 Input/Output

15 GND Ground

16 GND Ground

17 P20 Port 2, Pin 0 Input/Output

18 P21 Port 2, Pin 1 Input/Output

19 P22 Port 2, Pin 2 Input/Output

20 P23 Port 2, Pin 3 Input/Output

Figure 6. 20-Pin SSOP Pin Configuration, EPROM Mode Table 5. 18-Pin DIP/SOIC Pin Identification, EPROM Mode

8 CE Chip Enable Input

9 OE Output Enable Input

10 EPM EPROM Program Mode Input

12 CLEAR Clear Clock Input

13 CLOCK Address Input

17 D0 Data 1 Input/Output

18 D1 Data 0 Input/Output

19 D2 Data 2 Input/Output

20 D3 Data 3 Input/Output

General-Purpose OTP MCU with 14 I/O LInes

Electrical Characteristics

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This rating is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rat- ing conditions for an extended period may affect device reliability. Total power dis- sipation should not exceed 462 mW for the package. See Table 6. Power dissipation is calculated as follows: Total Power Dissipation = VCC x [ICC–(sum of IOH)] + sum of [(VCC–VOH) x IOH] + sum of (V0L x I0L) Table 6. Absolute Maximum Ratings

1. Applies to all pins except where otherwise noted. Maximum current into or out of pin must be ± 600 µA.
2. Device pin is not at an output Low state.

TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Figure 7. Test Load Diagram Table 7. Capacitance

microcontroller, at a standard ambient temperature range of 0ºC to 70ºC. Table 8. DC Characteristics, Standard Temperature Range

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

2.2 V 5

Table 8. DC Characteristics, Standard Temperature Range (Continued)

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

microcontroller, at an extended ambient temperature range of –40ºC to 105ºC. Table 9. DC Characteristics, Extended Temperature Range

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

Table 9. DC Characteristics, Extended Temperature Range (Continued)

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

1. Typical values are read at a VCC of 5.0V.
2. Port 2, Port 3, and Port 0 only.
3. STANDARD mode (not LOW EMI mode).
4. These values apply while operating in RUN mode or HALT mode.
5. These values apply while operating in STOP mode.
6. All outputs are unloaded and all inputs are at the V
7. If the analog comparator is selected, then the comparator inputs must be at the VCC level.
8. A 10-MΩ pull-up resistor is required in the circuit between the XIN pin to the VCC pin.

General-Purpose OTP MCU with 14 I/O LInes Table 10.AC Electrical Characteristics—STANDARD Mode and Temperature No Symbol Parameter V CC TA = 0ºC to +70ºC Units Notes 8MHz 12MHz Min Max Min Max 1T PC Input Clock Period 3.0V 125 DC 83 DC ns 1 5.5V 125 DC 83 DC ns 1 2T RC,TFC Clock Input Rise and Fall Times 3.0V 25 15 ns 1 5.5V 25 15 ns 1 3T WC Input Clock Width 3.0V 62 41 ns 1 5.5V 62 41 ns 1 4T WTINL Timer Input Low Width 3.0V 100 100 ns 1 5.5V 70 70 ns 1 5T WTINH Timer Input High Width 3.0V 5T PC5 T PC1 5.5V 5T PC5 T PC1 6T PTIN Timer Input Period 3.0V 8T PC8 T PC1 5.5V 8T PC8 T PC1 7T RTIN, TTTIN Timer Input Rise and Fall Time 3.0V 100 100 ns 1 5.5V 100 100 ns 1 WIL Interrupt Request Input Low Time 3.0V 70 70 ns 1,2 5.5V 70 70 ns 1,2 9T WIH Interrupt Request Input High Time 3.0V 5T PC5 T PC 1,2 5.5V 5T PC5 T PC 1,2

10 T WDT Watch-Dog Timer Delay

3.0V 12 12 ms 1,3 5.5V 12 12 ms 1,3 11 T POR Power-On Reset Time 3.0V 2 25 2 25 ms 1,4 5.5V 2 25 2 25 ms 1,4 Notes: 1. Timing reference is 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33–P31). 3. Typical T WDT is 55msec @ 5.0V and 25ºC. 4. Typical TPOR is 7msec @ 5.0V and 25ºC.

General-Purpose OTP MCU with 14 I/O LInes STANDARD Mode at Extended Temperature Table 11 describes timing characteristics in STANDARD mode at extended tem- perature for the timing diagram noted in Figure 8. Table 11.AC Electrical Timing—STANDARD Mode at Extended Temperature No Symbol Parameter V CC TA = –40ºC to +105ºC Units Notes 8MHz 12MHz Min Max Min Max 1 TPC Input Clock Period 3.0V 125 DC 83 DC ns 1 5.5V 125 DC 83 DC ns 1

2 TRC,TFC Clock Input Rise and Fall

3.0V 25 15 ns 1 5.5V 25 15 ns 1 3 TWC Input Clock Width 3.0V 62 41 ns 1 5.5V 62 41 ns 1 4 TWTINL Timer Input Low Width 3.0V 70 70 ns 1 5.5V 70 70 ns 1 5 TWTINH Timer Input High Width 3.0V 5TPC5 T PC 1 5.5V 5TPC5 T PC 1 6 TPTIN Timer Input Period 3.0V 8TPC8 T PC 1 5.5V 8TPC8 T PC 1

7 TRTIN,

3.0V 100 100 ns 1 5.5V 100 100 ns 1 TWIL Interrupt Request Input Low Time 3.0V 70 70 ns 1,2 5.5V 70 70 ns 1,2

9 TWIH Interrupt Request Input

3.0V 5TPC5 T PC 1,2 5.5V 5TPC5 T PC 1,2

10 TWDT Watch-Dog Timer Delay

3.0V 12 12 ms 1,3 5.5V 12 12 ms 1,3 Notes: 1. Timing reference is 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request made through Port 3 (P33–P31). 3. Typical T WDT is 55msec @ 5.0V and 25ºC. 4. Typical TPOR is 7msec @ 5.0V and 25ºC.

General-Purpose OTP MCU with 14 I/O LInes LOW NOISE Mode at Standard Temperature Table 12 describes timing characteristics in LOW NOISE mode at standard tem- perature for the timing diagram noted in Figure 8. 11 TPOR Power-On Reset Time 3.0V 2 25 2 25 ms 1,4 5.5V 2 25 2 25 ms 1,4 Table 12.AC Electrical Timing—LOW NOISE Mode at Standard Temperature No Symbol Parameter V CC TA = 0ºC to +70ºC Units Notes 1MHz 4MHz Min Max Min Max 1T PC Input Clock Period 3.0V 1000 DC 250 DC ns 1 5.5V 1000 DC 250 DC ns 1 2T RC, TFC Clock Input Rise and Fall Times 3.0V 25 25 ns 1 5.5V 25 25 ns 1 3T WC Input Clock Width 3.0V 500 125 ns 1 5.5V 500 125 ns 1 4. T WTINL Timer Input Low Width 3.0V 70 70 ns 1 5.5V 70 70 ns 1 5T WTINH Timer Input High Width 3.0V 2.5TpC 2.5TpC 1 5.5V 2.5TpC 2.5TpC 1 Notes: 1. Timing reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33–P31). 3. Typical T WDT is 55msec @ 5.0V and 25ºC. 4. Typical TPOR is 7msec @ 5.0V and 25ºC. Table 11.AC Electrical Timing—STANDARD Mode at Extended Temperature (Continued) No Symbol Parameter V CC TA = –40ºC to +105ºC Units Notes 8MHz 12MHz Min Max Min Max Notes: 1. Timing reference is 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request made through Port 3 (P33–P31). 3. Typical T WDT is 55msec @ 5.0V and 25ºC. 4. Typical TPOR is 7msec @ 5.0V and 25ºC.

General-Purpose OTP MCU with 14 I/O LInes 6T PTIN Timer Input Period 3.0V 4TpC 4TpC 1 5.5V 4TpC 4TpC 1 7T RTIN, TTTIN Timer Input Rise and Fall Time 3.0V 100 100 ns 1 5.5V 100 100 ns 1 WIL Low Time Interrupt Request Input 3.0V 70 70 ns 1,2 5.5V 70 70 ns 1,2 9T WIH High Time Interrupt Request Input 3.0V 2.5TpC 2.5TpC 1,2 5.5V 2.5TpC 2.5TpC 1,2 10 T WDT Watch-Dog Timer Delay Time for Time-out 3.0V 12 12 ms 1,3 5.5V 12 12 ms 1,3 11 TPOR Power-On Reset Time 3.0V 2 25 2 25 ms 1,4 5.5V 2 25 2 25 ms 1,4 Table 12.AC Electrical Timing—LOW NOISE Mode at Standard Temperature (Continued) No Symbol Parameter V CC TA = 0ºC to +70ºC Units Notes 1MHz 4MHz Min Max Min Max Notes: 1. Timing reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33–P31). 3. Typical T WDT is 55msec @ 5.0V and 25ºC. 4. Typical TPOR is 7msec @ 5.0V and 25ºC.

General-Purpose OTP MCU with 14 I/O LInes LOW NOISE Mode at Extended Temperature Table 13 describes timing characteristics in LOW NOISE mode at extended tem- perature for the timing diagram noted in Figure 8. Table 13.AC Electrical Timing—LOW NOISE Mode at Extended Temperature No Symbol Parameter V CC TA = –40ºC to +105ºC Units Notes 1MHz 4MHz Min Max Min Max 1T PC Input Clock Period 4.5V 1000 DC 250 DC ns 1 5.5V 1000 DC 250 DC ns 1 2T RC, TFC Clock Input Rise and Fall Times 4.5V 25 25 ns 1 5.5V 25 25 ns 1 3T WC Input Clock Width 4.5V 500 125 ns 1 5.5V 500 125 ns 1 4. T WTINL Timer Input Low Width 4.5V 70 70 ns 1 5.5V 70 70 ns 1 5T WTINH Timer Input High Width 4.5V 2.5T PC 2.5T PC1 5.5V 2.5T PC 2.5T PC1 6T PTIN Timer Input Period 4.5V 4T PC4 T PC1 5.5V 4T PC4 T PC1 7T RTIN, TTTIN Timer Input Rise and Fall Time 4.5V 100 100 ns 1 5.5V 100 100 ns 1 WIL Low Time Interrupt Request Input Low Time 4.5V 70 70 ns 1,2 5.5V 70 70 ns 1,2 9T WIH High Time Interrupt Request Input High Time 4.5V 2.5T PC 2.5T PC 1,2 5.5V 2.5T PC 2.5T PC 1,2 4.5V 12 12 ms 1,3 5.5V 12 12 ms 1,3 Notes: 1. Timing reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33–P31). 3. Typical T WDT is 55msec @ 5.0V and 25ºC. 4. Typical TPOR is 7msec @ 5.0V and 25ºC.

General-Purpose OTP MCU with 14 I/O LInes Low-Noise Version Low-EMI Emission The device can be programmed to operate in a LOW EMI EMISSION mode by means of an OTP bit option. Use of this feature results in:

• All pre-driver slew rates reduced to 10 ns typical
• Internal SCLK and TCLK operation limited to a maximum of 4 MHz–250 ns cycle time
• Output drivers typically exhibit resistances of 500Ω
• Oscillator divide-by-two circuitry eliminated The LOW EMI mode is an OPT option bit that can be selected by the customer at the time the ROM code is programmed into the OTP EPROM. The default condi- tion is a disabled LOW EMI mode. 11 TPOR Power-On Reset Time 4.5V 2 25 2 25 ms 1,4 5.5V 2 25 2 25 ms 1,4 Table 13.AC Electrical Timing—LOW NOISE Mode at Extended Temperature (Continued) No Symbol Parameter V CC TA = –40ºC to +105ºC Units Notes 1MHz 4MHz Min Max Min Max Notes: 1. Timing reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33–P31). 3. Typical T WDT is 55msec @ 5.0V and 25ºC. 4. Typical TPOR is 7msec @ 5.0V and 25ºC.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Pin Functions Pin Functions EPROM Mode D7–D0 Data Bus. Data can be read from, or written to, the EPROM through this data bus. VCC Power Supply. It is typically 5V during all EPROM operations (PROGRAM, PROGRAM VERIFY, etc.). CE Chip Enable (active Low). This pin is active during EPROM READ mode, PROGRAM mode, and PROGRAM VERIFY mode. OE Output Enable (active Low). This pin drives the Data Bus direction. When this pin is Low, the data bus is output. When High, the data bus is input. EPM EPROM Program Mode. This pin controls the selection of EPROM opera- tion modes. VPP Program Voltage. This pin supplies the program voltage. Clear (active High). This pin resets the internal address counter at the High level. Clock Address Clock. This pin is a clock input. The internal address counter increases by one count with one clock cycle. PGM Program Mode (active Low). A Low level at this pin programs the data to the EPROM through the data bus. Pin Function Changes in EPROM Mode With the exception of VCC and GND, the Z8 changes all of its pin functions in EPROM mode. XOUT offers no function; XIN functions as CE, P31 functions as OE, P32 functions as EPM, P33 functions as VPP, P00 functions as CLEAR, P01 functions as CLOCK, and P02 functions as PGM. Please refer to the Program- ming Specification for additional EPROM mode descriptions. STANDARD Mode XIN, XOUT. Crystal In, Crystal Out (time-based input and output, respectively). These pins connect a parallel-resonant crystal, LC, or an external single-phase clock (12 MHz max) to the on-chip clock oscillator and buffer. Port 0, P02–P00. Port 0 is a 3-bit bidirectional, Schmitt-triggered CMOS-compati- ble I/O port. These three I/O lines can be globally configured under software con- trol to be inputs or outputs (Figure 9). Auto Latch. The Auto Latch places valid CMOS levels on all CMOS inputs (except P33, P32, P31) that are not externally driven. A valid CMOS level, rather

be disabled by programming the AUTO LATCH DISABLE option bit. puts can be globally programmed as either push-pull or open-drain (Figure 10). Figure 9. Port 0 Configuration

Figure 10. Port 2 Configuration

as digital Schmitt-trigger inputs or analog inputs. Figure 11. Port 3 Configuration

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Pin Functions Comparator Inputs. Two analog comparators are added to input of Port 3, P31, and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators. Typical applications for the on-board comparators; zero-crossing detection, A/D conversion, voltage scaling, and threshold detection. In ANALOG mode, P33 input functions serve as a reference voltage to the comparators. The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP mode. The common voltage range is 0–4 V when the V CC is 5.0V; the power supply and common mode rejection ratios are 90 dB and 60dB, respectively. Interrupts are generated on either edge of Comparator 2’s output, or on the falling edge of Comparator 1’s output. The comparator output is used for interrupt gener- ation, Port 3 data inputs, or T IN through P31. Alternatively, the comparators can be disabled, freeing the reference input (P33) for use as IRQ1 and/or P33 input. The comparator requires two NOPs to be stable after setting its enable bit. ZiLOG recommends that interrupts IRQ0, IRQ1, and IRQ2 be disabled before setting the enable bit. After enabling the comparator, IRQ0, IRQ1, and IRQ2 should be cleared prior to reenabling these interrupts. ZiLOG also recommends clearing these interrupts when disabling the comparator.

• Power-On Reset
• Watch-Dog Timer Reset Power-On Reset (POR) Upon power-up, the Power-On Reset circuit waits for TPOR ms, plus 18 clock cycles, then starts program execution at address 000Ch (Figure 12). The Z8 con- trol registers' reset value is indicated in Table 14.

Figure 12. Internal Reset Configuration it may affect device reliability.

18 Clock

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Functional Description A timer circuit clocked by a dedicated on-board RC oscillator is used for a POR timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer trig- gered by one of the four following conditions:

• Power-bad to power-good status
• Stop-Mode Recovery
• WDT time-out
• WDH time-out Watch-Dog Timer Reset The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its termi- nal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an on-board RC oscillator. F B h I M R 0UUUUUUU F A h I R Q UU000000 IRQ3 is used for positive edge detection F 9 h I P R UUUUUUUU F8h* P01M U U U 0 U U 0 1 F7h* P3M UUUUUU00 F6h* P2M 11111111 Inputs after reset F5h PRE0 UUUUUUU0 F 4 h T 0 UUUUUUUU F3h PRE1 UUUUUU00 F 2 h T 1 UUUUUUUU F 1 h T M R 00000000 Table 14.Z8 Control Registers Reset Values* (Continued) Address Register Reset Condition CommentsD7 D6 D5 D4 D3 D2D1 D0 Note: *Registers are not reset after a Stop-Mode Recovery using P27 pin. A subsequent reset causes these control registers to be reconfigured as indicated in Table 14 and the user must avoid bus contention on the port pins or it may affect device reliability.

Figure 13. Program Memory Map

address space. I/O ports are mapped as per the existing CMOS Z8. Figure 14. Register File

• ••

addresses the starting location of the active working-register group. Figure 15. Register Pointer *Note: RP = 00: Selects Register Group 0.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Functional Description Stack Pointer The Z8 features an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 120 general-purpose registers from 04h to 7Fh. General-Purpose Registers (GPR) These registers are undefined after the device is powered up. The registers keep their most recent value after any reset, as long as the reset occurs in the VCC volt- age-specified operating range. Register R254 is designated as a general-purpose register and is set to 00h after any reset or Stop-Mode Recovery. Counter/Timer There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or exter- nal clock sources; however, the T0 can be driven by the internal clock source only (Figure 16). The 6-bit prescalers divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that is loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt request IRQ4 (T0) or IRQ5 (T1) is gener- ated. The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters are also programmed to stop upon reaching zero (SINGLE-PASS mode) or to automatically reload the initial value and continue counting (MODULO-N CONTINUOUS mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 3. The TIMER mode register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or nonretriggerable, or used as a gate input for the internal clock. This step is bypassed if LOW EMI mode is selected. Note: Note:

disables the six interrupt requests (Table 15). rupt service routine for that particular interrupt request. Figure 16. Counter/Timers Block Diagram

Note: F = Falling edge triggered; R = Rising edge triggered. Figure 17. Interrupt Block Diagram

MHz max., with a series resistance (RS) of less than or equal to 100 Ohms. Figure 18. Oscillator Configuration A = STANDARD mode frequency.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Functional Description HALT Mode This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active. 56KΩ 552kHz 480kHz 330kHz 300kHz 185kHz 170kHz 23kHz 22kHz 20KΩ 1.4MHz 1MHz 884kHz 740kHz 500kHz 450kHz 65kHz 61kHz 10KΩ 2.6MHz 2MHz 1.6MHz 1.3MHz 980kHz 820kHz 130kHz 123kHz 5KΩ 4.4MHz 3MHz 2.8MHz 2MHz 1.7MHz 1.3MHz 245kHz 225kHz 2KΩ 8MHz 5MHz 6MHz 4MHz 3.8MHz 2.7MHz 600kHz 536kHz 1KΩ 12MHz 7MHz 8.8MHz 6MHz 6.3MHz 4.2MHz 1.0MHz 950kHz Table 17.Typical Frequency vs. RC Values—VCC = 3.3 V @ 25°C Load Capacitor Resistor (R) 33 pF 56 pF 100 pF 0.00 1µF ABABABAB 1.0MΩ 18 kHz 18 kHz 12 kHz 12 kHz 7.4 kHz 7.7 kHz 1 kHz 1 kHz 560 KΩ 30 kHz 30 kHz 20 kHz 20 kHz 12 kHz 12 kHz 1.6 kHz 1.6 kHz 220KΩ 70kHz 70kHz 47kHz 47kHz 30kHz 30kHz 4kHz 4kHz 100KΩ 150kHz 148kHz 97kHz 96kHz 60kHz 60kHz 8kHz 8kHz 56KΩ 268kHz 250kHz 176kHz 170kHz 100kHz 100kHz 15kHz 15kHz 20KΩ 690MHz 600kHz 463kHz 416kHz 286kHz 266kHz 40kHz 40kHz 10KΩ 1.2MHz 1MHz 860kHz 730kHz 540kHz 480kHz 80kHz 76kHz 5KΩ 2MHz 1.7MHz 1.5MHz 1.2MHz 950kHz 820kHz 151kHz 138kHz 1KΩ 7MHz 4.6MHz 5MHz 3.6MHz 3.6MHz 2.6MHz 660kHz 565kHz Notes: A = STANDARD mode frequency. B = LOW EMI MODE frequency. Table 16.Typical Frequency vs. RC Values—VCC = 5.0 V @ 25°C (Continued) Load Capacitor Notes: A = STANDARD mode frequency. B = LOW EMI mode frequency.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Functional Description The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the inter- rupt service routine, the program continues from the instruction after the HALT. On the C12 ICEBOX, the IRQ3 does not wake the device out of HALT mode. STOP Mode This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 µA. The STOP mode is released by a RESET through a Stop-Mode Recovery (pin P27). A LOW INPUT condition on P27 releases the STOP mode. Program execution begins at location 000C(Hex). How- ever, when P27 is used to release STOP mode, the I/O port mode registers are not reconfigured to their default POWER-ON conditions. Thus the I/O, configured as output when the STOP instruction was executed, is prevented from glitching to an unknown state. To use the P27 release approach with STOP mode, use the fol- lowing instruction: A Low level detected on pin P27 takes the device out of STOP mode, even if it is configured as an output. To enter STOP or HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. The user must execute a NOP (Op Code = FFh) immediately before the appropriate SLEEP instruction, such as: On the CCP emulator, a software workaround must be used to enable P27 as the Stop-Mode Recovery source. LD P2M, #1XXX XXXXB NOP STOP Note: X = Dependent on user's application. FFh NOP ; clear the pipeline 6Fh STOP ; enter STOP mode or FFh NOP ; clear the pipeline 7Fh HALT ; enter HALT mode Note: Note: Note:

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Functional Description Watch-Dog Timer (WDT) The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within every 1 T WDT period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z = 1, S = 0, V = 0. WDT = 5Fh Op Code WDT (5Fh) The first time Op Code 5Fh is executed, the WDT is enabled; subsequent execu- tion clears the WDT counter. This clearing of the counter must be performed at least every T WDT; otherwise, the WDT times out and generates a reset. The gen- erated reset is the same as a power-on reset of TPOR, plus 18 crystal clock cycles. The software enabled WDT does not run in STOP mode. Op Code WDH (4Fh) When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters—it just makes it possible to operate the WDT during HALT mode. A WDH instruction exe- cuted without executing WDT (5Fh) yields no effect. Permanent WDT Selecting the hardware-enabled Permanent WDT option bit automatically enables the WDT upon exiting reset. The permanent WDT always runs in HALT mode and STOP mode, and it cannot be disabled. On the CCP emulator, a software workaround must be used to enable the software- or hardware-enabled WDT. Auto Reset Voltage (VLV) The Z8 features an auto-reset built-in. The auto-reset circuit resets the Z8 when it detects the V CC below VLV. Figure 19 shows the Auto Reset Voltage versus tem- perature. If the VCC drops below the VCC operating voltage range, the Z8 functions down to the VLV unless the internal clock frequency is higher than the specified maximum VLV frequency. Note:

Figure 19. Typical Auto Reset Voltage (VLV) vs. Temperature Note: (1) applies to V LV in RUN and HALT modes. (2) applies to VLV in STOP mode.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY OTP Option Bit Description OTP Option Bit Description One-Time Programmable EPROM option bits for the device are described in this section. Low-EMI Emission. The Z8 can be programmed to operate in a low-EMI emis- sion (low-noise) mode by means of an EPROM programmable bit option. Use of this feature results in:

• All drivers slew rates are typically reduced to 10ns
• Internal SCLK and TCLK = crystal operation limited to a maximum of 4 MHz– 250 ns cycle time
• Output drivers typically exhibit resistances of 500 ohms
• Oscillator divide-by-two circuitry eliminated RC Oscillator. The RC Oscillator option bit, when programmed, enables the inter- nal RC oscillator to connect to the XOUT and XIN pins while disabling the internal crystal oscillator to XOUT and XIN. ROM Protect. ROM Protect fully protects the Z8 ROM code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported (Z86E02/E04/E08/E09 and Z86C02/C04/C08 do not support the instructions of LDE and LDEI). When the device is programmed for ROM Protect, the Low-Noise feature is not automatically enabled. Auto Latch Disable. Auto Latch Disable option bit, when programmed, globally disables all Auto Latches. Permanent WDT Enable. The hardware-enabled permanent WDT Enable option bit, when programmed, enables the WDT permanently after exiting reset. Unlike software-enabled WDT, the hardware-enabled permanent WDT cannot be stopped in HALT or STOP modes. 32-kHz Enable. The 32-kHz Enable option bit enables the 32-kHz oscillator circuit and disables the high-frequency crystal oscillator circuit. This option bit is disabled if the RC oscillator option bit is programmed.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Control Registers Control Registers Table 18.Timer Mode Register—R241 TMR F1h Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read, W = Write. Bit Position Bit Field R/W Reset Value Description 7–6 Reserved R/W 00 Reserved—must be 0 5–4 T IN Mode R/W 00 TIN Mode 00: External Clock Input 01: Gate Input 10: Trigger Input (nonretriggerable) 11: Trigger Input (retriggerable)

3 T1 Count R/W 0 T1 Count

0: Disable 1: Enable

2 T1 R/W 0 T1

0: No Function 1: Load T1

1 T0 Count R/W 0 T0 Count

0: Disable 1: Enable

0 T0 R/W 0 T0

0: No Function 1: Load T0

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Control Registers Table 19.Counter/Timer 1 Register—R242 T1 F2h Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Note: R = Read, W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description 7–0 T1 R X T1 Current Value W X T1 Initial Value Range = 1–256 decimal; 01h–00h Table 20.Prescaler 1 Register—R243 PRE1 F3h Bank 0h: WRITE ONLY Bit 7 6 5 4 3 2 1 0 R/W W W W W W W W W Reset X X X X X X 0 0 Note: W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description 7–2 Prescaler W X Prescaler Modulo Range = 1–64 decimal; 00h–01h

1 Clock W 0 Clock Source

0: T1 External Timing Input (TIN) Mode 1: T1 Internal

0 Count W 0 T1 Count Mode

0: Single Pass 1: Modulo N

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Control Registers Table 21.Counter/Timer 0 Register—R244 T0 F4h Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Note: R = Read, W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description 7–0 T0 R X T0 Current Value W X T0 Initial Value Range = 1–256 decimal; 00h–01h Table 22.Prescaler 0 Register—R245 PRE0 F5h Bank 0h: WRITE ONLY Bit 7 6 5 4 3 2 1 0 R/W W W W W W W W W Reset X X X X X X X 0 Note: W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description 7–2 Prescaler W X Prescaler Modulo Range = 1–64 decimal; 00h–01h

1 Reserved W X Reserved—must be 0

0 Count W 0 T0 Count Mode

0: Single Pass 1: Modulo N Table 23.Port 2 Mode Register—R246 P2M F6h Bank 0h: WRITE ONLY Bit 7 6 5 4 3 2 1 0 R/W W W W W W W W W Reset 1 1 1 1 1 1 1 1 Note: W = Write. Bit Position Bit Field R/W Reset Value Description 7–0 P20–P27 W 1 P20–P27 I/O Definition 0: Defines bit as Output 1: Defines bit as Input

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Control Registers Table 24.Port 3 Mode Register—R247 P3M F7h Bank 0h: WRITE ONLY Bit 7 6 5 4 3 2 1 0 R/W W W W W W W W W Reset X X X X X X 0 0 Note: W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description 7–2 Reserved W X Reserved—must be 0

1 Port 3 W 0 Port 3 Inputs

0: DIGITAL mode 1: ANALOG mode

0 Port 2 W 0 Port 2 Outputs

0: Open-Drain 1: Push-Pull Table 25.Port 0 and 1 Mode Register—R248 P01M F8h Bank 0h: WRITE ONLY Bit 7 6 5 4 3 2 1 0 R/W W W W W W W W W Reset X X X 0 X X 0 1 Note: W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description 7–5, 3 Reserved W X Reserved—must be 0

4 Reserved W 0 Reserved—must be 0

2 Reserved W X Reserved—must be 1

1–0 P02–P00 W 01 P02–P00 Mode 00: Output 01: Input

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Control Registers Table 26.Interrupt Priority Register—R249 IPR F9h Bank 0h: WRITE ONLY Bit 7 6 5 4 3 2 1 0 R/W W W W W W W W W Reset X X X X X X X X Note: W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description 7–6 Reserved W X Reserved—must be 0

5 IRQ3, IRQ5 W X IRQ3, IRQ5 Priority (Group A)

0: IRQ5 > IRQ3 1: IRQ3 > IRQ5 4,3,0 Interrupt W X Interrupt Group Priority 000: Reserved* 001: C > A > B 010: A > B > C 011: A > C > B 100: B > C > A 101: C > B > A 110: B > A > C 111: Reserved

2 IRQ0, IRQ2 W X IRQ0, IRQ2 Priority (Group B)

0: IRQ2 > IRQ0 1: IRQ0 > IRQ2

1 IRQ1, IRQ4 W X IRQ1, IRQ4 Priority (Group C)

0: IRQ1 > IRQ4 1: IRQ4 > IRQ1 Note: *Selecting a Reserved mode causes an undefined operation.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Control Registers Table 27.Interrupt Request Register—R250 IRQ FAh Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read, W = Write. Bit Position Bit Field R/W Reset Value Description 7–6 Reserved R/W 00 Reserved—must be 0

5 IRQ5 R/W 0 Interrupt

IRQ5 = T1 1: Interrupt pending 0: No interrupt pending

4 IRQ4 R/W 0 Interrupt

IRQ4 = T0 1: Interrupt pending 0: No interrupt pending

3 IRQ3 R/W 0 Interrupt

IRQ3 = P32 Input (rising edge) 1: Interrupt pending 0: No interrupt pending

2 IRQ2 R/W 0 Interrupt

IRQ2 = P31 Input 1: Interrupt pending 0: No interrupt pending

1 IRQ1 R/W 0 Interrupt

IRQ1 = P33 Input 1: Interrupt pending 0: No interrupt pending

0 IRQ0 R/W 0 Interrupt

IRQ0 = P32 Input (falling edge) 1: Interrupt pending 0: No interrupt pending

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Control Registers Table 28.Interrupt Mask Register—R251 IMR FBh Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 X X X X X X X Note: R = Read, W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description

7 Master

R/W 0 1: Enables global interrupts

6 Reserved R/W X Reserved—must be 0

5–0 IRQ0–IRQ5 R/W X 1: Enables IRQ0–IRQ5 (D0 = IRQ0) Table 29.Flag Register—R252 Flags FCh Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset X X X X X X X X Note: R = Read, W = Write, X = Indeterminate. Bit Position Bit Field R/W Reset Value Description

7 Carry R/W X Carry Flag

6 Zero R/W X Zero Flag

5 Sign R/W X Sign Flag

4 Overflow R/W X Overflow Flag

3 Decimal

2 Half Carry R/W X Half Carry Flag

1 User R/W X User Flag F2*

0 User R/W X User Flag F1*

Note: *Not affected by RESET.

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Control Registers Table 30.Register Pointer—R253 RP FDh Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read, W = Write. Bit Position Bit Field R/W Reset Value Description 7–4 Working Register Pointer R/W 0 Working Register Pointer 3–0 Reserved R/W 0 Must be 0 Table 31.General Purpose Register—R254 GPR FEh Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read, W = Write. Bit Position Bit Field R/W Reset Value Description 7–0 Stack R/W 0 General Purpose Register Table 32.Stack Pointer Low—R255 SPL FFh Bank 0h: READ/WRITE Bit 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Note: R = Read, W = Write. Bit Position Bit Field R/W Reset Value Description 7–0 Stack R/W 0 Stack Pointer Lower Byte (SP0–SP7)

Figure 22. 20-Pin SSOP Package Diagram

General-Purpose OTP MCU with 14 I/O LInes

Ordering Information

For fast results, contact your local ZiLOG Sales offices for assistance in ordering the part(s) required. Contact your local ZiLOG Sales office by navigating to Sales Office on www .zilog.com. Table 33.Ordering Information Pin Count Package Size (KB) Description 18 DIP 0.5 Z86E0212PSC1995 Z86E0212PEC1995

1 Z86E0412PSC1995

2 Z86E0812PSC1995

4 Z86E0912PSC1995

SOIC 0.5 Z86E0212SSC1995 Z86E0212SEC1995

1 Z86E0412SSC1995

2 Z86E0812SSC1995

4 Z86E0912SSC1995

20 SSOP 0.5 Z86E0212HSC1995 Z86E0212HEC1995

1 Z86E0412HSC1995

2 Z86E0812HSC1995

4 Z86E0912HSC1995

Note: *The Standard temperature range is 0ºC to 70ºC. For parts that operate in the Extended temperature range of –40ºC to 105ºC, substitute the letter E for the letter S. For example, the PSI number for an 18-pin DIP operating at 1 KB in the extended temperature range is Z86E0412PEC1995.

General-Purpose OTP MCU with 14 I/O LInes Part Number Description ZiLOG part numbers consist of a number of components. For example, part num- ber Z86E0412PSC1995 is a 12-MHz 18-pin DIP that operates in the –0ºC to +70ºC temperature range, with Plastic Standard Flow. The Z86E0412PSC1995 part number corresponds to the code segments indicated in the following table. Z70 .35Tµ Process The Z86E02/E04/E08/E09 family of parts are manufactured using ZiLOG’s new advanced Z70 .35Tµ process. This process no longer requires the conventional 12.5VDC programming voltage—it operates with only 5VDC. Please refer to the Programming Specification for further information. Special consideration must be made in existing designs with this new process. Please contact the ZiLOG World Wide Customer Support Center for further information. Precharacterization Product The products represented by this document are newly introduced; hence ZiLOG has not completed a full characterization of the product. This document states what ZiLOG knows about this product at this time; however, additional features or nonconformance with some aspects of this document may be found, either by ZiLOG or its customers, in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. ZiLOG, Inc.

910 East Hamilton Avenue, Suite 110

Campbell, CA 95008 Telephone (408) 558-8500 FAX 408 558-8300 Internet: www .zilog.com Z ZiLOG Prefix

86 Z8 Product

04 Product Number

12 Speed (MHz)

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Document Information Document Information Document Number Description The Document Control Number that appears in the footer of each page of this document contains unique identifying attributes, as indicated in the following table: Change Log PS Product Specification

0046 Unique Document Number

0401 Month and Year Published

01 03/01 Original issue K. Low, R. Beebe 02 04/01 Revise DC voltage specs K. Low, R. Beebe

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Index Index A–E Carry Flag 57 Change Log 63 Counter/Timer 0 53 Counter/Timer 1 52 Customer Feedback Form 63 Customer Information 63 Decimal Adjust Flag 57 Document Information 63 Document Number Description 63 External Timing Input 52 H–O Half Carry Flag 57 Interrupt Group Priority 55 IRQ0 55–56 IRQ1 55–56 IRQ2 55–56 IRQ3 55–56 IRQ4 55–56 IRQ5 55–56 Master Interrupt Enable 57 Overflow Flag 57 P–Z P3M 54 Part Number Description 62 Plastic Standard Flow 62 Port 2 Mode Register 53 Port 3 Mode Register 54 Precharacterization Product 62 Prescaler 0 Register 53 Prescaler 1 Register 52 Prescaler Modulo 52–53 Problem Description or Suggestion 63 Product Information 63 Return Information 63 Sign Flag 57 T0 Count 51 T1 Count 51 T IN 51–52 TIN Mode 51 Trigger Input 51 User Flags 57 Working Register Pointer 58 Zero Flag 57

General-Purpose OTP MCU with 14 I/O LInes PS004602-0401 PRELIMINARY Customer Feedback Form Customer Feedback Form Z86E02/E04/E08/E09 Product Specification If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Customer Information Product Information Return Information ZiLOG System Test/Customer Support 910 E. Hamilton Avenue, Suite 110, MS 4–3 Campbell, CA 95008 Fax: (408) 558-8536 Email: tools@zilog.com Problem Description or Suggestion Please provide a complete description of the problem or suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary. Name Country Company Phone Address Fax City/State/Zip E-Mail Serial # or Board Fab #/Rev. # Software Version Document Number Host Computer Description/Type