Z84C30AB6

Z84C30 STMICROELECTRONICS | Alldatasheet

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L577 SGS-:THOMSON MICROELECTRONICS Z84C30 Z80C CTC CMOS VERSION = FOUR INDEPENDENTLY PROGRAMMABLE COUNTERVTIMER CHANNELS, EACH WITH A — | READABLE DOWNCOUNTER AND A SE- ae LS | LECTABLE 16 OR 256 PRESCALER. DOWN- ™O 7 > COUNTERS ARE RELOADED ‘ VIS A AUTOMATICALLY AT ZERO COUNT ’ | = THREE CHANNELS HAVE ZERO COUNT/TI- 7 MEOUT OUTPUTS CAPABLE OF DRIVING DARLINGTON TRANSISTORS pines pip2e = SELECTABLE POSITIVE OR NEGATIVE TRIG- (Plaste) (Cerame) GER INITIATES TIMER OPERATION = STANDARD Z80C FAMILY DAISY-CHAIN IN- ~ TERRUPT STRUCTURE PROVIDES FULLY —— VECTORED, PRIORITIZED INTERRUPTS. WITHOUT EXTERNAL LOGIC. THE CTC MAY | ALSO BE USED AS AN INTERRUPT CON- TROLLER c « INTERFACE DIRECTLY TO THE Z80C CPU PLocaa OR-FOR BAUD RATE GENERATION - TO THE (Plastic) ace V+ 10% POWER SUPPLY (Ordering Information at the end of the datasheet) . + %. — = LOW POWER CONSUMPTION » Pee arene LOGIC FUNCTIONS | = LESS THAN 10 uA IN POWER DOWN | MODE » EXTENDED OPERATING TEMPERATURE : = 40°C TO +85°C on pan Pe rene f= = DESCRIPTION cou anne, fo The Z80C CTC four-channel counter/timer can be Paus ) +] reno tm | crannen programmed by system software for a broad range =] srawats of counting and timing applications. The four inde- pane boned ba pendently programmable channels of the CTC sat- Te penny isfy common microcomputer system requirements ~aefes. caxnns, }>— for event counting, interrupt and interval timing, and cowrmar J ~ =] cs: general clock rate generation. rom) spe see System design is simplified because the CTC con- * nects directly to both the CPU and the SIO with no oasy eacao additional logic. In larger systems, address de- maga {= wo coders and butters may be required comrnon (= 4 in Programming the CTC is straightforward : each ttt channel is programmed with two bytes : a third is the ono necessary when interrupts are enabled. Once cen ee started, the CTC counts down, reloads its time con: stant automatically, and resumes counting. Soft- ware timing loops are completely eliminated. September 1988 114

Figure 4 : Counter/ Timer Block Diagram. PROGRAMMING i Each Z80C CTC channel must be programmed Same prior to operation. Programming consists of writing two words to the VO port that corresponds to the desired channel The first wordis a control word that selects the oper- _| car ating mode and other parameters : the second word rena sus constanr is a time constant, which is a binary data word with a value from 1 to 256. A time constant word must be preceded by a channel control word. Atter initialization, channels may be reprogrammed zero at any time. If updated contro! and time constant euxtna ————] words are written to a channel during the count oper- | ation, the count continues to zero before the news coe time constant is loaded into the counter. If the interrupt on any CTC channel is enabled, the programming procedure should also include an in- loaded into the down-counterwhenthe counter/time _teFrupt vector. Only one vector is required for all four channel is initialized, and subsequently after each Channels, because the interrupt logic automatically zero count. modifies the vector for the channel requesting ser- vice. PRESCALER A contro! word is identified by a 1 in bit 0. A 1 in Gai paler uments used omy int imer mode, bit 2 indicates a time constant word is to follow. In behets 36 The prescaler outpct Clocks the ‘@tTupt vectors are always addressed to Channel 0, down-counter during timer operation. The effect of 24 'dentified by a 0 in Bit 0. the rescaler onthe down-counteris amultplicaton ADDRESSING of the system clock period by 16 or 256. The pres: - n uring programming, channels are addressed with cater factor is Programmed by bit § of the channel the channel select pins CS: and CS». A2-bit binary . code selects the appropriate channel as shown in DOWN COUNTER the following table Prior to each count cycle, the down-counter is [Channel| <GS: ‘| CSo | loaded with the time constant register contents. The 0 0 counter is then decremented one of two ways, de- 1 0 pending on operating mode 2 ty = By the prescaler output (timer mode) 3 1 = By the trigger pulses into the CLK/TRG input (counter mode) RESET i The CTC has both hardware and software resets. Without disturbing the down-count, the CPU can read the count remaining at any time by performing The hardware reset terminates all down-counts and an U/O read operation at the port address assigned _ Sables all CTC interrupts by resetting the interrupt fo the CTC channel. When the down-cocnter bis in the control registers. In addition, the ZO/TO reaches the zero count, the ZC/TO output gener- 7d Interrupt outputs go inactive, IEO reflects IEI, ates a positive-going pulse. When the interrupt 294 DoD” go to the high-impedance state. All chan- is enabled, zero count also triggers an interrupt re- ‘N8lS must be completely reprogrammed after a quest signal (INT) from the interrupt logic. hardware reset. 7 The software reset is controlled by bit 1 in the chan- nel control word. When a channel receives a soft- aia 7 SSS:THoMsoN SY/ incroascrecwcs

ware reset, it stops counting. When asoftware reset _the timer is triggered automatically. The time con- is used, the other bits in the control word also stant word is programmed during an I/O write oper- change the contents of the channel control register. _ation, which takes one machine cycle. At the end of Aiter a software reset a new time constant word the write operation there is a setup delay of one must be written to the same channel clock period. The timer starts automatically (decre- If the channel control word has both bits D1 and Dz ments) on the rising edge of the second clock pulse set to 1, the addressed channel stops operating, __(T2) of the machine cycle following the write oper- pending a new time constant word. The channel is _ation. Once started, the timer runs continuously. At feady to resume after the new constant is pro. 2ef0 Count the timer reloads automatically and con- grammed. In timer mode, if Ds = 0, operations trig- __iues counting without interruption or delay, until gered automatically when the time constant word is Stopped by a reset. loaded. When Ds is set to 1, the timer is triggered externally through the CLK/TRG input. The time constant word CHANNEL CONTROL WORD PROGRAMMING is programmed during an I/O write operation, which The channel control word is shown in figure 5. It sets takes one machine cycle. The timer is ready for the modes and parameters described below. operation on the rising edge of the second clock Interrupt Enable. Dz enables the interrupt, so that pulse (T2) of the following machine cycle. Note that an interrupt output (INT) is generated at ero count. _the first timer decrement follows the active edge of Interrupts may be programmed in either mode and the CLK/TRG pulse by a delay time of one clock may be enabled or disabled at any time. cycle if a minimum setup time to the rising edge of clock is met. If this minimum is not met, the delay is OPERATING MODE extended by another clock period. Consequently, De selects either timer or counter mode. for immediate triggering, the CLK/TRG input must Prescaler factor (Timer Mode Only). Ds selects fac- precede Tz by one clock cycle plus its minimum tor-either 16 or 256. setup time. If the minimum time is not met, the timer i if . Trigger slope. Ds selects the active edge or slope of__Wll Start on the third clock cycle (Ts) the CLK/TRG input pulses. Note that reprogramm- Once started the timer operates continuously, with- ing the CLK/TRG slope during operation is equival- out interruption or delay, until stopped by a reset ent to issuing an active edge. If the trigger slope is Time constant to follow. A 1 in Dz indicates that the changed by a control word update while a channel _ next word addressed to the selected channel is a is pending operation in timer mode, the result is the time constant data word for the time constant regis- same as a CLK/TRG pulse and the timer starts. ter. The time constant word may be written at any Similarly, if the channel is in counter mode, the time. counter decrements. 0 in De indicates no time constant word is to fol- Trigger mode (timer mode only). D3 selects the trig- low. This is ordinarily used when the channel is al- ger mode for timer operation. When Dsis reset to0, ready in operation and the new channel control word Figure 5 : Channel Control Word... + ewancesintennurt | 9 Necro OOISABLES inTERMUPT = ContnoL woro

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IEO. interrupt Enable Out (output, active High). High WRITE CYCLE TIMING only if IEl is High and the CPU is not servicing anin- Figure 10 shows write cycle timing for loading con- terrupt from any CTC channel. IEO blocks lower trol, time constant or vector words. priority devices from interrupting while a higher priority interrupting device is being serviced. The CTC does not have a write signal input, so it Laan generates one internally when the read (RD) input INT. Interrupt Request (output, open drain, active ig High during Ts. During Tz IORQ and CE inputs Low). Low when any CTC channel that has been —_ are Low. M1 must be High todistinguisha write cycle programmed to enable interrupts has a zero-count —_ from an interrupt acknowledge. A 2-bit binary code condition in its down-counter. atinputs CS: and CSo selects the channel to be ad- TORQ. Input/Output Request {input from CPU, ac- _ dressed, and the word being written is placedon the tive Low). Used with CE and AD totransferdataand data bus. The data word is latched into the appro- channel control words between the CPU and the _ priate register with the rising edge of clock cycle Ts. CTC. During a write cycle IORQ and CE are active and RD inactive. The CTC does not receive a spe- ‘TIMER OPERATION cific write signal ; rather, it internally generates its __In the timer mode, a CLK/TRG pulse input starts the own from the inverse of an active RD signal. Ina __ timer (figure 11) on the second succeeding rising read cycle, IORQ, CE and RD are active ;the con. tents of the down-counter are read by the CPU. If Figure 8: A Typical Z60C Environment. 1ORQ and M1 are both true, the CPU is acknow- ledging an interrupt request, and the highest priority interrupting channel places its interrupt vector on the data bus. Mi. Machine_Cycle One (input from CPU, active Low). When Mi and IORQ are active, the CPU is Set acknowledging an interrupt. The CTC then places an interrupt vector on the data bus if it has highest priority, and if a channel has requested an interrupt (INT) | KY RD. Read Cycle Status (input, active Low). Used in nal P10 conjunction with IORQ and CE to transfer data and i channel control words between the CPU and the ai CTC. RESET. Reset (input active Low). Terminates all 7 down-counts and disables ail interrupts by resetting a 1 the interrupt bits in all control registers ; the ZC/TO T | and the Interrupt outputs go inactive ; IEO reflects a | | IE! ; D0-D7 go to the high-impedance state. ena, | cre ZC/TOo-2C/TO2, Zero Count/Timeout (output, ac- 7 zertonint tive High). Three ZC/TO pins corresponding to CTC 0 channels 2 through 0 (Channel 3 has no ZC/TO pin) In both counter and timer modes the output is an ac- =e a tive High pulse when the down-counter decrements one wo to zero. | ace TIMING anes READ CYCLE TIMING vin] — | or Figure 9 shows read cycle timing. This cycle reads 30 oma the contents of a down-counter without disturbing the count. During clock cycle Ta, the CPU initiates a KY Ky read cycle by driving the following inputs Low : RD, IORQ, and CE. A 2-bit binary code at inputs CS+ and CS selects the channel to be read. M1 must be High to distinguish this cycle from an interrupt ac- knowledge. No additional wait states are allowed. oy scstomson SY jcnosarraowics

Z84C30 $$ Figure 9 : Read Cycle Timing. The ZC/TO output occurs immediately after zero count, and follows the rising CLK edge. a Figure 11 : Timer Mode Timing. me —_Y AUT Figure 10 : Write Cycle Timing. Figure 12 : Counter Mode Timing. ~ | INTERRUPT OPERATION edge of CLK. The trigger pulse is asynchronousand The CTC follows the Z80C system interrupt proto- itmust have a minimum width. A minimum leadtime —_¢o| for nested priority interrupts and return from in- (210 ns) is required between the active edge of the _terrupt, wherein the interrupt priority of a peripheral CLK/TRG and the next rising edge of CLK to enable —_ig determined by its location in a daisy chain. Two the prescaler on the following clock edge. If the _jines-IEI and IEO-in the CTC connect it to the sys- CLK/TRG edge occurs closer than this, the initiation tem daisy chain. The device closest to the +5 V sup- of the timer function is delayed one clock cycle. This _ply has the highest priority (figure 13). For additional corresponds to the startup timing discussed in the _ information on the Z80C interrupt structure, refer to programming section. The timercanalsobestarted the 780 CPU Technical Manual. automatically if so programmed by the channel con- trol word. Figure 13 : Daisy-chain Interrupt Priorities. COUNTER OPERATION. In the counter mode, the CLK/TRG pulse input de crements the downcounter. The trigger is asyn- chronous, but the count is synchronized with CLK. vmontay pny cowesy gnome For the decrement to occur onthe next risingedge —|sv _ sets _ownces_ senses ste? of CLK, the trigger edge must precede CLK bya t= fu wftfa wp fe wp=fe op minimum lead time as shown in figure 12. If the lead time is less than specified, the count is delayed by ‘one clock cycle. The trigger pulse must have a mini- mum width, and the trigger period must be at least twice the clock period. L577 Scs:THOMsoN —

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AC CHARACTERISTICS (continued) [zeacsoa | zeacson | flee | oe eee { (ns) [1 | ToC | Clock Cycle time | ects | [2 | Twon | Glock wieth (high) | tos | ws a [tact] Giek Wat cow) tos es [4] tie [Cock Fartime To Po [s[ te [Cockrisetime TT Pt je[ th [aitoatimes CP [7 | scsi) [esto clock t seuptime Treo | | too | [8] TsCe() [CE to Clock TSeuptime | t80 (| | 100 | [a | tsio() | TORGL to Clock * SeupTime | ts | | too | [so | TsD() | AD. 1 to Glock TSewp Time | ts [To 11] “TéGiBO) [Clock T to Data Out Delay TT 200 T1830 | TaC(00z)_| 1ORO, RD 7 to Data Float [| io |) | | 13[ TsDIC) | Data into Clock * SetupTime —~~S*«YL~SC sd t Het tame tis Seat Spee “sf —}- +. Pee eee | tet | =| (interrupt immediately preceding Mi) [16] TaiO(OH | TORG! to Data Out Delay (INTA cycle) || to (| tio [17] ToieWe0n |eivweOl dey tc | t00 [18 TaieiEGy [VEIT 10 OT Belay atter EO decodes) |_| eo (| to | [19 | TacanT) [Glock TtoINTI Delay | intecetao] nrtecs 20] ee" lemem | esl tsCTR(C) satisfied 7 ToC+160 TeC+160 | tsCTR(C) not satistied 2TeC+370) 2TeC+370| [a1] TeoTR | CLKTAG Cycio Time tap atoo | | a 40 | [22] TroTR | CuKTRG Rise Time | | 80 Tw a[ mem [comer OT eT teeters" tt | [2s | tworrn | CLWTRGWietn righ) | zon | | to | [me [eemecrera eT fee] for] for immediate Count [7] RO [img st Penaerotomgcot |S] LOM] for enabling of Prescaler on following Clock Seto eae) 2g | Tac(zc/TOH) | Clock J to ZC/TO J Delay io [| | 140 | Notes :1. Timer mode 2. Counter mode 124 57 S88:THOMSON <0 SUGROBLECTRORICE

symbol [Parameter Value | Unit | Voc Supply Voltage with Respect to Vss = 05 10 Veo +08 Soldering Temperature (soldering time 10 seo) [200d Operating Temperature = 40 to 85 ct) DC CHARACTERISTICS (1) Cock nput Low Votage | Sit 08) P08 | V Clock input High Votage | New 0) Meo + 0] V Vit Input Low Voltage v (except CLK) Vin Input High Voltage 22 Vee v (except CLK) . {Vou | Output Low Voltage lo = 2.0 mA [ - | [oa | v | Voxr | Output High Voltage (1) lon = — 1.6 mA | - | v Voue | Output High Voltage (2) lou =~ 250 HA Wec- oe - | Vv [tu | Input Leakage Current Vss £ Vin < Voc = nA [te 3-State Output Leakage Vss + 0.4 < Vout < Veo +10 | pA Current in Float Ices Power Supply Current

4 MHz Vcc =5 V, CLK = 4 MHz 2 5 mA

6 MHz Vin = Veo — 0.2 V, Vi = 0.2 V 4 7 mA Icce | Stand-by Supply Current Vee =5 V, CLK = Voc 70 | pA Vin = Voc = 0.2 V Vu =02V Note: 1. Applied to ZC/TO:, 2C/TO; and ZC/TO2. TEST CONDITIONS Ta=-40°C to + 85°C driven at Vec-0.6 V for a logic "1" and 0.6 V for Voc =5V +10% a logic "0". ce = Timing measurements are made at 2.2 V for a Vss = 0 V. logic "1" and 0.8 V for a logic "0". AC TEST CONDITIONS. All AC parameters assume a load capacitance of = Inputs except CLK (clock) are driven at 2.4Vfor 100 pF. alogic "1" and 0.4 V fora logic "0". Clock input is Gy 8cs:THomson 13/14 BSG innctoczscrzcc | oT

ORDERING INFORMATION

[Tye | Peekage [Temps [Gack | —Beeciption Z84C30AB6 DIP-28 (plastic) —40/+ 85°C Z80C Counter Z84C30AD6 | DIP-28 (ceramic) —40/+ 85°C 4MHz Timer Control Z84C30AD2 | DIP-28 (ceramic) — 55/ + 125°C CMOS Version Z84C30AC6 | PLCC44 (plastic chip-carrier) -40/+ 85°C Z84C30BB6 | DIP-28 (plastic) —40/+ 85°C Z84C30BD6 | DIP-28 (ceramic) —40/+ 85°C Z84C30BD2 | DIP-28 (ceramic) —55/ + 125°C Z84C30BC6 | PLCC44 (plastic chip-carrier) 40/+ 85°C a & SGS-THOMSON 20