Z84C20AB6 | DigiCamel IC Datasheet

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= PROVIDES A DIRECT INTERFACE BETWEEN 8

280 MICROCOMPUTER SYSTEMS AND PE- — |

RIPHERAL DEVICES — Pm = BOTH PORTS HAVE INTERRUPT-DRIVEN " 7 HANDSHAKE FOR FAST RESPONSE iy: «FOUR PROGRAMMABLE _ OPERATING ‘ " ‘ | MODES : BYTE INPUT. BYTE OUTPUT, BYTE INPUT/OUTPUT (port A only), AND BIT B D INPUT/OUTPUT | DIP-40 DIP-40 = PROGRAMMABLE INTERRUPTS ONPERIPH- Plastic) (Ceramic) ERAL STATUS CONDITIONS | | = STANDARD Z80 FAMILY BUS-REQUESTAND | ~ PRIORITIZED INTERRUPT-REQUEST DAISY | /> CHAINS IMPLEMENTED WITHOUT EXTER- | NAL LOGIC | « THE EIGHT PORT B OUTPUTS CAN DRIVE i DARLINGTON TRANSISTORS (1.5 mA at c | 1,5 V) PLCC44 | # SINGLE 5 V = 10 % POWER SUPPLY (Plastic) = LOW POWER CONSUMPTION : {Ordering Information at the end of the datasheet) ~ 2mAtyp. at 4MHz ed - 3mAtyp. at 6 MHz = less than 10 uA in Power Down mode | ~UNCTIONG = EXTENDED OPERATING TEMPERATURE : LOGIC FUNCTIONS | = 40°C TO+85°C DESCRIPTION om} Do “b= The Z80C PIO Parallel I/O Circuit is a programm- ms) slo. Pe pamee able, dual-port device that provides a TTL-com- Te i Da a patible interface between peripheral devices and fe ” the CPU. The CPU configures the PIO to interface deen nor with a wide range of peripheral devices with no other —leran Sup external logic. Typical peripheral devices that are wo compatible with the PIO include most keyboards, eomrnat | 1 aero paper tape readers and punches, printers, PROM iene oy Poe programmers, etc. —y|" ae ‘One characteristic of the Z80 peripheral controllers | Yee By rons that separates them from other interface controllers ene bal is that all data transfer between the peripheral de- lew — vice and the CPU is accomplished under interrupt sno |} —— Thus, the interrupt logic of the PIO permits full use comms 60 | of the efficient interrupt capabilities of the CPU dur- | ing /O transfers. Alll logic necessary to implement a fuily nested interrupt structure is included in the PIO. September 1988 Wi4

—_—_Y A 288020 Data outputs are controlled by the CPU andcan be —_ register specifies which of the bits in the port are ac- writen or changed at any tine. tive and which are masked or inactive. = Individual bits can be masked off The mask control register specifies two conditions : = The handshake signals are not used in Mode 3, first, whether the actve state ofthe input bits is High Ready is held Low, and Strobe is disabled or Low, and second, whether an interrupt is gener- = When using PIO interrupts, the CPU interrupt ated when any one unmasked input bit is active (OR mode must be set to Mode 2. condition) or if the interrupt is generated when all unmasked input bits are active (AND condition). INTERNAL STRUCTURE The internal structure of the Z80C PIO consists ofa !NTERRUPT CONTROL LOGIC CPU bus interface, internal control logic, Port A /O The interrupt control logic section handles all CPU logic, Port B W/O logic, and interrupt control logic _interrupt protocol for nested-priority interrupt struc- (figure 3). The CPU bus interface logic allows the _tures. Any device's physical location ina daisy-chain PlO to interface directly to the CPU withnootherex- configuration determines its priority. Two lines (IEI ternal logic. The internal control logic synchronizes and IEO) are provided in each PO to form this daisy the CPU data bus to the peripheral device interfaces chain. The device closest to the CPU has the hig- (Port A and Port B). The two /O ports (AandB) are —_hest priority. Within a PIO, Port A interrupts have virtually identical and are used to interface directly __higher priority than those of Port B. In the byte input, to peripheral devices. byte output, or bidirectional modes, an interrupt can be generated whenever the peripheral requests a PORT LOGIC new byte transfer. In the bit control mode, an inter- Each port contains separate input and output regis- rupt can be generated when the peripheral status ters, handshake contro! logic, and the control regis- matches a programmed value. The PIO provides for ters shown in figure 4. All data transfers between complete control of nested interrupts. That is, lower the peripheral unit and the CPU use the data input _ priority devices may not interrupt higher priority de- and output registers. The handshake logic associ _vices that have not had their interrupt service rou- ated with each port controls the data transfers __ tines completed by the CPU. Higher priority devices through the input and the output registers. The May interrupt the servicing of lower priority devices. mode control register (two bits) selects one of the Ifthe CPU (in interrupt Mode 2) accepts an interrupt, four programmable operating modes. the interrupting device must provide an 8-bit inter- The control mode (Mode 3) uses the remainingreg- __rupt vector for the CPU. This vector forms a pointer isters. The input/output control register specifies to a location in memory where the address of the in- which of the eight data bits in the port are tobe out- __terrupt service routine is located. The 8-bit vector puts and enables these bits ; the remaining bits are _from the interrupting device forms the least signifi- inputs. The mask register and the mask controlreg- _cant eight bits of the indirect pointer while the | Reg- ister contro! Mode 3 interrupt conditions. The mask _ister in the CPU provides the most significant eight Figure 3 : Block Diagram. em Bourn. ramossane a) wi4 OT Se.

Figure 4 : Typical Port /O Block Diagram. seeeite | ina am, >| f=}Hs een | = Used in the bit mode only to allow generation of an interrupt ifthe peripheral I/O pins go to the spacitied state bits of the pointer. Each port (A and) has an inde- —_chronizes the port operations, controls the port pendent interrupt vector. The least significant bit of mode, port addressing, selects the read/write func- the vector is automatically setto 0 within the PIO be- tion, and issues appropriate commands to the ports cause the pointer must point to two adjacent mem- —_and the interrupt logic. The PIO does not receive a ory locations for a complete 16-bit address write input from the CPU ; instead, the RD, CE, C/D iOR Is generate th in nal Unike the other ZB0C peripherals, the PIO does not "4 |ORA signals generatethe write input internally enable interrupts immediately after programming. It waits until MI goes Low (e.g., during an opcode PROGRAMMING fetch). This condition is unimportantin the Z80C en- MODE 0, 1, OR 2. vironment but might not be if another type of CPU : ; is used. (Byte Input, Output. or Bidirectional). Programming a port for Mode 0, 1, or 2 requires two words per The PIO decodes the RET! (Retum From Interupt) port. These words are instruction directly from the CPU data bus so that each PIO in the system knows at all times whether AMODE CONTROL WORD. Selects tne port oper” itis being serviced by the CPU interrupt service rou- 2179 mode (figure 5). This word may be written any tine. No other communication with the CPU is re. "™@- quired. AN INTERRUPT VECTOR. The Z80C PIO is de- signed for use with the Z80C CPU in interrupt CPU BUS I/O LOGIC Mode 2 (figure 6). When interrupts are enabled, the The CPU bus interface logic interfaces the PIO di PIO must provide an interrupt vector. rectly to the CPU so no extemal iogic is necessary. WQDpE 3 For | tems, however, addr For ae customs, owever. adaress 6000'S (Bi inpuy Output). Programming a por for Mode 3 operation requires a control word, a vector (if inter- INTERNAL CONTROL LOGIC rupts are enabled), and three additional words, de- This logic receives the control words for each port —_Scribed as follows : during programming and, in turn, controls the oper- 0 REGISTER CONTROL. When Mode 3 is se- ating functions of the PIO. The control logic syn- _iected, the mode control word must be followed by ang ey ses-tHomson SY imcroarcrremes

Ao-Az. Port A Bus (Bidirectional, 3-state). This 8-bit__ BRDY. Register B Ready (Output, Active High). This bus transfers data, status, or controlinformation be- _signal is similar to ARDY, except that in the Port A tween Port A of the PIO and a peripheral device. Ao _ bidirectional mode this signal is High when the Port is the least significant bit of the Port A data bus. A input register is empty and ready to accept data ARDY. Register A Ready(Output, Active High). The _from the peripheral device. meaning of this signal depends on the mode ofoper- _ BSTB. Port B Strobe Pulse From Peripheral Device ation selected for Port A as follows : (Input, Active Low). This signal is similar to ASTB, OUTPUT MODE. This signal goes active to indicate xcept that in the Port A bidirectional mode this sig- that the Port A output register has been loaded and _nal strobes data from the peripheral device into the the peripheral data bus is stable andready fortrans- Port A input register. fer to the peripheral device. C/D. Control Or Data Select (Input, High = C). This INPUT MODE. This signal is active when the Port _pin defines the type of data transfer to be performed input register is empty and ready to acceptdatafrom between the CPU and the PIO. A High on this pin the peripheral device. during i oP uit to the PIO causes the Gata bus BIDIRECTIONAL MODE. This signal is active when {be interpreted as a command for the port selectes data is available in the Port A output register for by the BVA Select ine. A Low on this pin means that transfer to the peripheral device. In this mode, data _tNe data bus is being used to transfer data between ig not placed on the Port A data bus, unless ASTB tne CPU and the PIO. Otten address bit Ar from the is active. CPU is used for this function. . ; CE. Chip Enable (Input, Active Low). A Low on this CONTROL MODE. This signal is disabled and, enables the PIO to accept command or data in ASTB. Port A Strobe Pulse From Peripheral De puts from the CPU during a write cycle or to trans- . Port A Strobe Pulse From Peripheral Device mit data to the CPU during a read cycle. This signal (Input, Active Low). The meaning of this signal de- _ ig generally decoded from four I/O port numbers for pends onthe mode of operation selected for PortA Ports A and B, data, and control as follows : CLK. System Clock (Input). The Z80C PIO uses the OUTPUT MODE. The positive edge of this strobe is standard single-phase Z80C system clock. issued by the peripheral to acknowledge the receipt. 5.7. CPU Data Bus (Bidirectional, 3-state). This of data made available by the PIO. bus is used to transfer all data and commands be- INPUT MODE. The strobe is issued by the periph- tween the CPU and the PIO. Do is the least signifi- eral to load data from the peripheral into the PortA cant bit. input register. Data is loaded into the PIO when this 41. interrupt Enable In (Input, Active High). This sig- signal is active. nal is used to form a priority-interrupt daisy chain BIDIRECTIONALMODE. When this signalis active, when more than one interrupt-driven device is being data from the Port A output register is gated onto _ used. A High level on this pin indicates that no other the Port A bidirectional data bus. The positive edge devices of higher priority are being serviced by a of the strobe acknowledges the receipt of the data. CPU interrupt service routine. CONTROL MODE. Thestrobe is inhibited internally. EO. Interrupt Enable Out (Output, Active High). The Bo-Br. Port B Bus (Bidirectional, 3-state). This 8-bit _ 'EO signals the other signalrequired to form a daisy bus transfers data, status, or control information be- chain priority scheme. It is High only if IE! is High tween Port B and a peripheral device. The Port B and the CPU is not servicing an interrupt from this data bus can supply 1-5mA at 1.5V to drive Daring. PIO: Thus this signal blocks lower priority devices ton transistors. Bo is the least significant bit of the ‘0m interrupting while a higher priority device is bus. being serviced by its CPU interrupt service routine. sa a cae ___ INT. Interrupt Request (Output, Open Drain, Active B/A, Port B Or A Select (Input, High = B). This pin : defines which port is accessed during a data trans- Low). When INT isactve the PIO is requesting an fer between the CPU and the PIO. ALowonthis pin erupt : selects Port A; a High selects PortB. Often address !0RQ. Input/Output Request (Input from CPU, Ac- bit Ao from the CPU is used for this selection func- _ tive Low). IORQis used in conjunction with B/A, C/D, tion. CE, and RD to transfer commands and data be- Ota B57 SES:THOMSON

tween the CPU and the PIO. When CE, AD, and going edge of CLK, indicating data is available. IORQ are active, the port addressed by B/A trans- Ready stays active until the positive edge of the fers data to the CPU (a read operation). Converse- strobe line is received, indicating that data was ly, when CE and IORQ are active but RD is not, the taken by the peripheral. The positive edge of the port addressed by B/A is written into from the CPU _strobe pulse generates an INT if the interrupt enable with either data or control information, as specified _ flip-flop has been set and if this device has the hig- by CID. Also, if IORQ and Mi are active simulta- _hest priority. neously, the CPU is acknowledging an interrupt ; the interrupting port automatically places its interrupt INPUT MODE (MODE 1) f vector on the CPU data bus if itis the highest priority tea pone seer igure is nme into mre device requesting an interrupt. ing edge of strobe activates INT, if Interrupt Enable Mi. Machine Cycle (Input from CPU, Active Low). _is set and this is the highest-priority requesting de- This signal is used as a sync pulse to control sev- _vice. The following falling edge of CLK resets Ready eral internal PlO operations. When both the Mt and —_to an inactive state, indicating that the input register RD signals are active, the CPU is fetching an in- is full and cannot accept any more data until the CPU struction from memory. Conversely, when both M1 — completes a read. When a read is complete, the and IORQ are active, the CPUis acknowledging an positive edge of RD sets Ready at the next Low- interrupt. In addition, M1 has two other functions going transition of CLK. At this time new data can within the PIO: it synchronizes the PIO interrupt be loaded into the PIO. logic ; when M1 occurs without an active RD or IOR@ signal, the PIO is reset. Selliadbabielarnuiars 2 1 i. = . is is a combination of Modes 0 and 1 using all four RD. Read Cycle Status (Input from CPU, Active handshake lines andthe eight Port A I/O lines (figure Low). ILRD is active, or an VO operation is in pro- 4). Port B must be set to the bit mode and its in- gress, RD is used with B/A, C/D, CE, and IORQ 10 guts must be masked. The Port A handshake lines transter data from the PIO to the CPU. are used for output control and the Port B lines are used for input control. If interrupts occur, Port A’s TIMING vector will be used during port output and Port B's The following timing diagrams show typical timing in _Will be used during port input. Data is allowed out aZ80C CPU. envirernment For more precise spec ‘onto the Port A bus only when ASTB is Low. The fications refer to the composite ac timing diagram. _"'sing edge of this strobe can be used to latch the Waite cycle data into the peripheral. Fi : ; . BIT MODE (MODE 3) igure 11 illustrates the timing for programming the ; j 2B0C PIO oF for writing data to one of its ports. No bit mode does not utilize the handshake signals, Wait states are allowed for writing to the PIO other 27. anormal port write or port read can be executed than the automatically inserted Twa. The PIO does any time. When writing, the data is latched into not receive a specific write signal; itinternallygener- _ te output registers with the same timing as the out- ates its own from the lack of an active RD signal. Put mode (figure 16). CYCLE When reading the PIO, the data returned to the CPU READ is composed of output register data from those port Figure 12 illustrates the timing for reading the data __data lines assigned as outputs and input register input from an external device toone of the PIOports. data from those port data lines assigned as inputs. No Wait states are allowed for reading the PIO other —‘ The input register contains data that was present than the automatically inserted Twa. immediately prior to the falling edge of RD. An inter- rupt is generated if interrupts from the port are en- OUTPUT MODE (MODE 0) abled and the data on the port data lines satisty the An output cycle (figure 13) is always started by the logical equation defined by the 8-bit mask and 2-bit ‘execution of an output instruction by the CPU. The mask control registers. However, if Port A is pro- WR pulse from the CPU latches the data fromthe grammed in bidirectional mode, Port B does not CPU data bus into the selected port's output regis-__issue an interrupt in bit mode and must therefore be ter. The WR” pulse sets the Ready flag afteraLow- _polled. G57 SSS:THOMSON ze TK RncomBcTROICZ

Figure 17 : Interrupt Acknowledge Timing wae] [6 [=| |» | ax ame Sene wo —\\ Figure 18 : Return From Interrupt. ew PLPLLULL Pn = /——- a eT \\ SNS over a ue a

104 K57 888:THomson —__ _

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AC CHARACTERISTICS (continued) [zsaGa0n |z040208 | a siete (ns) (ns) | (ns) [i [tec [Glock GycieTime aco] te | [2 [wor | Cleo wiah igh) 08 as || Fs [two | Cloc With on) 08 | es | [4[ tie [clock Fan time go ff 20 | [s| we | coxniseTime co | 2 [e[ Rosia) | 6. 8A COWARD RODS Tme Si [r[ th | Ary Ho Times for pected Seup time [<0] [| | [| Ten) | FO. TORG to ook T Setup Time p18] 70] | [| Tero) R0-10RG 1 Yo Osta Out Dey SS) ——id 0 | [10] Tar1(005) | RO-TORG To Data Ou Foat Boay || v0) | 70 | [ai[ Ts0u6) | Datainto clock TSeuptime so Tf co || [12] Téio(OoH) | TORG to Data Out Delay INTACK Cycle) | 160 || 120 | [sa | temucn [Mitte GlockTSeuptime co To [| [ra] Tawiion [MIT te Clock U Setup Time Micycie) To To | | [15] Tamideo) | Mi! to 101 Delay (interruptimmediately preceding MIL) | [180 | 100 | [16 | Tst€O) | tet to ORG! Setup Time (NTACK Cycle) taf too | | [a7] roreweon [ieiLiool belay ta 120 | [18 TaIEIMEOH | EIT io OT Delay (after ED decode) | te] 180 | ep eae eee Ll (to activate READY on Next Clock Cycle) [eo] TagiROVD | Clock | to READY T Oey Sn || [2t| TecROV [Clock VioREADY I Delay | go] sz | [ee] tTwst@ | STROBE Puse wan Sao |e Pe cere, LIL (to activate READY on Next Clock Cycle) [24] Teio(Po) | 1ORG T to PORT DATA Stable Delay (Modeo) || te |_| 160 | [25| TsPOSTB) | PORT DATA to STROBE T Setup Time (Mode 1) ago] | 190 | [as TaSTE(PD) | STROBE | to PORT OATA Stable (Mode 2) ———~|_—‘|aia| | 189] [ar TasTaeon | STROBE T10 PORT DATA Feat Dey (Moc 2) || 1¢0| | 160] [28 TePount) | PORT DATA Maich to INT J Deiy Mode 2) | 490 | 90] tes] Tasraanty | STROBE Tio NTS ely SSS tao | 88 |

124 Gy S6S-THOMSON

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4 MHz Vee = 5 V, CLK = 4 MHz - 2 5 mA

6 MHz Vin =Voo~02V, Vn =02V| - 3 8 | ma

lece | Stand-by Supply Current Voc =5 V, CLK = Voc = 70 | WA Vin =Voo 02 V Vii =02V Notes : 1. * Applied to Por B ony 2. Typical value is specified at 25 ‘C. TEST CONDITIONS Ta=-40°C to + 85°C driven at Voc — 0.6V for a logic "1 and 0.6V for Voc = BV + 10% a logic "0". Vss = OV = Timing measurements are made at 2.2V for a logic "1" and 0.8V for a logic "0". AC TEST CONDITIONS All AC parameters assume a load capacitance of = Inputs except CLK (clock) are driven at 2.4V for 100pF. a logic "1" and 0.4V for a logic "0". Clock input is SY incrosscmomes

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Z84C20AB6 specifications and overview.

Summary

Z80C PIO CMOS VERSION

Description

Z80C PIO CMOS VERSION

Source title Z84C20AB6 Datasheet(PDF) - STMicroelectronics

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