Z8420

Z8420 STMICROELECTRONICS | Alldatasheet

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Z80 PIO PARALLEL INPUT/OUTPUT CONTROLLER ae eee ee eee # PROVIDES A DIRECT INTERFACE BETWEEN

280 MICROCOMPUTER SYSTEMS AND PE-

= BOTH PORTS HAVE _INTERRUPT-DRIVEN : ee i. HANDSHAKE FOR FAST RESPONSE Ths Tihs bar = FOUR PROGRAMMABLE _ OPERATING Lin a, MODES : BYTE INPUT, BYTE OUTPUT, BYTE Br D Y INPUT/OUTPUT (Port A only), AND BIT DIP-40 DIP-40 INPUT/OUTPUT (Plastic and Frit Seal) (Ceramic) « PROGRAMMABLE INTERRUPTS ON PERIPH- ERAL STATUS CONDITIONS = STANDARD Z80 FAMILY BUS-REQUEST AND PRIORITIZED INTERRUPT-REQUEST DAISY ( CHAINS IMPLEMENTED WITHOUT EXTER- ne? NAL LOGIC 7” = THE EIGHT PORT B OUTPUTS CAN DRIVE c DARLINGTON TRANSISTORS (1.5 mA at PLccaa

1.5 V) (Plastic)

DESCRIPTION (Ordering Information at the end of the datasheet) The Z80 PIO Parallel /O Circuit is a programmable, dual-port device that provides a TTL-compatible in- terface between peripheral devices and the Z80 LOGIC FUNCTIONS CPU. The CPU configures the 280 PIO to interface with a wide range of peripheral devices with no other external logic. Typical peripheral devices that are compatible with the Z80 PIO include most key- 7 z j boards, paper tape readers and punches, printers, i : PROM programmers, etc. fs | One characteristic of the Z80 peripheral controllers ome e “| that separates them from other interface controllers hed * pont a is that all data transfer between the peripheral de- ~ ql vice and the CPU is accomplished under interrupt control. Thus, the interrupt logic of the PIO permits ae in full use of the efficient interrupt capabilities of the 280 CPU during I/O transfers. All logic necessary to cournot a ao implement a fully nested interrupt structure is in- Be ql cluded in the PIO. fs + Another feature of the PIO is the ability to interrupt Yee : veers the CPU upon occurrence of specified status condi- oxo = tions in the peripheral device. For example, the PIO eux “ can be programmed to interrupt if any specified pe- sao ripheral alarm conditions should occur. This inter- werenaver a an rupt capability reduces the time the processor must ‘CONTROL { ha spend in polling peripheral status The Z80 PIO interfaces to peripherals via two inde- pendent general-purpose I/O ports, designated port September 1988 115 175

INTERNAL STRUCTURE INTERRUPT CONTROL LOGIC The internal structure of the Z80 PIO consists of a The interrupt control logic section handles all CPU 280 CPU bus interface. internai control logic, port A __interrupt protocol for nested-priority interrupt struc- VO logic. port 8 VO logic. and interrupt control logic —_tures. Any device's physical location ina daisy-chain (figure 3). The CPU bus intertace logic allows the configuration determines its priority. Two lines (IEI

280 PIO to interface directly to the 260 CPU withno and IEO) are provided in each PIO to form this daisy

other external logic. The internal control logic syn-__ chain. The device closest to the CPU has the hig- chronizes the CPU data bus tothe peripheraldevice —_hest priority. Within a PIO. port A interrupts have interfaces (port A and port B). The two VO ports (A _ higher priority than those of port B. In the byte input. and B) are virtually identical and are used to inter-_byte output. or bidirectional modes. an interrupt can face directly to peripheral devices. be generated whenever the peripheral requests a new byte transter. in the bit control mode. an inter- PORT LOGIC rupt can be generated when the peripheral status Each port contains separate input and output regis» —_ matches a programmed value. The PIO provides for ters. handshake control logic. and the control regis-__ complete control of nested interrupts. That is, lower ters shown in figure 4. All data transfers between _ priority devices may not interrupt higher priority de- the peripheral unit and the CPU use the data input __vices that have not had their interrupt service rou- and output registers. The handshake logic associ- tines completed by the CPU. Higher priority devices ated with each port controls the data transfers may interrupt the servicing of lower priority devices, through the input and the output registers. ine If the CPU (in interrupt mode 2) accepts an interrupt. mode control register (two bits) selects one of the the interrupting device must provide an 8-bit inter. four programmable operating modes. rupt vector for the CPU. This vector forms a pointer The control mode (mode 3) uses the remaining reg- toa location in memory where the address of the in- isters. The inpuvoutput control register specifies terrupt service routine is located. The 8-bit vector which of the eight data bits in the port are to be out- from the interrupting device forms the least signif Puts and enables these bits : the remaining bits are _—_cant eight bits of the indirect pointer while the | Reg- inputs, The mask register and the mask control reg-_ister in the CPU provides the most significant eight ister control mode 3 interrupt conditions. The mask —_ts of the pointer. Each port (A and B) has an inde- register specifies which of the bits in the portare ac- —_pendent interrupt vector. The least significant bit of tive and which are masked or inactive. the vector is automatically set to 0 within the PIO be- The mask control register specifies two conditions: Cause the pointer must point to two adjacent mem- first, whether the active state of the input bits is High _Ory locations for a complete 16-bit address. or Low, and second, whether an interrupt is gener. Unlike the other Z80 peripherals. the PIO does not ated when any one unmasked input bit is active (OR enable interrupts immediately after programming. It condition) or if the interrupt is generated when all waits until M1 goes Low (e.g.. during an opcode unmasked input bits are active (AND condition). fetch). This condition is unimportant in the Z80 en- Figure 3 : Block Diagrain. rey ‘Cowtnoe Se bate ran esvoanace wwranrSae {320 A oar sarees corrman a aa cS )esnornce wwrenmurT CONTROL une G57 S5S:THOMSON = 3s SYM incnomaccrencs 177

Figure 4 : Typical Port I/O Block Diagram. a | H t i + Used in the bit mode only to allow generation of an interrupt if the peripheral 1/0 pins go to the specified state vironment but might not be if another type of CPU = PROGRAMMING Thepiog odes the RETI (Return From Interrupt) MODE 0, 1,0R2 e jecodes the eturn From Interrupt . instruction directly from the CPU data bus so that (Byte Input, Output, or Bidirectional). Programming each PIO in the system knows at all times whether 2 Port for mode 0, 1, or 2 requires two words per itis being serviced by the CPU interrupt service rou- _ Port. These words are : tine. No other communication with the CPU is fe- A MODE CONTROL WORD. Selects the port oper- quired. ating mode (figure 5). This word may be written any CPU BUS I/O LOGIC time. The CPU bus interface logic intertaces the Z80 PIO. AN INTERRUPT VECTOR. The Z80 PIO is de- directly to the Z80 CPU, so no external logic is signed for use with the Z80 CPU in interrupt mo- necessary. For large systems, however, address de 2 (figure 6), When interrupts are enabled, the PIO decoders and/or butfers may be necessary. must provide an interrupt vector. INTERNAL CONTROL LOGIC MODE 3 This logic receives the control words for each port (Bit Input/Output). Programming a port for mode 3 during programming and, in turn, controls the oper- _ operation requires a control word, a vector (if inter- ating functions of the Z80 PIO. The controllogicsyn- _rupts are enabled), and three additional words, de- chronizes the port operations, controls the port scribed as follows : mode, port addressing, selects the read/write func- VO REGISTER CONTROL. When mode 3 is se- tion, and issues appropriate commands to the ports it i © lected, the mode control word must be followed by and the interrupt logic. The Z80 PIO does not_re- th ntrol ‘d that sets the /O trol ceive awrite input from the CPU ; instead, the RD, 701"! Fontiol ware nat Sets te on nts CE, C/D and IORA signals generate the write input". which in turn defines which port lines are inputs and which are outputs (figure 7), internally. 4s Ky ScS:THomson _ SYM fricnon.acincencs, 178

PIN DESCRIPTIONS bit Ao from the CPU is used for this selection func- Ao-Ax, Port A Bus (Bidirectional, 3-state). This 8-bit tion. bus transfers data, status, or control informationbe- BRDY. Register B Ready (Output, Active High). This tween port A of the PIO and a peripheral device. Ap _ signal is similar to ARDY, except that in the port A is the least significant bit of the port A data bus. bidirectional mode this signal is High when the port ARDY. Register A Ready (Output, Active High). The 4 input register is empty and ready to accept data meaning of this signal depends onthe mode of oper-__‘{fom the peripheral device. ation selected for port A as follows : BSTB. Port B Strobe Pulse From Peripheral Device OUTPUT MODE. This signal goes active to indicate _(Input, Active Low). This signal is similar to ASTB, that the port A output veguiert has been loaded and except that in the port A bidirectional mode this sig- the peripheral data bus is stable and ready for trans ren heat austen the peripheral device into the fer to the peripheral device. CID. Control Or Data Select (Input, High = C). This INPUT MODE. This signallis active when the port A in defines the type of data transferto be performed input register is empty and ready to acceptdata from — etween the CPU and the PIO. A High on this pin the peripheral device. during a CPU write to the PIO causes the Z80 data BIDIRECTIONAL MODE. This signal is active when _bus to be interpreted as a command for the port se- data is available in the port A output register for _lectedby the B/A Select line. A lowon this pin means transfer to the peripheral device. In this mode, data __that the Z80 data bus is being used to transfer data is not placed on the port A data bus, unless ASTB_~—_between the CPU and the PIO. Often address bit Ax is active. from the CPU is used for this function. CONTROL MODE. This signal is disabled and GE. Chip Enable (Input, Active Low). A low on this forced to a Low state. pin enables the PIO to accept command or data in- STB. PortA Strobe Pulse From Peripheral Device Puts from the CPU during a write cycle or to trans- (Input, Actives.ow), The meaning of this signal de. ‘mit data to the CPU during a read cycle. This signal pends on the mode of operation selected for port A'S generally decoded from four /O port numbers for Bs follows ports A and B, data, and control. OUTPUT MODE. The positive edge of this strobe is CLK. System Clock (Input). The Z80 PIO uses the issued by the peripheral to acknowledge the receipt __ Standard single-phase 280 system clock. of data made avaliable by the PIO. Do-D7. Z80 CPU Data Bus (Bidirectional, 3-state). INPUT MODE. The strobe is issued by the periph- This bus is used to transter all data and commands eral to load data from the peripheral into the port A between the Z80 CPU and the Z80 PIO. Do is the input register. Data is loaded into the PIO when this _least significant bit. signal is active. IEl. Interrupt Enable In (Input, Active High). This sig- BIDIRECTIONAL MODE. When this signalisactive, nal is used to form a priority-interupt daisy chain data from the Port A output register is gated into the when more than one interrupt-driven device is being port A bidirectional data bus. The positive edge of used. A High level on this pin indicates that no other the strobe acknowledges the receipt of the data. devices of higher priority are being serviced by a CONTROL MODE. Thestrobeisinhibitedinternally. __ CPU interrupt service routine. bus transfers data, status, or control information be-_1EO signalis the other signal required to form a daisy tween port B and’a peripheral device. The port B chain priority scheme. It is High only if IEI is High data bus can supply 1.5 mA at 1.5 V to drive Dar- and the CPU is not servicing an interrupt from this lington transistors. Bo is the least significant bit of PIO. Thus this signal blocks lower priority devices the bus. from interrupting while a higher priority device is B/A. Port B Or A Select (Input, High = B). This pin being serviced by its CPU interrupt service routine. defines which port is accessed during adata trans-__ INT. Interrupt Request (Output, Open Drain, Active fer between the CPU and the PIO. Alow onthis pin Low). When INT is active the Z80 PIO is requesting selects port A ;a High selects port B. Often address _an interrupt from the Z80 CPU. os My SSS:THOMSON YD ico tcriornic 180

SSSSSSSSSSSSSSSSSSSSS—SFSSSSSSSS_ 78420 AC CHARACTERISTICS Symbol P | c | ze420 | ze420A | Ze4208 symbol arameter fomment Min. Min. Max. —~ — (ns) (ns) | (ns) 1] Teo | Clock Cycle Time 4d 400 | (1) 165 | (1) 2 “IwCh | Clock Wiath (high) _ 170 {2000| 105 [2000] 65 [2000

3 TwCl Clock Width iow) 170 |2000/ 105 |2000| 65 |2000)

4 TiC___| Clock Fall Time 30 [30 | | 20

TG) Geek Ase ting | [foo | tao | 6] TscsiR) | CE_B/A C’D to RD, @ 50 1ORQ J Setup Time

7 Th Any Hold Times for Specified Setup

| Time [e | tsANC) [AD TORGto Clock T Setup Time | fis] favs || 70 [| [10] TaR(0s) | RD. 1ORQ T to Data Out Float Delay | fseo [sto | 70 | TsDKC) Data in to Clock 7 Setup Time cL=sopF | s0{| | 50] |[40/ | TdlQ{00!) | IORG ~ to Data Out Delay (INTACK @ er fe] | cycle) [13] TsMuCr) | MI to Clock t Setup Time [ fawl [80] | 70 TsMi(Cf) MI 7 to Clock + setup Time (Mi | (8) ° cycle) TOMKIEO) | MI é to IEO 4 Delay (interrupt 6.7) 300 190 immediately preceding Mi 4)

16 TSIEM(IO) IEI to |ORQ J Setup Time (INTACK (7) 140 100

cycle) 17] ToIEWIEOH “| EI J t0 1E0 J Delay ©) 190 130 CL = 50 pF

18 TAlEWIEOr) IEl 7 to 1EO 1 Delay (after (5) | 210 160 160

ED decode)

19 TelO(C) JORQ 7 to Clock 4 Setup Time (to 220 200

• ___.__| activate READY on next clock cycle) | _ _ 20| TaC(ADYr) | Clock « to READY 7 Delay 6) 200 CL = 50 pF TAC(ADY!) | Clock | to READY 4 Delay ® | [ss0f [sao [| 120] [22] TwST® | STAOBE Pulse Wath sof [aso] pao) TsSTB(C) STROBE 1 to Clock J Setup Time (8) 220 220 (to activate READY on next clock cycle) Notes: 1 TcO-TwCh~ Tw + TC + TIC 2 increase TARi(00) by 10 ns lor each 50 pF increase in oad up to 200 pF max 3. Increase TdiO{00) by 10.ns for each 50 pF increase in ioading up to 200 pF max.

4 For Moce 2 TwSTB > TSPO(STB}

5 Increase these values by 2ns or each 19 pF increase in loading up to 100 pF max. & TsCS(Al) may be reauced. However the tme subtracted trom TSCS(Al) may be added to TRKDO} 7 25 TOO > (N-2)TAIEKIEOH « TIMIIEO) + TsIEIIO) + TTL Butler Delay i any

8 Mi must be actve fora minimum of two clock eyes fo reset the PIO

Gj S6S:THOMSON _ wis V7 acromacrsonice 185

AC CHARACTERISTICS (continued) | [20420 | zesz0n | 204208 | yNe | /Max.| Min. (ns) | (ns) [24] TelO(PD) | TORQ T to PORT DATA Stable 6) L Delay (mode 0) |25| tsPD(STB) | PORT DATA to STROBE 1 Setup Time (mode 1) TdSTB(PD) | STROBE | to PORT DATA Stable (5) {mode 2) 27| TdSTB(PDr) | STROBE T to PORT DATA Float CL =50 pF 160 Delay (mode 2) ToPD(INT) PORT DATA Match to INT J Delay 540 490 (mode 3) [ze[ TasTeIN | STROBE Tio NTT Dewy || a eo [| Notes: 1 ToC=TwCh + Twot + Tro TIC 2 Increase TaRi(0O) by 10 ns for each 50 pF increase in load up to 200 pF max. 3 Increase TdIO(DO) by 10 ns for each 50 pF increase in loading up to 200 pF max. 4 For Mode 2 TwSTB > TsPD(STB). 5 Increase these values by 2 ns for each 10 pF increase in loading up to 100 pF max. 6 TsCS(RI) may be reduced. However the time subtracted from TsCS(RI) may be added to TARI(00). 7 25 TAC > (N-2)TAIEKIEOS + TMM(IEO) + TsIEKIO) + TTL Butter Delay if any. 8 Mt must be active fora minimum of two clock cycles fo reset the PIO.

425 Gy Scs:THoMson

AC CHARACTERISTICS (continued) O PO=| On| O wn “3 rf epost Lathasiad SS ED, SS | | ® @ - [eS on Pek Fra - SS Gl | | os — 2 a eo no @> > sn [I ODEO ® say 8 — aad SS —@—e wont cj) 1 13/16 OSS. 187

=03t0+70 Operation Ambient Temperature __As Specified in Order Codes _ ee Tae _| Storage Temperature Range - =6510+150 | C Stresses greater than those listed under Absolute Maximum Ratings may cause permanenidamage to the device. This is stress rating only ; operation of the device at any condition above those incicated in the operational sections of these specications is not implied Exposure to absolute maximum rating conditions for exiended periods may affect device reliability. STANDARD TEST CONDITIONS All ac parameters assume a load capacitance of The characteristics below apply for the followingtest_ 100PF max. conditions, unless otherwise noted. All voltages are referenced to GND (0 V). Positive current flows into ay the referenced pin. Available operating temperature ve ranges are : ae +4.75V< Voc <+5.25V = 40°C to +85 C. me 2 = 55 Cto+ 125°C, Lif +4.75V< VCC < +5.25V DC CHARACTERISTICS [‘Symboi |____ Parameter | Test Gonditiona | Win | Wax | Unt] |-o3 | oss [| v | Vuie__ | Clock Input High Voltage V-= - 06] Voc+03 [Vi | input Low Voltage __ -03 | 08 Vv Vix | Input High Voltage es ee er) vo [Vor [Output tow vottage | tn 20 mA =| 04 | Vv __Vox | Output High Voltage Jon =-250uA | 4 vi} im Vin = 0 to Voc =10 | 10 uA ‘Over specified temperature and voltage range. CAPACITANCE [ Symboi [ "Parameter [Test Gonditions [| min. | Max. [ unit | c Unmeasured pins retuned || 10 | pF _ | Cw | input Capacitance to ground. [| 5 | oF | Cour | Output Capacitance a Over specified temperature range «f= 1 MHz 1415 ee OSs. 188

ORDERING INFORMATION

[type [Package Temp, [| Clock [Description _|

7842081 DIP-40 (plastic) O/+ 70°C Z80 Parallel

Z8420F1 —_| DIP-40 (frit seal) o/+ 70°C Input/Output Unit 842001 —_| OIP-40 (ceramic) O/+ 70°C 25 MH

7842006 DIP-40 (ceramic) 40/+ 85°C ia

2842002 —_| DIP-40 (ceramic) 55/+125°C | 2842001 | PLCC44 (plastic chip-carrier) __O/+ 70°C _ 78420AB1 | DIP-40 (plastic) O/+ 70°C ‘Z8420AF1 DIP-40 (frit seal) O/+ 70°C H | 28420AD1 _| DIP-40 (ceramic) 1+ 70°C awe | Z8420AD6 | DIP-40 (ceramic) ~40/+ 85°C 28420A02 | DIP-40 (ceramic) ~ 85/4 125°C ‘28420AC1 PLCC44 (plastic chip-carrier) O/+ 70°C 78420BB1 DIP-40 (plastic) O/+ 70°C (78420BF1 DIP-40 (frit seal) O/+ 70°C 78420801 _| DIP-40 (ceramic) O!+ 70°C 6 Mie 28420806 _| DIP-40 (ceramic) ~40/+ 85°C 28420BD2 _| DIP-40 (ceramic) = 55/4125°C 2242081 _| PLCC44 (plastic chip-carrier) Ol+ 70°C _ a] SY iacromecrnomes 189