Z8400AB1

Z8400 STMICROELECTRONICS | Alldatasheet

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and Z80* software compatibility is required for daisy-chaining. logether with indexed and relative and arrays. ‘The 280 microprocessors and associated peripheral with or without daisy chain. by a vectored interrupt system. This counter. Figure 1. Logic Functions

third-generation single-chip microprocessors _very fast interrupt response. it parabus. second-and third-generation register. or up qe pe comprehensive microprocessor product printers, tape punches, and keyboards. i6RG C20 at four programmable hens counter/timers, Bi-Synch and SDLC. nesta comncion bit prescaler. timer mode. cost asynchronous serial communication. Figure 2. Pin Configuration Figure 2a. Chip Carrier Pin Configuration ort It has two channels and a full modem 1 The PIO (Parallel Input/Output) operates control interface.

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280 CPU Registers CPU Registers (Continued)

Figure 4 shows three groups of registers fore: i ; ground data processing. The second set a within the Z80 CPU. The first group consists of registers consists of six registers with Beate Sve (Blt) Remner of duplicate sets of 8-bit registers: a assigned functions. These are the I (Interrupt AR Accumulator a Stores an operand or the results of an operation principal set and an alternate set (designated Register), the R (Refresh Register), the IX nF Flags 8 See Instruction Set. by ' [prime], e.g., A’). Both sets consist of and IY (Index Registers), the SP (Stack 8, BY General Purpose 8 Can be used separately or as a 16-bit register with C the Accumulator Register, the Flag Register, Pointer), and the PC (Program Counter). ac General Purpose 8 See B, above. and six Senerel-purpose registers. Transfer The third group consists of two interrupt DD General Purpose 8 Can be used separately or as a 16-bit register with E. ot ate etween these duplicate sets of status flip-flops, plus and additional pair of BE General Purpose 8 See D, above Togistere is accomplished by use of flip-flops which assists in identifying the HH General Purpose 8 Can be used separately or as a 16-bit register with L. xchange” instructions. The result is faster interrupt mode at any particular time. Table LL General Purpose 8 See H, above response to interrupts and easy, eilicient 1 provides further information on these * ve: The (B,C), (D implementation of such versatile. registers. Nese: Fre (BO), ® BD ana (HLL) sets are combined as follows: programming techniques as background- DoHigh byte E-Low byte H-—High byte L-Low byte “oy Interrupt Register 8 Stores upper eight bits of memory address for vectored interrupt processing. suai necusven . R Refresh Register 8 Provides user-trasparent dynamic memory refresh. Lower seven bits are (STER SET ALTERNATE REGISTER SET automatically incremented and all eight are placed on the address bus during each instruction fetch cycle refresh time. Wy Index Register 16 ‘Same as IX, above. ' Pc Program Counter 16 Holds address of next instruction. ——_n Table 1. CPU Registers rs —___. INTERRUPT FuPLoPE. eraTuE sence ; treanver MODE FUP FLOPS 4 Joe | fb eaRaee wage » : — 13 IRTEAger MS3E 3 ‘ i Fig. 4. CPU Registers | a Se

! + game it “ +) i * HI dl | || ZB401 ia) i a 00 . | | 28400 Fintan OSRE | (ETE vit | a a Interrupts: General Operation The CPU accepts two interrupt input processing cycle begins. This is « special Interrupts: General Operation (Continued) : signals: NMI and INT. The NMI is a non- fetch (MI) cycle in which IORQ becomes _ configuration. Each device in the chain has CPU interrupt status. Operation of the two maskable interrupt and has the highest active rather than MREO, as in normal MI an interrupt enable input line (IEI) and an flip-flops is described in Table 2. For more priority. INT is a lower priority interrupt cycle. In addition, this special MI cycle is interrupt enable output line (IEO), which is details, refer to the Z80 CPU Technical and it requires that interrupts be enabled in automatically extended by two WAIT states, fed to the next lower priority device. The Manual. software in order to operate. INT can be to allow for the time required to first device in the daisy chain has its IEI connected to multiple peripheral devices ina acknowledge the interrupt request. input hardwired to a High level. The first — wired-OR configuration. device has highest priority, while each Action FF, IFF2 Comments The Z80 has a single response mode for Mode 0 Interrupt Operation. This mode is succeding device has a corresponding lower © —————_________ interrupt service for the non-maskable similar to the 8080 microprocessor interrupt priority. This arrangement permits the CPU CPU Reset 9 0 Maskeble inert interrupt. The maskable interrupt, INT, has service procedures. The interrupting device to select the highest priority interrupt from Mashable interrupt three programmable response modes cee ee a meeetan on the date bus. This is several simultaneously interrupting Di instruction 2 8 Haskable -eerae available. n, WI ipherals. These are: initiate a call to the selected one of eight ee nterrupting device disables its tg0 EL insiruction u an, pore ie A restart locations in page zero of memory. dl + lower prioril ripheral . Microprocesses wih the 0080 Unlike the 8080, the 280 CPU responds to vd ra ‘been corvieed, hoe servicing, its LDA, instruction + IFF2—Parity flag = Mode 1 — Peripheral Interrupt service, the Call instruction with only one interrupt IEO line is raised, allowing lower priority execution . © psy-ebay . acknowledge cycle followed by two memory eripherals to demand interrupt servicing. LD A, R instruction 2 4 for use with non-8080/280 systems. read cycles. Pethe 280 CPU will nest (queue) any eecntion_ etre aiFe . — a vector rupt 3 i Accept NMI 0 IFF, IFF\\~IFF2 eee dai ceeees interrupt scheme, afode I Interrupt Operation, Mode 1 __ Bending nterrupls or inlerrupis received * (sob en Family and compatible peripheral operation is very similar to that for the NMI. wi food pe’ INTdisabled) devices. The principal difference is that the Mode | serviced. RETN instruction IFFy_— FFF ad ‘i " completion of an The CPU services interrupts by sampling _—*M*erupt has a restart location of 0038H only. Interrupt Enable/Disable Operation. Two “™*¥" service routine. the NMI and INT signals at the rising edge Mode 2 Interrupt Operation. This interrupt flip-flops, IFF, and IFF;, referred to in the Fable 2. State of Flip-Flops of the last clock of an instruction. Further mode has been designed to utilize most ‘ register description are used to signal the Table 2. State of Flip-Flops interrupt service processing depends upon effectively the capabilities of the Z80 the type of interrupt that was detected. microprocessor and its associated peripheral, Details on interrupt responses are shown in family. The interrupting peripheral device the CPU Timing Section. selects the starting address of the interrupt | Non-Maskable Interrupt (NMI). The non- service routine. It does this by placing an i maskable interrupt cannot be disabled by 8-bit vector on the data bus during the { program control and therefore will be interrupt acknowledge cycle. The CPU forms accepted at all times by the CPU. NMI is @ pointer using this byte as the lower 8-bits usually reserved for servicing only the and the contents of the I register as the i highest priority type interrupts, such as that upper 8-bits. This points to an entry in a H for orderly shut-down after power failure has _table of addresses for interrupt service | been detected. routines. The CPU then jumps to the routine | After recognition of the NMI signal at that address. This flexibility in selecting i (providing BUSREO is not active), the CPU the interrupt service routine address allows | jumps to restart location 0066H. Normally, the peripheral device to use several different | software starting at this address contains the types of service routines. These routines may | interrupt service routine. be located at any available location in | a memory. Since the interrupting device | Maskable Interrupt (INT). Regardless of the supplies the low-order byte of the 2-byte | interrupt mode set by the user, the Z80 vector, bit 0 (Ag) must be a zero. response to a maskable interrupt input _ | follows a common timing cycle. After the Interrupt Priority (Daisy Chaining and | interrupt has been detected by the CPU Nested Interrupts). The interrupt priority of (provided that interrupts are enabled and each peripheral device is determined by its | BUSREQ is not active) a special interrupt physical location within a daisy-chain H fo ee

i | | And | ean ai i URES | a ii i ait Instruction Set i 8-Bit Load Group The Z80 microprocessor has one of the © 16-bit arithmetic operations most powerful and versatile instruction sets __— eo em available in any 8-bit microprocessor. It & Rotates and shift ‘ Symbolic age Opeode Naot Moot M Mol T includes such unique operations as a block © Bit set, reset, and test operations Minomente Operon PT CG HO Bee Prime reine eee Comments move for fast, efficient data transfers within er cata woke Xe ee Ore 7 1 : go memory or between memory and I/O. It also o Jumps rn roe soe Re ke ee me te a. pT me ; . roa Pre ae re re re } allows operations on any bit in any location @ Calls, returns, and restarts wpe ity |r iH PIED E Df Toit oo 3 § oon Tee ing i the 280 ©. Input and output operations os Jet ef ope owing is a summary of the , : Loediea r= tved eek eke ee in 3 sw om A instruction set and shows the assembly A variety of addressing modes are oi 110 language mnemonic, the operation, the flag implemented to permit efficient and fast data tool, bar we xe ee ee Oe ,o2 07 status, and gives comments on each transfer between various registers, memory [DUk-d.r X=@ —e sek Sk eee hom pw 3 5 ls instruction. The Z80 CPU Technical Manual locations, and input/output devices. These ‘ og and 280 CPU Programming Manual contain addressing modes include: waved. (ear coke ke ee Ui 2 8 8 significantly more details for programming a Immediate : ares : use. e LOCHU.» (HL) = se Ke XK © 6 6 CNCNO B 2 3 10 © Immediate extended : LwOtsd, 9 (ed =o ce ae 1 0 Modified page zero one % hi mas 2 : 0 ti © bit loads © Extended cae WDA A- 180) sexe ke ee wm 1 2 7 © 16-bit loads © Indexed Dba ADB Pips ett t echo 1 FF Resistor BDA ise) Rnd Pleo el of Siow 3 fob © Exchanges, block transfers, and searches ‘Hesister \\ at

0 B-bit arithmetic and logic operations © Register indirect Bonk Gack DIET E DIL wie et 2G

a Implied BER Gok Digi off Smo 2 3 4 of © General-purpose arithmetic and CPU i rae control o Bit DAL ket tix oxueo+ viding 2 2 8 a1 ono 57 DAR ACR trxoxuro+ iin gb 2 2 9 : ov lL IN, $F ia Ina see eee Hit 2 2 6 abo I DRA RHA sexe nee es Ulin 2 2 9 oi oni Mla PONS if etn ete eats OF a tonedactne Pi hag 12 ilar aren era or \\ Seca i St a ee Rc

pangs i ad CSUN : HERE ih Ai \\ i ii i \\ 1 8400,) Lh ; 78400 ee i i t ' e Pa LA Ra { cs 16-Bit Load Group | Exchange. Block Transfer, Block Search Groups Ss ss eS Symbolic fags Mo.ot Mo.ol M Mo.ol T 5 gepe HL | DE= HL we Ke Ke ee OE oF 1 4 Mawmoate Opreion —«§ ZR PVN CMS lO Rex Bye Cycle. Slotes Comment EAR AP APO AP Pik kis t mome 1 1 4 Memmenle __Cporeven 9 ERY HC 500 te Her Drten_Creioe Saree __Commens : pikre sis 1d page bank ne adm aa an a a ac 7 i Be = 8c xox Tong be 1 an a a 0 te i oc - Be nrlary reer a ob i HL aL 7 ary thm hm Ce ce ce 0 a ne ed | eae. A= geen sexe ke ee woe 1 5 8 Go 100 O01 21 n | Los aoe mm BeegPe 5 +e Xe Xe es uonimoD 2 6 B rac i Dy - (SP) £ Grae on B Mm | am se ke xe ee Uinm 4 4 ou moe Maser se Xe xe ee Hl 2 6 2 100 001 3 ‘ ‘ rele } 1i 1000 at wi (0H = (HL eK OK FO + WED 2 4 18 Load CLD Inte LHL ton) H = (one) se kere ee wmon 3s 5 i De~ Dev! 10 100 000 0 ‘DB, increment Ctr) “a= j HLT Hist the pointers and =a ‘ B= Ben o ddocement the Be ‘LO dd. (nn) dy = (nino 1) ee Ke Xe © © HED 4 6 Dn ‘ ‘counter (BC) dd, = (nn) Ol dat O1 Lor, (DE) = (HL) 8 kX 0X 0 0 + Nw ED 2 5 a UBC #0 aa De ~ Deel jolioom B24 ie BETO oan ul HL HL+! LD IX, tna) XH = (ane) ee Ke Xe ee ODD 4 6 a ° BC~BC-1 XL = (an) © 10) G10 2A Repeet until are Peco WI lond) Tye = (one td sexe ke ee Winim «© 6 Bw app (08 — ty eex ox os umop 2 4 TYE = (na) 00 101 010 24 i DE ~DE-1 10 101 00 AB rer H RU HL-t Lian HL (nel) =H sexe ke es won 3s os 6 i BC = BC-1 ° fone rrr tor (DB) ~ (HL) se xox 00+ imine 2 $ 2 ECwO LDiew.dd (ened ee eee HE 4 8 DEW DE wimao se 2 4 eae (en) = dd, a 0 on i Boe} rar i Repeat ot LD om, 1X fant) — Ky, sek ek ee © oninn 4 6 w meno fo) fa) {ond = Tt © 100 010 22 crt A~ (HU pre x ee rde Mion 10: ED 2 4 6 rat ‘ HL Hist 16 100 ol At Wom. Gnenemy ee ke ke ee whi «6m | 86 = Bn ® ° mee mina ona A= ony Prk ak tae Hime 2 8 RBC Rand a Ae (HL ee a cee ke ee ion Ho ~ Hust wooo: Bt 2 ¢ HBC Dae BSe sx pieikir: wee por gs ere ay HM 001 Fo Repeat until ws. seat seme ke ee Hm 2 2 Bos ULL OL Fo Pair - fo} PUSH = (SP-2) - a Pare a as ane @ (== sat Neo 1 sn 8 cro A- am rex ex dds nimi 2 4 6 s-s6 3 a DE een 10 101 ool AB PUSHIX§ = (SP=2)~ XL. sXe Xe ee Homo 2 6 os UO | BC ~ BC-1 ey oO (SP=1) = Xy 31 100 101 ES ! Pt ‘SP ~ SP -2 ’ POR AW (HL) pax ex nde 11 10h 101 ED 2 5 2 EBC # Cand ws SPD~ ML ke eee Aen (SD > the twee 7 * 8 ML HL-1 wou 2 4 EBC Oe oe 9-3-2 ' BC = BC-1 er) wm aS Ke Ke ee Qn Repeat uel aay ~ (SP) oo ’ Sid : Aw (Hi) or form iy GPe at HG) Ke Ke ee Hon DD — xp — SP) Moo #7 4 “ NOTE, OD the revit of B= 1 eave the Z ling woe, ether sta ree! Seo spe tt w wt wpe entactonconieton ely. Fore My ghey ee ke ke ee HD 2 4 He mn g 1 co oot Bt a eT : NOTES. dd ayo sooner pam BC DE HE ge ain Altay re heh re dae cr i i er rr ti rea tn rep pce,

, ta t gum Bae pees 4 | Pou Lol eat , ' thie \\\\ 28400, ||) i a ali ———eSSSSSSSSSSSSSSSSSSSSSSsseseF OO 8-Bit Arithmetic and Logical Group General-Purpose Arithmetic and CPU Control Groups ee oe ‘Symbolic logs Opcode Moot Noo! M Kool T ‘Symbolle Page Opcode Nowot Nowot M Nowol T ‘Memonle Operation «SZ PVM C78 S42 110 Hox Bytes Cycles Staten Comments Mormonic Operation S 2H PVN C78 $46 210 Hex Bytes Cycles States Commante Memmensc Operation 8M Se SO es Pre Cree Seon Maesoele Ope Oe ian ee a a ET To ° into packed BCD scouimulaae. ADA, Anker bike xvor wom: Poke kag fling a ADA | AaAen tort kv 0 4 i Bin0 202 7 @8 BCD operand. -—ne oc cPL A-k ee ee 1 4 ‘Complement o D pomsmlioe (o's ADAH) A-ASG = 1 1 X 1X ¥ 0 4 10Gu0 12007 Oe ‘complemer). ADDAMK+OA-AsUKes 1 t Xt XV OF wom pw 3 8 1B Ww H xs AnO-K Po KVL Miri ED 2 2 6 Magatace. (e's

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4 MA CCR oro? ee RX KR 6 Ob CMF OF 1 4 Cor ‘carry ~d = ioe ADAW:OA-Aedrea 11 Xi XVOd Mit mp 2 5 << crt ee xox so 1 wn 1 1 4 Seteneyfag 10 10 NoP No operation tok) ee ee wma I 1 4 ~ 4 - ner CPU ati Pox des tt atomm 1 1 4 AOCAs AnAeeecr oF KEK VOD sie any os xe e-0 Pix de bss noone 1 1 4 sue foAne CHL), (+a), zt a Diy dt nuourw 1 14 us rexexvae a (Yd) as shown e BO ‘Set imerrupt se Xe Ke ee HimimeD 2 2 8 SCAs AnA-ecy oF KEK Vv I) GD fot ADD instruction ‘modeO 01 ooo 110 46 AND AnAns tixixpoo The ndisted bis ati Seinerropt sexe wee © Hine 2 2 8 * resoce the EE ‘mode | 91 010 110 58 ORs AnAve rixoxpoo rents he Ea Me Set terupt eee exe ee Hininm 2 2 8 XOR* A-Aes 11k Ox POO fen} ‘mode 2 01 O11 110 SE i os ao roxexvad ; SSTES 1 hone te wig al ep Ince rered rr xrxvos of 114 EF mca cary tap. new amet KK YO + nota 13 on ‘ shcume ira ar ot acing tent Shr Dh MEK kes) — Pekar xv oe won pm 3 6 2B ae © 10 ~ 3 = ReWr+a aves ~ take x vos im mp 3 6 2B oreae at Ark ji 2 2 ue a) 16-Bit Arithmetic Group pica meme] bixenvae fr) sis any of (HD, (kee) + a ts showa for INC. DEC sare lormet JoDHLw HL Hew see Ke 01 Om oO 1a Reg fd sates a NC. aac Reptece ES] wi AOCHLw HL-HLewecy or 1K XK VO 4 WIED 2 4 15 Ob DE oe a a 010 10 HL opcode ns SOCHLw HL-MLew-cY of KKK VTE iI ED 2 4S 01 wo 010 ADDI p= IK + pp eee or Hono 2 4 fi 01 ppl os fic 01 DE i ns OOM Wao eee eee Oe Mi 2 4S ee Rag er GOL oat ODE to us Ace went sexe re ee mon roa 8 sok ke ik’s Piggy sft moni 2 2 @

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we weaved ee ke xe ee Tite 2 2 0 100 011 23 De net rr er tor 68 ok ee ea Pigs gs ff Wont 2 2 101 ont 28 peer wena eee xe ee Tinto 2 2 0 101 o1F 28 em IES wn arab er pars OC, DELS feeltt ha eget por 86, OE IK 5 : {lyon pear pas BS BE. SP

! A PORES ae Ad ak it V4 the Lyi Sh HE ze i N Ns | 78400 Ks HE zelgoo}] 1 | Wael: Hae { ead toe ef | i Aes stats Hioles all | ema af EI S| : a Rotate and Shift Group Bit Set, Reset and Test Group — ee syanete Page Opcode Nasal Moot M NovotT Syabotic Page Opts Maal Nol M No.l T Moemente Sees Rw c mbotio Mex Byes Cycles Stole Comments wewmoale Seg nc ketones fost Se MT Ca Meemente _Opwreton SN CS Hee Oye Ore ee YMC msn notes ___Commente mca LG we to + oO 1 mcm om 1 1 4 Romelalhcrutr sree tem Kika x xo uoocs 2 2 8 5 te * sooner i grea 2-@y ki xixxoe tooc 2 9 2 ome xox o + ooowmr 7 ot 1 4 Rotate leit } Ol b 10 ow D Claes . fostwor {gre (kedp 2- Ra Kix ik eo + Monine «4 8 mM LE * accu i * i 11 O04 ont cB to i a iL rece COrssep be + + x ok + 0 1 Commi OF 1 te Reset ight circular ‘ atin ay * ronan. ' b___Bit Tested Tb. Uv ediy 2 = Tot Ki xixxoe ummm « 8 » wo aA seo 6 Or moma tk Rate nate LBB MY edly 2— eae ur ait ior FD oro = pote re 10 2 0 ra nic bak OX PO 1 Woon CB 2 2 Rotate ltoveler oe ik an 3 we. wee ; i$ RLC HL bre ox Pot oon ce 2 4 18 thee Hi hog obi mee soe pel see ke ee mcs 2 2 8 | mcwea\\@-O pi xox por norm om 4 6 @ Che Oe. IHD Kaba = Toi on GB io Sith cHL)GHLp 1 sek ee ee Tooce 2 4 - 4 = iL Hb 10 oo Bz} 110 mA Serb. (ed) (kody = sexe xe ee Koni 6 6 2 HO ol CB ncaa buxoxPor ummm ¢ 6 2B M0 a Mooi ou 8 Ge iw Emi Instruction format SETb Ved) W¥edip = 1 se ke ke ee Tim 4 6 OB woes ed aute sat ' 11 ott €B ue banoxPron soar : hon mer (HU.UX+ dAlY +d) bdaeiapiarh iH > no mcm Ciel) pi correo: @ TB or BUC ee er ui, tke kes Totem mar (HOAX +8) (IY +d) with shown code. H (ed). | Costes } ixeg) eB Ras Rem CS—BF ti xo xe os | SET ection. eas, a —__ stam GIS xo x Pot 1 SOTES) The eter my etn (621 one meriHiyKeBitod j seam = CG *F—-"B op i xo xeon | SEP UKoatod | Jump Group sun (OSA ti xoxeo: | on - a mer iHUik+d¥+d) | e PC = nn x x 1 0 alt a3 3 10 ey | rat ond mo | ERED APs kok Po + Hiri ED 2 $B Rewedigshh an! — Censuses nea See, alg alto i 6F Th beowre « Usonincoe rex Tee 9 2 » Se De eccumeitot taePOo a, an mer i a ecto i otharwien can 210 NC non-carcy ‘RRD LOE 7-3-2] 1 1 KX GK P Oe Imi ED 2 5 18 The conten of the conse Ee Za orion & Spee hat ot | 10 PO party ot irene Ho Pr Sgn postive ’ me Fo~ Pee eK Ke ee wom 2 3 IM sn egatve ae ACs wee ee ee Bie m2 27 Memon sot met conte aes fect, 2 912 Meondon mt Foote mae hee Se Ke ee nom 2 27 Hendon nt met continue ares | fers, 222 Mewnden w mt : PS ieee Pie Ese ee Ke ee wore 2-27 Mean sot et contove paar wet 2312 eandon met. . For Ree we tees eee Ke 6 6 wore 2-27 Memedtion nt mat ee mane

peel it (ange : nip ne | eg Pa} oe aan agi sa peeetmmarateses i Be vate RE ee oo Jump Grup (Continued) Input and Output Grup ee po H Moesoale Opectico —& -ZOR PVM C me 469110 Hex Bye Creloe Stowe Commanta Mowmeale Operon «8 ZH PVM C S070 Hex Bye Cycle Stowe Comments Mesoonte____Opwration SEO MC (78549 210 Hex Byres Cyeles States Comments |= Masmente Operation SEM PV MC 780 10 Hex Dt Creleg Stemy Comment zo, 2312 Wecondition i mat. r rear} Ce ae ee ee LE PCW PCve BAG — = Aes. © Ag ~ Ais (HL PO= HL ee re ke ee oe 1 1 4 wo 1-0) tax tx Po * NwiilEeD 2 3. 12 CwAg~ Ar { ft = 110 only the Ol Fr 000 Bio Ag - Als wx) Po sek eX ee + HoniDD 2 2 8 ii flags will be affected:

1 Tol oot 1 (0) cum =A

wm ro-1r re rr at tu — (©) KrxX XXX 1X nwiwED 2 4 1 CwAg~Ar Die = B= B= re arr “0 HU- HL +1 Ua =0, ba ar a) Kix KX X21 X img 2 8 2 CwA~a continue Be b-t iollocio 8 | Bea Beas Ais pes, 2003 We HU- fst 2 os Fos Pose Fapeat unl u8-0 eS Bro NOTES: « represania the axlanaicn nthe relative aadremng mode ® 2g eh component nemer nina age © 6,12 > xo ay - © REX XX Ki X NimiED 2 4 % Cwoho~Ar barer tet aa ol pron a8 PC sw B-B-1 10 101 O10 AA Bio Ag~ Als vivcehednn de remand . arn OR ty KY XXX KTR Mie 2 8 2 CwAg~Ar Be a-t 10 111 010 BA (Bo Bone Ais RL HL-1 2 oe Repeater (ua. Bre Call and Return Group Ourin.A (=A re Pe are cc 9 Aa ~ Als niO.r ar see ke ee mie 2 3) Cela CAlLm = (SP-D=-FH SKK ee Nome 3 8 on or x Olt Oot Bean P22 — PL <a = e) PC = an 7k out (©) — (HL) Roux x x K 1 X porto ed 2 4 16 geto-M. = 1 100 ott AB BioAg~ CAuLce.nn eondtion a a ee fonts feos Sele aaraen om @- Hu KX XX KL xX nied 2 2% CAg~A7 Conte, Tet 8 8 teu tue, here 10 No oll Be wae Beas Ais eherrse same os HL=Hi+1 2 4 16 CALL en Repeat until (1B=o) RET Poy - (SP) sek eRe ee Umm 1 3) | Bro fo) PCH ~ (SP-+1) t ouTD (C) — (HL) Xox x XX 1X wir ire 2 4 16 Sto Ag ~ Az _ {0 101 O11 AB Boag RET ce ——eondtion re ce ce ee | fos at-1 fens cculaie ! ‘continue, 1 3M Hee tue, 10} crime. conn - Ko1x Mii 2 $2 CwAg~ Ar hers s=_Conditon i ev x UR KX om on (uBso Bag ~ Als aoe j a 2 6 Ret 01 2 ser | Repeat nal = 0 (peo Ren ewe fom Se eee imi 2 4g ONC noncary lek interuot 4} oot iot 4D SST Qe tel Bot wwe he Zag. eave Hirt ReTN! Rerum Irom see Re ee TTI ED 2 4 ag DFO pantroad | Oi ihe omtoh B= Zag ton-natiable 01 amo 1ol «8 10 Pan pootive interust LLM gn pgotive \\ RSTp (P-1) PCH eek eee ee em 1 30 uk ‘ (Se-2 — Pep tore \\ PCH 0 Ol BH | PCL=P 010 10H Hy Ou 18H i i 2H i tol 2H i no BH i i 3H i NOTE ETN ihhy OF, : 1 eee a

ah NEE Rac itiiit: : Tete EV i cvs a | Pin Descriptions Summary of Flag Operation | Ay-Aig: Address Bus (output, active High, can be placed on the data bus. t 3-state). Ag-Ajs form a 16-bit address bus. MI. Machine Cycle One (output, active Low). —— ——~-~—w—wnw,-’rr’rr—oO The Address Bus provides the address for MI, together with MREQ, indicates that the rvcton Comm memory data bus exchanges (up to 64K current machine cycle is the opcode fetch NODA WADCA.® DETR aR YO Bh add or add wah oory | bytes) and for I/O device exchanges. cycle of an instruction execution. M1, SuBN SBCA CPawEG 1 1X 1 XY Lb) Sbenbien. mbar with carry, compare and negate accumulator. | BUSACK. Bus Acknowledge (output, active together with IORQ, indicates an interrupt Bea ron« PER SE BO Gh tena operaone | Tow), Bus Acknowledge indicates to the acknowledge cycle. ban pret ky of gegen ij requesting device that the CPU address bus, MREQ. Memory Request (output, active 0D bo. we eer rae | Gata bus, and control signals MREO, IORQ, —_Low, 3-state). MIREG indicates that the Sout PEER EY Lt lebtnieectnme | BD, and WE have entered their high- address bus holds a valid address for a SPCHL es mana $8 RO YOY Remwamumaon impedance states. The external circuitry can memory read or memory write operation. aan 11K 0X PO 1 Remand shit cations . now control these lines. NMI. Non-Maskable Interrupt (input, ete bi xoxpor ek BUSREQ. Bus Request (input, active Low). negative edge-triggered). NMI has @ higher DAA Te ee ef Betimal Stet ccc. Bus Request has a higher priority than NMI priority than INT. NMI is always recognized ee PL RL Ef bt Somptman accumiaer and is always recognized at the end of the at the end of the current instruction, cor DE KE 5 8 t Somplemen carry. ‘ current machine cycle. BUSREQ forces the independent of the status of the interrupt BO sn ouro EEK 2X BOF tamer indvet . ' CPU address bus, data bus, and control enable flip-flop, and automatically forces the AINOR OTRGTOR XL KK KO T] Biect mputand oupu. 2 + OB # Other «0 i signals MREQ, IORQ, RD, and WR to go to CPU to restart at location 0066H. LDIRLDOR KX EOF FO os} Bick wari intvctons P/V = 1 BC 0, oterwise PV = 0 a high-impedance state so that other devices RD. Read (output, active Low, 3-state). CPt CPIR: CPD: CPOR BOP RR KT TD) Blak serhinaaciony 22 24.8» (HL, charwae 2 0/0 «1 can control these lines. BUSREO is normally RD indicates that the CPU wants to. IDALIDAR ta xo «ts content of the erupt en , wire-ORed and requires an external pully read data from memory or an levice. bits Pe Se SP etoeee oto terete eee for these Spplications. Extended BUSES The addressed I/O device or memory should ee periods due to extensive DMA operations can USe this signal to gate data onto the CPU ‘Symbol Operation Symbol Operation prevent the CPU from properly refreshing data bus. — ay Pere td acto ne panty he operation is a Spero D,-Dy. Data Bus (input/output, active High, initializes the CPU as follows: it resets the Eu) chavo the some tiny. Logical operstions alfect 0 The lag i unchanged by the operation : Restate). Dg-D; constitute an B-bit interrupt enable flip-flop, clears the PC and this flag with the parity of the result while 1 The flag is set by the operation. bidirectional data bus, used for data Registers I and R, and sets the interrupt arithmetic operations aflect this flag with the x The flag is a "don't care.” ! exchanges with memory and I/O. status to Mode 0. During reset time, the overtiow of the result. If P/V holds Paris Pv = v P/V flag affected according to the overflow result HALT. Halt State (output, active Low). H ALT address and data bus go to a high- 11 ra a oan eT To ANTS ce _ Indices that he CPU has exaouted a Halt” pedance sate, and all control output the result of the operation produced an overflow. Boers according to the parity result | instruction and is awaiting either a non- signals go to the inactive state. 4 Hall-carry flag. H = 1 if the add or subtract r ‘Any one of the CPU registers A, B, C, DE, H, L. maskable or a maskable interrupt (with the Note that RESET must be active for a operation produced a carry into or borrow from ‘Any 8:bit location for all the addressing modes | mask enabled) before operation can resume. minimum of three full clock cycles before the N bi Ae the sccumulator . allowed for the particular instruction. | While halted, the CPU executes NOPs to reset operation is complete. _ Aaavoubtect ag, W = 1 tthe previous opera; wt Any 16-bit acai or all he cresting modes | maintain memory refresh. RFSH. Refresh (output, active Low). RFSH, H&N Hand N flage are used in conjunction withthe “ ere a ea odae tagiatrs IX oF IY. | INT. Interrupt Request (input, active Low). together with MREQ, indicates that the lower decimal adjust instruction (DAA) to properly cor- —R Refresh counter. ot. i Interrupt Request is generated by I/O seven bits of the system's address bus can be rect the result into packed BCD format following EN B-bit value in range < 0, 255 >. devices. The CPU honors a request at the used as a refresh address to the system’s ecktion or subtraction using operands with an 16-bit value in range < 0, 65535 > | end of the current instruction if the internal dynamic memories. cc — eerfLinctag.C = 1 the operation produced | Soltware-controlled interrupt enable flip-flop WAIT. Weit (input, active Low). WATT Scary from the MSB ol the operand or result. | (IF) is enabled. INT is normally wire-ORed _ indicates to the CPU that the addressed | and requires an external pullup for these memory or I/O devices are not ready for a \\ applications. data transfer. The CPU continues to enter a ( TORQ. Input/Output Request (output, active Wait state as long as this signal is active. | Low, 3-state). IORQ indicates that the lower Extended WAIT periods can prevent the . | half of the address bus holds a valid /O CPU from refreshing dynamic memory properly. | address for an I/O read or write operation, WR. Write (output, active Low, 3-state). TORO is also generated concurrently with MI WR indicates that the CPU data bus | during an interrupt acknowledge cycle to holds valid data to be stored at the \\ indicate that an interrupt response vector addressed memory or I/O location. Sn nn i

cycle later, MREQ goes active. When active, | . = V/O device read or write RD indicates that the memory data can be as in the fetch cycle. In a memory write semiconductor memories. enabled onto the CPU data bus. Figure 5. Instruction Opcode Fetch |

| interrupt is accepted, a special MI cycle is two Wait states to this cycle.

9 ED | Le a eH

| NOTE: 1) Th = Last atte of previous instructor. 2) Two Wait crcias automatically inserted by CPUC). Figure 7. Input or Output Cycles |

amen ean P| ees AY ANE oo Ze400 | i fated il { call EHR CPU Timing (Continued) } CPU Timing (Continued) _ . . { Bus Reqeust/Acknowledge Cycle. The CPU and WR lines to a high-impedance state with maskable interrupt input INT but has higher executes a restart (RST) operation and jumps last clock poviog of 2a machine cycle that time, any external device can take priority and cannot be disabled under to the NMI service routine located at address, (Figure 10). If BUSREQ is active, the CPU control of these lines, usually to transfer data Software control. The subsequent timing is 0066H (Figure 9). j setts address, data, ond MREQ, TORO, RD, between memory and I/O devices. similar to that of a normal instruction fetch | rt of i seen cnrme | a t % 1 pe oe i eee tele _ i Koy ' dee mn TILIA. : xv, ——— : be =o . t i i FEF > ar 58 =a] 0 =. } Met 1 a a we i ; en men Ee | are are sow pa | | ' : se | Bre ae , i | ‘ " T\\ secgnlnd on the lllowing mache cic. Wi ialiog edge prevedia Teast ' lap i en i i Figure 9, Non-Maskable Interrupt Request Operation | So | NOTE: T= Last ate of any M eyele Tye An arbizary clock cycle ned by eaquesing demos | Figure 10. Z-Bus Request/Acknowledge Cycle i i fo

Figure 11. Halt Acknowledge Cycle | 18 TaWAIT\\C) WATT Hold Time after Clock 1 — o- o- o- 0

2 TdCr(RFSHr) Clock 1 to RFSH 1 Delay = 190 — 10 — 10 — 6

Figure 12. Reeet Cycle Ji mings are prelimne~? and subject to change,

re Wessca et bs | peste ij Hee) Bere vated” i a i Ras toate UNE AEE i Neen EEE EEE —_— AC Characteristics (Continued) | Footnotes to AC Characteristics Za400 = Z8400R | -8400B—28400H Number Symbol 78400 284004, ‘734008 Min Max Min Max Min Max Min Max | 0° ODS ONO TS Number Symbol _ Parameter (ns) (as) (ns) (ns) (ns) (ns) (ns) (ns) | 1 TC TwCh+TwCl+TrC+TiC TwCh+TwCl+TrC+TiC TwCh+TwCl+TrC + TIC an cn REEF 2. TwCh Although static by design, Although static by design, Although static by design, 96 TACKHALT) Clock 1 to HALT T or ¢ — - - — my TwCh of greater than TwCh of greater than TwCh of greater than 37 TwNMI NMI Pulse With oa - 9 - » - Oo — 200 ps is not guaranteed 200 ps is not guaranteed 200 us is not guaranteed 38 TsBUSREQ(Cr) BUSREO Setup Time to Clock? 80 — 80 — 80 ~ 4 ~ | 7 — TdA(MREQH — TwCh + TIC-75 ——— TwCh + TIC - 63 ——— TwCh + TIC-50 ——— 30‘ TeBUSUREC\\Cr) BUSREO Hold Time after Clockt 0 — 0 ~ 0 ~ 0 ~ | 10 TwMREQh — TwCh+TIC-30 TwCh+TIC-20 TwCh+TiC-20 — 40 ——TACHBUSACKi) Clock 1 to BUSACK | Delay ———— 120 ———100 909 80, 11 TwMREQl ToC -40 TeC-30 TeC-30 41 TdCK(BUSACKr) Clock | to BUSACK 1 Delay — no — 1 — 9 — @ ; 2% — T4AUORQ! =~ TeC-80 TeC-70 ToC -55

42 TdCe(T2) Clock t te Data Float Delay — 9 ~ 9 ~ » - w | ca TaDCW Beo-210 Be- im tec va

Delay (REO, TORO, RD, ond WE) | 3 tewaeo) « Tecistee-s = Twcisnee-m = TwlsTe=ss ‘ +TrC-| wCl+TrC- +TrC~

44 TaCH(AD) Clock 1 te Address Float Delay = — 090 3 TacT#ay TwolsT:C--40 TwCl+TrC-50 TwCl+TrC-50

——45 ——TdCTr(A) —— MREO 1, TORO t, RD t, and —— 160>_— 80-35 0-—-_ . - + TIC-65 - WR T to Address Hold Time . i 50 TdMl(IORQA) 2TcC + TwCh + TiC -80 2TcC + TwCh + TIC -65 2TcC + TwCh + TIC~SO0

46 TsRESET(Cr) RESET to Clock 1 Setup Time 9 = 6 = BH = % =~ | AL Tost Condos Yuc=048 8

47 ThRESET(Cr) RESET to Clock t Hold Time - 0 =~ 0 =~ 0 = 0 yisday Vouso8 v

48 TsINT#(Cr) INT to Clock f Setup Time a —- @ -~ 0 — 8 — | Vic = Veo-0.6 V FLOAT = £0.5 V

49 ThINTs(Cr) INT to Clock t Hold Time —- 0 = 0 =~ 0 = 0 } a

59 ——TamtilOROD—Mi 1 to TORS 4 Delay 620" 505" __—265"zro-— | 51 TACKIORQ! ~— Clock $ to TORO 4 Delay — no — 8 — 7 — @ | Absolute Maximum Ratings $2 TACIIORQ) Clock T to TORQ 1 Delay - wo - 8 - nD - @ | Storage Temperature ... —65°C to + 150°C Stresses greater than those listed under Absolute Maximum 83 TACK) Clock to Data Valid Delay 280151 IS | Temperature Erenrotay cnly dporeton al the eves 0 any condition’ or clock periods other than a aes in Vol:ages on all inputs and outputs specications Is nol implied. Exposure to ebsolute maximum ble, calculate parameters using the expressions in the table on ges P P specications is not implied: Exposure to absolute maxim | Standard Test Conditions | The characteristics below apply for the All ac parameters assume a load | following standard test conditions, unless capacitance of 50 pF, Add 10 ns delay for | otherwise noted. All voltages are referenced each 50 pF increase in load up to a ; ‘oe GND (0 V). Positive current flows into the maximum of 200 pF for the data bus and 100 1 referenced pin. Available operating pF for address and control lines. temperature ranges are: | © 0°C to +70°C, aa | 44.78 V < Voc = +5.25V ae = —40°C to +85°C, noon Test +4.75 V < Voc S$ +5.25V +4.75V < Veo S +5.25V | ++

’ t : : t agen Tse eaaesyed re v0 Vik : neh 784001 1h SN) Zeq00 VEL Zet00F TT Seti wourtad i Peetestamd) ! a So DC Characteristics | Ordering Information Symbol Parameter Min, Max Unit Test Condition \\ Type Package Temp. Clock Description Symbol Pants OC Oe rr orJToJamem— | __ Package eee Vite ‘Clock Input Low Voltage -0.3 0.45 v | z3300 3 pase oo + bed 780 Central Processing Unit . _ 73100 BS lastic = 40/ +85" Vise Clock Input High Voltage Vee -0.6 Voc+03 V | Bn Peat OTe Vin Input Low Voltage -0.3 08 v So) FS Frit Seal = 40/ 485°C Vin Input High Voltage 2.0 Veo OV | S300 DI Ceramic 0/+70°C Vou Output Low Voltage 0.4 Vo Igp= 1.8 mA 73400 pe Ceramic ee 2.5 MHz =- 73400 ‘eremic 55/4125" Vou Output High Voltage 24 V lous —250 0A 73100 Cl Plastic Chip-Carrier 0/+70°C lec Power Supply Current 73100 C6 Plastic Chip-Carrier = 40/+85°C 280 150) mA i 400. KI Ceramic Chip-Carrier 0/+70°C BOA 2000 mA 23400 K6 Ceramic Chip-Carrier —40/+85°C 0B 2 mA | Bx K2 Coramic Chip-Carrier ~85/+ 125°C 200 | 25x00A BL Plastic 0/ + 70°C 20H nA BOA BE Plastic = 40/+85°C li Input Leakage Current - 10 BA Viy=0 to Veo 008 FI Fett Seal 0/470°C ho 3-State Output Leakage Current in Fisat -10 10° #A Vout=0.4 to Voc | 2BS00A F6 Frit Seal —40/+85°C TpauiwygulpmhebMak 734004 Dl Ceramic 0/+ 70°C For military grade parts, Ioc is . BOA DE Cor - a 2. Typicel rate for Z400A is 60 mA, en De Crame ees ) 40 Mite 3. Ais-Ao,D7-Do, MREQ, TORQ, RD, and WR. 7:C0A C1 Plastic Chip-Carrier 0/+70°C Z3400A CB Plastic Chip-Carrier —40/+85°C

784004 K1 Ceramic Chip-Carrier 0/+70°C

78:00A KB Ceramic Chip-Cerrier = 40/+85°C 78:00 K2 Ceramic Chip-Carrier -55/+125°C

736008 BL Plastic 0/+70°C

i | 753568 BE Plestic = 40/ + 85°C Capacitance SF Frit Seal 0/+70°C Symbol Parameter Min. Max Unit Note t TBx00B FS Frit Seal —40/ + 85°C —_ ee 23008 DI Ceramic 0/+70°C Cotock Clock Capacitance E) Fo \\ 25:008 DE Ceramic = 40/+85°C | gg a, Cw Input Capacitance 5 pt Upmensured pines | Zas008 D2 Ceramic -ss/+i2sec (OO ™ Cot Output Capacitance 10 oF | 34008 C1 Plastic Chip-Carrier 0/+70°C. <r Eee 288008 CB Plastic Chip-Carrier —40/+85°C T,=25°C, f=1 MHz | 254008 K1 Ceramic Chip-Carrier 0+ 70°C | 73x03 Ke Ceramic Chip-Carrier = 40/+ 85°C | Basn08 x2 Ceramic Chip-Carrier ~58/+ 125°C. | 73008 BL Plastic 0” +70°C | Zas00x BE Plastic = 40/+85°C; | BH Fl Frit Seal 0/+70°C. | 2as00% Fe Frit Seal —40/+ 85°C 2400H DI Ceramic 470°C Na sate 28400H DE Ceramic -ao/+asec (OO MEE 23400H Cl Plastic Chip-Carrier 0/+ 70°C 7B400H CB Plastic Chip-Carrier -40/+85°C | Goon Ki Ceramic Chip-Carrior 0/+70°C | T3HO0H Ke Ceramic Chip-Carrier ~40/+.85°C i j