Z8001B1V

Z8001SEGCPU STMICROELECTRONICS | Alldatasheet

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ky, SGS-THOMSON 28001 SEGCPU TM, wucrosusctnomies 28002 CPU CENTRAL PROCESSING UNIT = Regular, easy-to-use architecture. = = Instruction set more powerful than many mini- _ \\ computers. - ® Directly addresses 8M bytes. th = Eight user-selectable addressing modes. 1 al . = Seven data types that range from bits to 32-bit tl long words and word strings. 1 = System and Normal operating modes. PDIP40 = Separate code, data and stack spaces. . = Sophisticated interrupt structure. ae = Resource-sharing capabilities for multiprocess- _— ( ing systems. ~ t = Multi-programming support. a ie = Strong compiler support. yr = Memory management and protection provided ' by 28010 Memory Management Unit. Poipas z i tudi [ . 32 it operations, including signed multiply and (Ordering information at the end of the datasheet) = Z-BUS compatible = 4,6 and 10MHz clock rate. Figure 1-1. Logic Function GENERAL DESCRIPTION The Z8000 microprocessor has been designed to ws fe S8b—] accommodate a wide range of applications, from mane | oes 2 — the relatively simple to the large and complex. The pleco © 3P——

28000 CPU is offered in two versions : the Z8001 ( =fesissm 9,0

and Z8002. Each CPU comes with an entire family suns | STE SES | mimes of support components : a memory management I peo ee | unit, a DMA controller, serial and parallel /O con- Ss" Feoed 1935 —= | trollers and extended processing units - all com- Sepa aed Sans patible with the Z-BUS*. Together with other 28000 co (a oar Family components, the advanced CPU architec- rr rr) Fe J ture provides in an LSI microprocessor design the cove, (SBR a ha flexibility and sophisticated features usually asso- . = | s+ ory ciated with mini- or mainframe computers. weawvers { 9 ee The major architectural features of the 28000 CPU Tt io i that enhance throughput and processing power are wane { 18 | SBT? stom | a general purpose register file, system and normal a modes of operation, multiple addressing spaces, a rope powerful instruction set, numerous addressing vec ONO CuK EET saooraae modes, multiple stacks, sophisticated interrupt structure, a rich set of data types, separate VO May 1991 4

Z8001,2 CPU

280012 CPU

GENERAL DESCRIPTION (Continued) address spaces and, forthe 28001, alarge address _ operations have been separated from memory ac- space and segmented memory addressing. Each —_cesses, further enchancing the capability and inte- of these features is treated in detail in the next —_grity of Z8000-based systems, and a sophisticated section. interrupt structure facilitates the efficient operation These architectural features combine to produce a. Of Peripheral /O devices. Moreover, the Extended powerful, versatile microprocessor. The benefits Processing Unit (EPU) capability of the Z8000 that result from these features are code density, lows the CPU to unload many time-consuming compiler efficiency, support for typical operating _'@SkS onto external devices. system operations, and complex data structures. Special features of the 28000 have been intro- These topics are treated in this chapter. duced to facilitate the implementation of multiple The CPU has been designed so that a powerful focessor systems. In addition, the 28001 CPU memory management system can be used to im- has a large, segmented addressing capability that prove the utilization of the main memory and provide _9featly extends the applicability of microprocessors protection capabilities for the system. This is dis- © large system applications. Cussed in this chapter. Although memory manage- General-Purpose Register File. The heart of the ment is an optional capability - the ZB000 CPU is an 8000 CPU architecture is a file of sixteen 16-bit extremely sophisticated processor without memory —_ general-purpose registers. These general-purpose management: the CPU has explicit features to facili registers give the 28000 its power and flexibility and tate integrating an external memory management add to its regular instruction structure. Gevice into a 28000 system configuration. General-purpose registers can be used as accu- Finally, care has been taken to provide a very mulators, memory pointers or index registers. Theit general mechanism for extending the basicinstruc- major advantage is that the particular use to which tion set through the use of external devices (called they are put can vary during the course of a pro- Extended Processing Units - EPUs). In general,an _ gram as the needs of the program change. Thus, EPU is dedicated to performing complex andtime- the general-purpose register file avoids the critical consuming tasks so as to unburden the CPU. bottlenecks of an implied or dedicated register Typical tasks for specialized EPUs include floating- architecture, which must save and restore the con- Point arithmetic, data base search and mainten- tents of dedicated registers when more registers of ance operations, network interfaces, and many —_a particular type are needed than are supplied by others. This topic is treated in this chapter. the processor. The 28000 CPU register file can be addressed in Architecture several ways : as 16 byte registers (occupying one The architectural resources of the 28000 CPU _ half of the file) or as 16 word registers or, by using include sixteen 16-bit general-purpose registers, __the register pairing mechanism, as eight long-word seven data types ranging from bits to 32-bit long (32-bit) registers or a four quadruple-word (64-bit) words and byte strings, eight user-selectable ad- _registers. Because of this register flexibility, itis not dressing modes, and an instruction set more necessary (for example) for a Z8000 user to dedi- powerful than that of most mini-computers. The 110 _cate a 32-bit register to hold a byte of data. Regis- istinct instruction types combine with the various __ters can be used efficiently in the 28000. Gata types and addressing modes to formarichset instruction Set. A powerful instruction set is one of 414 instructions. Moreover, the set exhibits a of the distinguishing characteristics of the Z8000. Hector eee rd oree man Saoteasing The instruction set is one measure of the flexibility ; a 9 and versatility of a computer. Having a given oper- modes, with 8-bit byte, 16-bit word, and 32-bit ation implemented in hardware saves memory and 'ong-word data types. improves speed. In addition, completeness of the The CPU generates status signals indicating the operations available on a particular data type is nature of the bus transaction that is being at- frequently more important than additional, esoteric tempted ; these can be used to implement sophis- instructions, which are unlikely to affect perfor- ticated systems with multiple address spaces - _ mance significantly. The Z8000 CPU provides a full memory areas dedicated to specificuses. The CPU complement of arithmetic, logical, branch, /O, also has two operating modes, system andnormal, shift, rotate, and string instructions. In addition, which can be used to separate operating system ‘special instructions have been included to facilitate functions from normal application processes. YO —_ multiprocessing, multiple processor configurations, 2 “THOMSON:

J Z8001,2 CPU and typical high level language and operating sys- _ipulation instructions can use calculated values to tem functions. The general philosophy of the in- specify the bit position within a byte or word as well struction set is two-operand register-memory _asto specify the position statically in the instruction. operations, which include as a special subset reg- The Rotate and Shift instructions are considerably ister-register operations. However, to improve more flexible than those in previous microproces- code density, a few memory-memory operations _sors. The String instructions are useful in transiat- are used for string manipulation. The two-address_ ing between different character codes. format reflects the most frequently occuring oper Multiple-processor configurations are supported by ations (such as A — A +B). Also, having one ofthe _special instructions. operands in a rapidly accessible general-purpose register facilitates the use of intermediate results Data Types. Many data types are supported by generated during a calculation. the 28000 architecture. A data type is supported . when it has a hardware representation and instruc- The majority of operations deal with byte, word, or tions which directly apply to it. New data types can long-word operands, thereby providing a high de- always be simulated in terms of basic data types, gree of regularity. Also included in the instruction but hardware support provides faster and more setare compact, one-word instructions forthe most convenient operations. The basic data type is the frequently used operations, such as branching byte, which is also the basic addressable element. short distances in a program. The architecture also supports the following data The instruction set contains some notable addi- types : words (16 bits), long words (32 bits), byte tions to the standard repertoire of earlier micropro- _stfings, and word strings. In addition, bits are fully cessors. The Load and Exchange group of supported and addressed by number within a byte instructions has been expanded to support opera-___or word. BCD digits are supported and represented ting system functions and conversion of existing _as two 4-bit digits in a byte. Arrays are supported microprocessor programs. The usual arithmetic in- _by the Indexed addressing mode (in Chapter AD- structions can now deal with higher-precision oper- DRESSING MODES). Stacks are supported by the ands, while hardware multiply and divide instruction set and by an external device (the Mem- instructions have also been added. The Bit Man- ory Management Unit 28010 MMU) available with the Z8001. Figure 1-2. 28000 CPU Functional Block Diagram ! GENERAL aiaie ne ae ' | eunwose oct: ; ' neossens user (a i ' = I "T TAT BUS i wnrcarace KB ‘ ‘shucTiOa neosrers ! i EXECUTION ope774 TRCEPTON H |. 28000 cru ' ee rc1226 * 3

Z8001,2 CPU Architecture (Continued) Addressing Modes. The addressing mode, which Programs executing in normal mode which have errors is the way an operand is specified in an instruction, can always reproduce those errors for debugging pur- determines how an address is generated. The poses simply by re-executing the program with its Z8000 CPU offers eight addressing modes. _original data. Programs using faciities available only in Together with the farge number of instructions and _ system mode may have errors due to timing consider- data types, they improve the processing power of _ations (e.g. based upon the frequency of disk requests the CPU. The addressing modes are Register, and disk arm-position) that are harder to debug be- Immediate, Indirect Register, Direct Address, cause these errors are not easily reproduced. Thus, Index, Relative Address, Base Address, and Base __the preferred method of program development is to Index. Several other addressing modes are implied _ partition the task into a portion which can be performed by specific instructions, including autoincrement. without those resources accessible only in system The first five modes listed above are basicaddress- mode (which will usually be the bulk of the task) and a ing modes that are used most frequently and apply —_portion requiring system mode resources. The classic to most instructions having more than one address- example of this partitioning comes from current mini- ing mode. (In the 28002, Base Address and Index computer and mainframe systems : the operating sys- modes are identical, and in the 78001, Base Ad- _temruns in system mode and the individual users write dressing capabilites can be simulated with all in- their programs to run in normal mode structions, using Based Addressing or the Memon Management Unit and the Direct or Indexed ad. To further support the system normal mode dicho- dressing mode.) tomy, there are two copies of the stack pointer -one for a system mode stack and another for a normal Multiple Memory Address Spaces. The 28000 mode stack. These two stacks facilitate the task CPU facilitates the use of multiple address spaces. witching involved when interrupts or traps occur. To When the 28000 CPU generates an address, italso_ingure that the normal stack is free of system infor- outputs signals indicating the particular internal tation, the information saved on the ocaurance of activity which led to the memory request : instruc- interrupts or traps is aways pushed on to the system tion fetch, operand reference, or stack reference. tack before the new program status is loaded. This information can be used in two ways : to increase the memory space available to the pro-. Separate /O Address Spaces. The 28000 Archi- cessor (for example, by putting programs in one tecture distinguishes between memory and /O ‘space and data in another) ; or to protect portions spaces and thus requires specific /O instructions. of the memory and allow only certain types of This architectural separation allows better protection accesses (for example, by allowing only instruction and has more potential for extension. The use of fetches from an area designated to contain proprie- separate VO spaces also conserves the limited tary software). The Memory Management Unit 28002 data memory space. There are in fact two (MMU) has been designed to provide precisely separate VO address spaces : standard VO and these kinds of protection features by using the special /O. The main advantage of these two spaces CPU-generated status information. is to provide for two types of peripheral support System/Normal Mode of Operation. The 28000 _ “hips “standard /O peripheral and special /O periph- CPU can tun in either system mode or normal _&*als- devices such as the 28010 Memory Manage mode. In system mode, all of the instructions can Ment Unit that do not respond to standard VO be executed and all of the CPU registers canbe © Commands, but do respond to special /O com- accessed. This mode is intented for use by pro- _ Tands. A second advantage of these two spaces is grams performing operating system functions. In _‘hat they allow 8-bit peripherals to attach to the Normal mode, some instructions may not be ex. '0W-order eight its (standard /O) or tothe high-order ecuted (e.g., /O operations), and the control regis- eight bits (special /O) of the processor Address/Data ters of the CPU are inaccessible. In general, this US. mode of operation isintended for use by application The increased speed requirements of future micropro- programs. This separation of CPU resources pro- _cassors are likely o be achieved by tailoring memory motes the integrity of the system, since programs and /O references to their respective, characterste Operating in normal mode cannot access those —_feference pattems and by using simultaneous /O and aspects of the CPU which deal withtime dependent memory referencing, These future possibilties require or system-interface events. anarchtectural separation today. Memory-mapped /O is stil possible, but loss of protection and lack of expandability are severe problems. 4 .

2Z8001,2 CPU Interrupt Structure. The sophisticated interrupt Large Address Space for the Z8001. For many structure of the Z8000 allows the processor to —_ applications, a basic address space of 64K bytes continue performing useful work while waiting for _is insufficient. A large address space increases the peripheral events to occur. The elimination of peri- range of applications of a system by permitting odic polling and idling loops (typically used todeter-__ large, complex programs and data sets to reside in mine when a device is ready to transmit data) memory rather than be partitioned and swapped increases the throughput of the system. The CPU _into a small memory as needed. A large address supports three types of interrupts. Anon-maskable space greatly simplifies program and data man- interrupt represents a catastrophic event which agement. In addition, large address spaces and requires immediate handling to preserve system memories reduce the need for minimizing program integrity. In addition, there are two types of mask- _size and permit the use of higher level languages. able interrupts : non-vectored interrupts and vec- The segmented version of the Z8000 generates tored interrupts. The latter provides an automatic 23-bit addresses, for a basic address space of 8 call to separate interrupt processing routines for megabytes (8M or 8,388, 608 bytes). each peripheral, depending on the vector mented Addressing of the 28001. The seg- Presented by the peripheral to the 28000. eed version of the 28000 CPU divides its 23-01 The Z8000 has implemented a priority system for addresses into a7-bit segment number and a 16-bit handling interrupts. Vectored interrupts have Segment offset. The segment number serves as a higher priority than non-vectored interrupts. This _ logical name of a segment ; itis not altered by the priority scheme allows the efficient control of many effective address calculation (by indexing, for peripheral devices in a 28000 system. example). This corresponds to the way memory is. . . typically used by a program -one portion of the An interrupt causes information relating to the cur memory is set aside to hold instructions, another rently executing program (program status) to be for data. In a segmented address space, the in- saved on a special system stack with a code de- structions could reside in one segment (or several scribing the reason for the switch. This allows _gifferent modules in different segments), and each recursive task switches to occur while leaving the gata set could reside in a separate segment. One normal stack undisturbed by system information. advantage of segmentation is that it speeds up The program state to handle the interrupt (new address calculation and relocation. Thus, segmen- program status) is loaded from a special area in tation allows the use of slower memories than memory, the program status area, designated by a inear addressing schemes allow. In addition, seg- pointer resident in the CPU. ments provide a convenient way of partitioning The use of the stack and of apointertotheprogram Memory so that each partition is given particular status area is a specific choice made to allow access attributes (for example, read-only). The architectural compatibility if new interrupts or traps 28000 approach to segmentation (simultaneous are added to the architecture access to a large number of segments) is necess- ary if all the advantages of segmentation are to be Multi-Processing. The increase in microproces-_eatized. A system capable of directly accessing sor computing power that the Z8000 represents —_ only, say, four segments would lack the needed makes simple the design of distributed processing flexibility ‘and would be constrained by address systems having many low-cost microprocessors space limitations. running dedicated processes. Memory Management. Memory management The Z8000 provides some basic mechanisms that _ consists primarily of dynamic relocation, protection, allow the sharing of address spaces among differ-_ and sharing of memory. It offers the following ad- ent microprocessors. Large segmented address _vantages : providing a logical structure to the mem- spaces and the support for external memory man- _ory space that is independent of the actual physical agement make this possible. Also, a resource re-_lacation of data, protecting the user from inadver- quest bus is provided which, in conjunction with tent mistakes such as attempting to execute data, software, provides the exclusive use of shared __ preventing unauthorized access to memory resour- critical resources. These mechanisms, and new ces or data, and protecting the operating system peripherals such as the Z8038 FIO, have been _from disruption by the users. designed to allow easy asynchronous communica- tion between different CPUs. J 5

28001,2 CPU — Architecture (Continued) The addresses manipulated by the programmer, _single word ; this format may be used by assem- used by instructions, and output by the segmented _blers and compilers. 28000 CPU are called logical addresses. The €x- The largest reduction in program size and increase ternal memory management system takes the logi- in. speed results from the consistent and regular cal addresses and transforms them into physical structure of the architecture and from the more addresses required for accessing the memory. This powerful instruction set -factors that substantially address transformation process is called reloca- —_ reduce the number of instructions required for a tion, which makes user software independentofthe —_ task. The architecture is more regular relative to physical memory. Thus, the user is freed from preceding microprocessors because its registers, specifying where information is actually located in address modes, and data types can be used in a the physical memory. more orderly fashion. Any general-purpose register The segmented Z8000 CPU supports memory except RO can be specified as an accumulator, management both with segmented addressing and _index register, or base register. With a few excep- with program-status information. A segmented ad- _ tions, all basic addressing modes can be used with dressing space allows individual segments to be _ill instructions, as can the various data types. treated differently. General-purpose registers do not have to be Program status information generated by the CPU_ changed as often as registers dedicated to a specific permits an external memory management device Purpose. This reduces program size, since frequent to monitor the intended use of each memory ac- _!0ad and store operations are not required. cess. Thus, illegal types of access can be sup- Compiler Efficiency. For microprocessor users, Pressed and memory segments protected from _the transition from assembly language to high-level unintended or unwanted modes of use. For —_ languages allows greater freedom from architectu- example, system tables could be protected from —_ral dependency and improves ease of programm- direct user access. This added protection capability _ ing. However, rather than adapt the architecture to becomes more important as microprocessors are particular high-level language, the Z8000 was applied to large, complex tasks. designed as a general-purpose microprocessor. (Tailoring a processor for efficiency in one language Benefits of the Architecture often leads to inefficiency in unrelated languages). provide several significant benefits :improvements in rinimize typical compilation and code-generation code density, compiler efficiency, operating system bl Al the feat isthe larity of t, and support for high level data structures. problems. Among these features is the regularity o support, PPO 'g the 28000 addressing modes and data types. Ac- Code Density. Code density affects both proces- cess to parameters and local variables on the sor speed and memory utilization. Code compac- _ procedure stack is supported by the "Index With tion saves memory space -an especially important Short Offset" addressing mode, as well as the Base factor in smaller systems- and improves processor Address and Base Index addressing modes. In speed by reducing the number of instruction words —_adgition, address arithmetic is aided by the Incre- that must be fetched and decoded. The Z8000 ment and Decrement instructions. offers several advantages with respect to code ing of data, logical evaluation, initialization, and ensiy. The mest frequent used instructions are Testingot data, logical evaluation intiaization and encoded in single-word formats. Fewerinstructions structions Test, Test Condition Codes, Load Imme- are “reeded 10 accomplish @ given task and @ gate Into Memory, and Compare Immediate With Consistent and regular arc itecture furtherreduces Memory, Since compilers and assemblers fre- the number of instructions required. quently manipulate character strings, the instruc Code density is achieved in part by the use of tions Translate, Translate And Test, Block special "short" formats for certain instructions Compare, and Compare String all resultin dramatic which are shown by statistical analysis to be most —_ speed improvements over software simulations of frequently used by assemblers. A “short offset" these important tasks. In addition, any register mechanism has also been provided to allow a _ except RO can be used as a stack pointer by the 2-word segmented address to be reduced to a —_ Push and Pop instructions. 6 -

8007.2 CPU

Operating System Support. Interrupt and task- supported in the 78000 by the index and the Base switching features are included to improve opera- Index addressing mode and by segmented ad- ting system implementations. The dressing. The Base Index addressing mode allows memory-management and compiler-support fea- the use of pointers into an array (i., offsets from tures are also quite important. the array’s starting address). Segmented address- The interrupt structure has three levels : non-mask- ing allows an array to be assigned to one segment, able, non-vectored, and vectored. When an interrupt Which can be referenced simply by segment num- occurs, the program status is saved on the stack with 8" an indication of the reason for this state-switching _Lists occur more frequently than arrays in business | before a new program status is loaded from a special applications and in general data processing. Lists | area of memory. The program status consists of the are supported by Indirect Register and Base Ad- flag register, the control bits, andthe program counter. dress addressing modes. The Base Index address- The reason for the occurence is encoded in a vector —_ing mode is also useful for more complex lists. that is read from the system bus and saved on the +446 are used in all applications for nesting of stack. In the case of a vectored interrupt, the vector ea ee a So also determines ajump table address that pointstothe outines, ee structured languages, and interrupt interrupt processing routine. handling. Stacks are supported by the Push and Pop instructions, and multiple stacks may be im- The inclusion of system and normal modes im- —_ plemented based on the general-purpose registers proves operating system organization. In the sys- of the Z8000. In addition, two hardware stack poin- tem mode, all operations are allowed ; in the ters are used to assign separate stacks to system normal mode, certain system instructions are pro- —_and normal operating modes, thereby further sup- hibited. The System Call instruction allows a con- porting the separation of system and normal oper- trolled switch of mode, and the implementation of ating environments discussed eariier. traps enforces these restrictions. , ; Byte and word strings are supported by the Trans- Traps resultin the same type of program status-saving_—_ate and Translate And Test instructions. Decimal as interrupts in both cases, the information saved is strings use the Decimal Adjust instruction to do pushed on to a system stack that keeps the normal —_ decimal arithmetic on strings of BCD data, packed stack undisturbed. The Load Multiple instruction allows two characters per byte. The Rotate Digit instruc- the contents of registers to be saved efficiently in tions also manipulate 4-bit data. memory or on the stack. Running programs can cause program status changes under direct software control Two CPU Versions : Z8001 and Z8002. The with the Load Program Status instruction. 28000 CPU is offered in two versions : the 28001 . ran . 48-pin segmented CPU and the Z8002 40-pin non- Finally, exolusion and serialization can beachieved segmented CPU. The main difference between the with the "atomic" Test And Set instruction that syn- two is addressing range. The 28001 can directly chronizes asynchronous cooperating processes. address 8M bytes of memory ; the 28002 directly Support for Many Types of Data Structures. A _ addresses 64K bytes. The Z8001 has a non-seg- data structure is a logical organization of primitive mented mode of operation which permits it to ex- elements (byte, word, etc.) whose format and ac- _@cute programs written for the Z8002. cess conventions are well-defined. Common data ot all applications require the large address space structures include arrays, lists, stacks, and strings. gf the 78001 ; for these applications the 28002 is Since data structures are high-level constructs fre- recommended. Moreover, many multiple-proces- Quently used in programming, processor perfor” sor systems can be implemented with one 28001 mance is significantly enchanced if the CPU ang severals 2802s, instead of exclusively using provides mechanisms for efficiently manipulating —_7gq91s. Since the same assembler generates them. The Z8000 offers such mechanisms. code for both CPUs, users can buy only the power In many applications, one of the most frequently they require without having to worry about software encountered data structures is the array. Arrays are incompatibility between processors. . 7

Z8001,2 CPU Extended Instruction Facility The 28000 architecture has a mechanism for ex- memory spaces, segmented addresses, and sup- tending the basic instruction set through the use of port for multiple processors are beyond the capa- external devices. Special opcodes have been set bilities of the traditional microprocessor. The aside to implement this features. When the CPU benefits of this architecture -code density, compiler encouters an instruction with these opcodes in its support, and operating system support- greatly instruction stream, it will perform any indicated ad- enhance the power and versatility of the CPU. The dress calculation and data transfer ; otherwise, it will CPU features that support an external memory treat the “extended instruction" as being executed management system also enhance the CPU's ap- by the external device. Fields have been set aside —_plicabilty to large system environments. in these extended instructions which can be inter- preted by external devices (Extended Processing Units -EPUs) as opcodes. Thus, by using appropri- Register organization ate EPUs, the instruction set of the Z8000 can be PI A , hi extended to include specialized instructions. The 2800 CPU is a register-oriented machine that . offers sixteen 16-bit general-purpose registers and In general, an APU is dedicated to performingcom- _a set of special system registers. All general-pur- plex and time-consuming tasks in ordertounburden —_poge registers can be used as accumulators and the CPU. Typical tasks suitable for specialized aii but one as index registers or memory pointers. EPUs include floating-point arithmetic, data base i search and maintenance operations, network inter- Register flexibility is created by grouping and over- faces, graphics support operations -a complete ist lapping multiple registers (Figure 1-3a and 1-3b). would include most areas of computing. For byte operations, the first eight 16-bit registers (RO...R7) are treated as sixteen 8-bit registers Summary ters are grouped in pairs (RRO ... RR14) to form The architectural sophistication of the Z8000 micropro- 32-bit long-word registers. Similarly, the register set cessor is on a level comparable with that of the minicom- is grouped in quadruples (RQO ... RQ12) to form puter. Features such as large address spaces, multiple 64-bit registers. Figure 1-3a. Z8001 General-Purpose Registers Figure 1-3b. Z8002 General-Purpose Registers ze001 z8002 8 x

Z8001,2 CPU Instruction Set Summary The 28000 provides the following types of instruc- _ — Bit Manipulation tons = Rotate and Shift. — Load and Exchange. — Block Transfer and String Manipulation. — Arithmetic. — Input/Output. ~ Logical. — CPU Control. — Program Control. Load and Exchange Clock Cycles“? Mnemonics Operands ys{u". Word, Byte —~—~‘Long Word” Operation \\ NS ss SL NS SS SL “cur dst R 7 Clear CLRB IR 8 : - dst 0 | DA " 12 14 x 2 12015 : EX Risto R 6: Exchange EXB Ro Rese | DA «15 168 : x 16 16 19 | Lo R.sre R 3+ + 5 Load into Register | LOB iM 7 te Rest | oe iM 5 (byte only) | IR 7 : - abl - : DA «9 «10 «12121348 | | x 10 10 13 13 13 16 | BA 14 - 7 . BX 14 : - 47 : : | Lo otk OR 8 = = f= = Load into Memory (Store) f LOB DA W 12 14 14 15 17° dst-—R LOL x 12 12 15 15 15 18 BA 14 Te Bx 14 - - 17 - j i dstIM Rot Load Immediate into Memory | LOB DA 14 15 17 dst «IM xX 1 1 18 LDA Rysre DA 12 13 15 Load Address xX 13 13 16 Ree source address BA 1B : BX 15 - - | LOAR Reco RA 15 : Load Address Relative ! Rie source address LK Rs IM 5 Load Constant | ! Ren(n=0... 15) | LDM Reon IR ot Load Multipe | DA 14 15 17 > +3n R © src (n consecutive words) i} xX 15 15 18 (vet. 18) LOM dst,R,n IR W : - | Load Multiple (Store Multiple) DA 14 1517 > +3n dst — R (n consecutive words) i eT

Z8001,2 CPU Load and Exchange (Continued) t Clock Cycles “ Mnemonics Operands Addr. Word, Byte Long Word Operation : NS SS SL NS SS SL_ j “LDR Rysre RA 14 - - 17 == Load Relative I LORB Re sre LORL (range - 32768 ... + 32767) LOR dst.R RA 14 - 17 = = Load Relative (Store Relative) | LDRB dst R j LORL (range - 32768 ... + 32767) | POP st R 8 - = 12 =. Pop POPL IR 12 - : 19 : - dst — IR DA 16 «16 = 18_=—-23_ «23.25 Autoincrement contents of RL x 1% 16 19 23 23 26 | PUSH Isc R Ee PUSHL IM 12 : : - Resre IR 13-20, Autodecrement contents of R i DA 1414 «16 tk x 14 14 17 21 21 24 : Arithmetic ape Rec Ro 8 with Carry S*@d ADCB ReR¢ sre + cary | ADD R,sre R 4 005 7 Be ADDB IM J+ 5 14 eRe ste | ADDL IR rs) | DA 9 1 2 15 16 18 x 10 10 13 16 16 19 | cP Rest R 4 = = 8 = = Compare with Register CPB IM T+ + 18s Rete | cPL IR re DA 9 10 12 15 16 18 i x 10 10 13 16 16 19 i cP dst,IM IR "1 - ‘Compare with Immediate : CPB DA 14 1517 dst - IM x 15 15 18 | —— 1 DAB dst R 5 Decimal Adjust DEC dstia R 4-0 Decrement by n ! DECB IR Ww : - dst — dst -n DA 13001416 (n= 1... 16) x 41417 bv Rare R107 = 74 = vide (signed) j DIVL IM 107 - - 744 - Word : Rn. 1 Rans 1+ SrC | IR 107. 107. «107/744 7440 744 Ro & remainder DA 108 108111745746 748 Long Word : Rn. 2ne3 Rain +3 x 108. 109 «112 «746 «7460749 +src Ran «1 © remainder j EXTS dst R 1" - if = Extend Sign | EXTSB Extend sign of low order half of dst | EXTSL through high order half of dst 10 -THOMSON

Z8001,2 CPU Arithmetic (Continued) Clock Cycles Mnemonics Operands yoges Word, Byte Long Word Operation NS ss SL NS SS SL INC dstin R 400-0 Increment by n INcB IR " - dst — dst+n x 14 14 17 MULT Risto R 70 - 282" = = Multiply (signed) MULTL. IM 70 = BB = Word: Rain es = Rr 1 + 810 IR 70 - - 282" - = Long Word : Ran. 3— Rev anss DA 71 7274 «283" 284 286" “Plus seven cycles for each'1 in x 72 72 75 284" 284* 287° the multiplicand NEG dst R 7. Negate NEGB IR 2. dst—0-dst DA 15 16 18 x % 6 19 | spc Rise R 5 - - Subtract with Carry | SBCB ReR-src- cary | ‘SUB R,sre R 4 : : 8 - - Subtract | SUBB IM 7: 1400 = 0 - RER- sre i susL IR rs ' DA 9 10 12 15 16 18 x 10 10 13 16 «616 «(19 Logical AND Rec A 40-0 AND : ANDB IM 7 Re RAND sro IR 7 - - i DA 9 10 12 | x 10 10 «13 i com dst R 7 Complement ' come in 2 0. dst < NOT dst DA 615 68 x 16 16 19 oR Risre R 4 5: oR ORB IM 77 ReRORStc IR 7. : DA 9 10 12 1 x 10 10 13 i Tec cc,dst R 5 Test Condition Code | CCB Set LSB if ccis true ! — Ed TEST dst R 7 - 13 - - Test | Teste IR 8 - = 13 = = dstORO TESTL DA Ww 12 14 16 17 19 x 120 12 «18 «17:17 XOR Rasre R 40-0 Exclusive OR | XORB IM 7. ReRXOR sre ' IR 7 - - | DA 9 10 12 x 10 10 «13 :

7 S6S-THOMSON ul

2Z8001,2 CPU Program Control esse Clock Cycles | i Addr, i | Mnemonics Operands odes Word, Byte Long Word Operation i | NS sS SL NS SS SL CALL dst IR 10-45 - "Call Subroutine DA 12 18 20 Autodecrement SP x 13 18 ral @SP« PC PC — dst CALR dst RA 10-5 Call Relative ! Autodecrement SP @sSP«<PC PC < PC + dst (range -4094 to +4096) | DUNZ Ridst RA 1h Decrement and Jump if Non-Zero | DBUNZ ReR-1 \\ IfR*0:PC—PC +ost i (range -254 to 0) : IRET® - 13 - 16 Interrupt Return PS + @SP Autoincrement SP JP cc,dst IR 10 - 15, (taken) Jump Conditional IR 7 - 7 (not taken) Ifecis true: PC < dst DA 7 8 10 i x 8 8 W ‘JR cc,dst RA 6 a . Jump Condition Relative If cc is true: PC < PC + dst (range -256 to +254) RET ce : 10 13 (taken) Return Conditional 1 7 7 (not taken) if cc is true : PC — @ SP \\ Autoincrement SP sc sre IM 3300-9 System Call Autodecrement SP @ SP — old PS Push instruction PS « System Call PS. Bit Manipulation | err dst.8 R 4 Test Bit Static BITB IR 8. Z flag — NOT dst bit specified by b i DA 10 "1 13 1 x W W 14 BIT dst.R R 10 - : Test Bit Dynamic BITB Z flag — NOT dst bit specified by Contents of R RES dst R 4-0. Reset Bit Static RESB IR too. Reset dst bit specified by b DA 13 14 16 x 14 14 7 RES dstR R oo - Reset Bit Dynamic | RESB Reset dst bit specified by contents R 12 (jy SGS-THOMSON TT SES 08

2Z8001,2 CPU Bit Manipulation (Continued) Clock Cycles _ Mnemonics Operands sade. ~~ Werd,Byte LongWord Operation NS SS SL NS SS SL SET dst.b R 4. Set Bit Dynamic SETS IR moo. Set dst bit specified by b DA 13 14 16 x 4014 «17 SeT oth OR 0 8- Set Bit Dynamic SETB Set dst bit specitied by contents of R TSET dst R 7 - : Test and Set TSETB IR W - - S flag — MSB of dst DA 14 15 17 dst < all 1s x 15 1518 Rotate and Shift TRL dsin R 6torn=1 Rotate Lett i RLB R Tiorn=2 by n bits (n = 1, 2) RLC dstn R 6torn=1 Rotate Left through Carry RLCB R Ttorn=2 by n bits (n= 1, 2) RLDB Aso Ro 9. " Rotate Digit Left RRO stn R 6torn=1 Rotate Right RRB R 7iorn=2 by nbits (n= 1,2) RRC dst.n R 6 forn=1 Rotate Right through Carry i RRCB R 7 forn=2 by n bits (n= 1,2) | fp EOI RRDB Rsre R 9 : . Rotate Digit Right | poe Eee SDA dst. R (15 +3n) (15 + 3n) Shift Dynamic Arithmetic | SDAB Shift dst left or right SDAL by contents of R SDL dstR R (15 + 3n) (15 + 3n) Shift Dynamic Logical SDLB Shift dst left or right SDLL by contents of SLA dstin R (13 + 3n) (13 + 3n) Shift Left Arithmetic SLAB by n bits ‘SLAL | SLL dst.n R (13 + 3n) (13 + 3n) Shift Left Logical | SLLB by n bits ‘SLLL | SRA dst,n R (13 + 3n) (13 + 3n) Shift Right Arithmetic i} SRAB by n bits SRAL | SRL dstn R (13 + 3n) (13+ 3n) Shift Right Logical ‘SRLB by n bits SRLL ‘SGS-THOMSON 13.

Z8001,2 CPU Block Transfer and String Manipulation Clock Cycles “ 'Mnemonics Operands 4c". Word, Byte Long Word Operation ' NS SS SL NS SS SL cPD RxsreRycc IR 20 - - Compare and Decrement | CPDB Rx - sre | Autodecrement src address | Rye Ry-1 (CPDR | AxstcRy.co IR (11 + 99) ‘Compare, Decrement and Repeat | CPDRB Rx- sre Autodecrement src address \\ Rye Ry-1 L Repeat until cc is true or Ry = 0 (cP AxsteRy,co IR 2 - ~~ Compare and Increment | CPIB Rx - sre | ‘Autoincrement sre address | Ry Ry-1 | cPIR AxsrcRy,co IR (11 + 99) Compare, Increment and Repeat CPIRB Rx - sro Autoincrement src address. | Rye Ry-1 L Repeat until cc is true or Ry = 0 CPSD—dstisroAcc IR 25 - ‘Compare String and Decrement CPSDB dst - sre Autodecrement dst and sre | addresses | ReR-1 TCPSDR dstsrcRcc | IR (11+ 14n) ‘Compare String, Decr. and Repeat | CPSDRB dst - sro | Autodecrement dst and src 1 addresses

1 ReR-1

: Repeat unti cc is true or R = 0 : CPSI dst,src,R,cc IR 25 : Compare String and Increment cPsia dst - sre Autoincrement dst and src addresses ReR-1 CPSIR_—dstsrc.Rcc IR (11+ 14n) ‘Compare String, Incr. and Repeat CPSIRB dst - src Autoincrement dst and sre addresses ReR-1 Repeat unti'cc is true or R= 0 Lop dstscR IR 200 - Load and Decrement Lope dst src Autodecrement dst and sre addresses ReR-1 LDDR dstrscR IR (11 + 9n) Load, Decrement and Repeat LODRB dst — src Autodecrement dst and src addresses ReR-1 Repeat until R = 0

1 G57 S6S-THOMSON

Z8001,2 CPU Block Transfer and String Manipulation (Continued) Clock Cycles") Mnemonics Operands Aad" a ete ~SCLeng Word Operatic perands Modes Word, Byte Long Word )peration NS SS SL NS SS SL Lol dstsoR IR 200 Load and Increment LDIB dst — src Autoincrement dst and sre addresses ReR-1 LOIR dstsR IR (11+ 9n) Load, Increment and Repeat LDIRB dst < sre Autoincrement dst and src addresses ReR-1 Repeat until R = 0 TROB dstsoR IR 5 Translate and Decrement dst < sre (dst) Autodecrement dst address ReR-1 TRORB = dstsrc,R_— IR (11 + 14n) Translate, Decrement and Repeat dst < src (dst) ! Autodecrement dst address ' ReR-1 i Repeat until R = 0 | TRIB dst,src,R IR 25 : - Translate and Increment H dst < src (dst) Autoincrement dst address i ReR-1 1 fo TRIRB dstsrcR IR (11 + 14n) Translate, Increment and Repeat dst < src (dst) Autoincrement dst address \\ ReER-1 ! Repeat until R = 0 TRTDB = sictse2QR IR 25 Translate and Test, Decrement RH1 < src? (srct) i Autodecrement src1 address ReR-1 { TRTORB = srci,src2,R IR (11 + 14n) Translate and Test, Decr.and Repeat ' RH1 & src? (srct) Autodecrement src1 address ReR-1 Repeat until R = 0 or RH1 = 0 TRTIB src1,src2,R_ IR 25 - - ‘Translate and Test, Increment RH1 ¢- src2 (srct) Autoincrement srct address i ReR-t TRTIRB src1,src2,R IR (11 + 14n) Translate and Test, Incr. and Repeat RH1 © sre2 (srt) Autoincrement src1 address ReR-1 Repeat until R = 0 or RH1 = 0

7 SS-THOMSON 15

Z8001,2 CPU Input/Output Clock Cycles Mnemonics Operands A%c, word, Byte ~~-~Leng Word Operation NS sS SL NS SS SL In? Rasre IR 10 - - Input INB ® DA 12 : - Re sre Ind ® dstsrcR IR 2t : : Input and Decrement INDB ®) dst — sro Autodecrement dst address ReR-1 INDR® — dst.sro,R IR (11 + 10n) Input, Decrement and Repeat INDRB @ dst — sre ‘Autodecrement dst address ReR-1 Repeat until R = 0 INL? dtscR IR te Input and Increment _ ine ® dst — sre Autoincrement dst address ReER-1 INIR ?) dst,sre,R IR (11 + 10n) Input, Increment and Repeat INIRB ® dst < src Autoincrement dst address ReR-1 Repeat until R = 0 out ®) dst,R IR 10 - : Output outs DA 12 : : dst R ouTD ?— dstisrc.R IR at : : Output and Decrement ouTDB dst — src ‘Autodecrement src address ReR-1 OTOR @— dst.srcR IR (11 + 10n) Output, Decrement and Repeat OTDRB ® dst — sro Autodecrement src address ReR-1 Repeat until R = 0 OuTl® dsisoR Rt Output and Increment outs ? dst — sro Autoincrement src address RR comin dst.src,R IR (11 + 10n) Output, Increment and Repeat OTIRB dst — sro Autoincrement src address ReR-1 Repeat until R = 0

16 SGS-1

Z8001,2 CPU Input/Output (Continued) Clock Cycles Addr, i Mnemonics Operands yaoges Word, Byte Long Word Operation NS SS SL NS SS SL SIN?) Risto DA 12 - - Special Input SINB ® Resre | SIND ? dstsrc,R IR a - : Special Input and Decrement | SINDB dst < src Autodecrement dst address ROR-t SINDR — dst,src,R IR (11 4 10n) Special Input, Decr. and Repeat SINDRB 7 dst — src ‘Autodecrement dst address ROR-1 Repeat until R = 0 “sin, ® dst.src,R IR 24 : - ‘Special Input and Increment i SINIB dst < sro | Autoincrement dst address ReR-1 SINIR dst.src,R IR (11 + 10n) Special Input, Incr. and Repeat SINIRB dst « sro | ‘Autoinorement dst address ReR-t Repeat until R = 0 out ® dst.src DA 12 : - Special Output souTs ? dst — sre SE SOUTD ® dstisrc,R IR at : Special Output and Decrement | souTos ® dst < sre ' ! Autodecrement sre address } | ReR-1 | SOTDR ® dstsrc,R_ IR (11 + 10n) Special Output, Decr. and Tepes] SOTDRB dst — src | Autodecrement src address | | ReR-1 | | Repeat until R = 0 | | SOUTI?— dst,sre,R IR 24 - - ‘Special Output and Increment souTis ? dst — src Autoincrement sre address ReR-1 SOTIR® ~— dst.src,R IR (11 + 10n) ‘Special Output, Incr. and Repeat SOTIRB dst «= sro ! Autoincrement src address ROR-1 Repeat until R = 0 | CO eS G57 S6S-THOMSON wv

Z8001,2 CPU CPU Control Clock Cycles | Mnemonics Operands 4°. word, Byte ‘Long Word Operation NS SS SL NS SS SL_ COMFLG flags : 7 OO ‘Complement Flag (Any combination of C. Z. S, P/V) a1?) int - 7 - - Disable Interrupt (Any combination of NVI, VI) B® int - 7 : : Enable Interrupt (Any combination of NVI, VI) HALT? - - (8 + 3n) HALT upeTL” = CTLAs «= R 7 : : Load into Control Register CTLR « src LoctL® dst.CTLR oR 7 : - Load from Control Register dst — CTLR LDCTLB §FLGRsc | R 7 Oe Load into Flag Byte Register FLGR « sre LOCTLB = dstFLGR—-R 7. Load from Flag Byte Register dst FLGR Lops ® src IR 12 - 16 Load Program Status DA 16 2022 PS < sic x 17 20 23 pit ® . : 7 : - Test Multi-Micro Bit _ Sot S if Mis Low ; reset S if Mi is High. MREQ® dst R (12 + 7m) Multi-Micro Request mres : 5 : : Multi-Micro Reset [ser ® : : 5 Multi-Micro Set | NOP. - : 7 - - No Operation | RESFLG flag : 72 Reset Flag | (Any combination of C, Z. S, P/V) a — — me an | SETFLG flag : 7 : : Set Flag (Any combination of C, Z, S, P/V) Notes : 1. NS=Non-Segmented ‘SS = Segmented Short Offset SL = Segmented Long Ottset. 2. Privileged instruction. Executed in system mode only. 18° SGS-THOMSON

Z8001,2 CPU Condition Codes Code | Meaning Flag Settings CC Field i Always false - 0000 | Always true : 1000 Zz Zero Z=1 0110 NZ Not zero Z=0 1110 Cc Carry Cat { omit NC No Carry C=0 4111 PL Plus S=0 N01 Mi Minus S=1 0101 NE Not equal Z=0 ] 1110 EQ Equal Z=1 o110 ov Overflow PV st 0100 NOV No overflow PV =0 1100 PE Parity is even PV =1 0100 PO Parity is odd PV=0 1100 GE Greater than or equal (signed) (S XOR P/V) = 0 1001 ur Less than (signed) (S XOR P/V) =1 0001 GT Greater than (signed) [ZOR (S XOR P/V)] =0 1010 LE Less than or equal (signed) [Z OR (S XOR P/V)] = 1 0010 UGE Unsigned greater than or equal C=0 11 | ULT Unsigned less than C=1 ont | UGT Unsigned greater than ((C =0) AND (Z=0)}=1 1011 ULE Unsigned less than or equal (CORZ)=1 0011 iL Note that some condition codes have idertical flag settings and binary eld in the instruction Z= £0, NZ =NE, C = ULT.NC » UGE, OV » PE, NOV = PO G57 SGS-THOMSON 19 TO OF tc —£_

2Z8001,2 CPU PIN CONFIGURATION Introduction This chapter covers the external manifestations — Stop request. This type is used to delay CPU (e.g., the activity on the CPU pins) that result from instruction execution the operations described in prerious chapters. When an interrupt or bus request is made, it is Since the pins are connected to the system bus answered by the CPU according to its type : for mugh of the discussion will center on the bus and interrupt request, an interrupt acknowledge trans- bus operations. The 28000 CPU is designed to be —_actionis initiated ; for bus requests, the CPU enters compatible with the Z-BUS protocols, which are Bus Disconnect state, relinguishes the bus, and described in the Z-BUS Summary. In the sections activates an acknowledge signal ; for stop re- that follow, the interface between the Z8000 CPU quests, the CPU stops execution and enters and its environment is described in detail. Stop/Refresh state. A resource request is gener- ated by the CPU when it executes a multi-micro Bus Operations request instruction Two kinds of operations can occur on the system bus : transactions and requests. At any given time, Cpu Pins one device (either the CPU orabus requester, such the CPU pins can be grouped into five categories as the 28016 DMA Controller) has control of the according to their funcrona. 9 bus and is known as the bus master. A transaction is initiated by the bus master and is responded to _— Transaction Pins. These signals provide timing, by some other device on the bus. Only one trans- control, and data transfer for Z-Bus transactions. action can proceed at a time ; six kinds of transac- — ADo-AD1s. Address/Data (Output, active tions can occur : High, 3-state). These multiplexed data and ad- ig — Memory transaction. This type is used to trans- dress lines carry VO addresses, memory ad- fer eight or 16 bits of data to or from a memory dresses, and data during Z-Bus transactions. location For the 28001, only the offset portion of memory ~ VO transaction. This type is used to transfer addresses is carried on these lines. eight or 16 bits of data to or from a peripheralor © — SNo-SNz. Segment Number (28001 only, Out- CPU support component, such as an MMU put, active High, 3-state). These lines contain - EPU transfer. This type is used to transfer 16 the segment number portion of a memory ad- bits of data between the CPU and an EPU Sto_8Ts. (Out High, 3-state) _ - STo-ST3. utput, active, High, 3-state, interrupt Trap Acknowledge. This type is used These lines indicate the kind of transaction oc- to acknowledge an interrupt or trap and to trans- curing on the bus and give addtional informa. fer an identification/status word from the inter- tion about the transaction (such as the address none eens device do rot tanst space for memory transactions). — Refresh. ese transactions do not transfer ze ; — KS. Address Strobe (Output, active Low, 3- data. They refresh dynamic memory slate). The rising edge of AS indicates tho be. ~ Internal operation. These transactions do not ginning of a transaction and shows that the transfer data. They indicate that the CPU is Address, STo - STs, W/S, RW, and BIW signals performing an operation that does not require are valid. Sata to be transferred on the bus ~ DS. Data Strobe (Output, active Low, 3-state). Only the bus master may initiate transactions. A DS provides timing for data movement to or from request, however, may be initiated by a component the CPU. that does not have controlofthebus.FourtyPesot —_ wy aeagwrite (Output, Low = Write, 3- requests can ocour : state). This signal determines the direction of ~ Interrupt request. This type is used to request data transfer for memroy, I/O, or EPU transfer the attention of the CPU transactions. ~ Bus request. This type is used to request control __ B/W. Byte/Word (Output, Low = Word, 3-state). of the bus to initiate transactions This signal indicates whether a byte or word of - Resource request. This type is used to request data is to be transmitted during a transaction. control of a particular system resource 20 5) So Bp ScsTHomson

28001,2 CPU Figure 2-1. 28001 Pin Configuration Figure 2-2. Z8002 Pin Configuration | Bae soy G2 oD | 20 B A06 woo G3 6B as avi Ge 39 Pave won qe © BP wm, aon Gs 38 B an; wow Gs 4 Bl t06 vow Ge v7 B Ave ao Gs 3D a. sors G5 x B avs se 7 2D oy so ds 35 Boats a ds « B ws a dq? 34 B avy sis Ga © B 15 sos Ge 33 Bl a0, vou 10 Bom. 10 Ge 32 BL Ab: vee Go zeo01 8 B Ao vec G1 28002 5) Fano v G2 secopu x B sx w qr SPY 35 Bcoce m Ge 3B oo m die 2 BS aor que ss B coc wi Gs 2a B eescaue wm Gis “ps ast que 27 Baya wet dis 33 [7 reserveo wo Gis 26 PN/s eqn 2B ew wea 2s Ba/w ma Gwe » Bw = dv 24 Bi ausacx = qv so B ew sy doe 23 B wat sts Gao 29D BSA siz Gas 22D a0O sta Gar 23 Bani st; 20 2B sto sy G2 7 Bp aR sto Gas a B sig os Gx 2 Boxy voor ss2 v2001393 , EReL ar Be CS

Z8001,2 CPU CPU Pins (Continued) ~ WAIT. (Input, active Low). A Low on this line - NVI. Non-Vectored Interrupt (Input, active indicates that the responding device needs Low). ALowon this line requests anon-vectored more time to complete a transaction, interrupt. - MREQ. Memory Request (Output, active Low, - VI. Vectored Interrupt (Input, active Low). A 3:-state). A falling edge on this line indicates that Low on this line requests a vectored interrupt. the address/data bus is holding a memory ad __SE@T_ segment Tap (28001 ony, Input, active dress. Low). A Low on this line requests a segment Bus Control Pins. These pins carry signals for trap. fequesting and obtaining controlofthebus irom the mutteeicro Pins. These pins are the Z8000's CPU. interface to the Z-BUS resource request lines. ~ BUSREG. Bus Request (Input, active Low). gl yuti-micro in (Input, active Low). This input Low indicates that a bus requester has obtained is used to samplo the stale at to hese oF is trying to obtain control of the bus. request ines - BUSACK. Bus Acknowiedge (Output epg ~ MO. Multi-Micro Out (Output, active Low). This has relinquished control of the bus in response tine is used by the CPU to make resource re- to a bus request. quests. 7 , CPU Control. These pins carry signals which Interrupt/Trap Pins. These pins convey interrupt and external rap requests toe GPU. contr the overall operation ofthe CPU. — NMI Non-Maskable Interrupt (Input, Edge ac. ~ STOP. (Input, active Low). This line is used to tivated). A High-to-Low transition on NM re. Suspend CPU operation during the fetch of the quests a non-maskable interrupt rst word of an instructio - RESET. (Input, active Low). A Low on this line resets the CPU 22 01

Z8001,2 CPU Figure 2-4. Pin Functions | Ss AD 15 7 | a, Ss ——— mrReEQ 13 | AD 12 | READ /WRITE .° " | TRANSACTIONS NORMAL /SYSTEM ape | BYTE /WORD 9 | AD 8 ADDRESS/ | ST AD 7 DATA BUS S12 zgo01 *26 ST! zgoo2 4° 5 | sto “cpy 40 4 | __ AD 3 ceu € - WAIT AD 2 | CONTROL STOP AD 4 AD o J CONTROL BUSACK 1 SN 6 78001 | | ! SN ONLY | —_ 1 5 1 | NMI 1 SN 4 i] INTERRUPTS { vw 1 SN3 SEGMENT Nui ! SN > NUMBER: 1 - 1 SN 4 fl | MULTI-MICRO { MI | SNo \\ CONTROL wo | SECT SEGMENT = |

1 TRAP '

Vec GND CLK VRO01248 | Gf SES-THOMSON na

ZB001,2 CPU Figure 2-5. Transaction Timing BAT soles HAT somal tr setinanly and NO oe icsupt/ ato on AD sen eas crs Fou en Sin ces Kern ole 1/0 SEN Se areal se B ee teas SRT ee (agoress [> [ STROBE) A toting insects fst rang inate ol natn oc eye 8) a teat Te Seo ae Sat SNo-SNg a NO) ose ote ck Sle ioe ve ot soe ADg~ AD} 5 caress a> OFFSET) — fee cotton see Reed Ain STg-STy R/WB/W,S/N IATUS INFORWATH a a CT INFORMATION) ects mommorleconce pu'ine Saareen ond Yes cine a 5s 1/0 tronsters (DATA Neary, EU tenses ont STROBE) Meret /vep scenonseye ~X READ | Age a ert ge oe PU Fama Gale oS ine SS Aoi reeies |, ine Shoes by tne CPU os — - (Data STROBE) WRITE fog onset tne cy 24 -THOMSON + hyp sestomsow

2Z8001,2 CPU Transactions Data transfers to and from the CPU are accom- __ation transactions do not transfer any data and thus plished through the use of transactions. Figure 2-5 do not activate DS.) For write operations (R/W = shows the general timing for a transaction. Low), a Low on DS indicates that valid data from ; the bus master is on the ADo - ADis lines. For read All transactions start with Address Strobe (AS) operations (RAW = High), the bus master makes being driven Low and then raised High bythe CPU. Do - AD15 3-state before driving DS Low so that On the rising edge of AS, the status lines STo- STs __ the addressed device can put its data on the bus. are valid ; these lines indicate the type of transac- The bus master samples this data on the falling tion being initiated (see Table 2-1 ; the six types of clock edge just before raising DS High. transactions are discussed in the sections that follow). Associated with the status lines are three WAIT. As shown in Figure 2-5, WAIT is sampled other lines that become validat this time. Theseare 0" a falling clock edge one cycle before data is Normal/System (N/S), Read/Write (R/W), and Sampled by the CPU (Read) or DS rises (Read or Byte/Word (B/W). Except where indicated below, Write). If WAIT is Low, another cycle is added to N/S designates the operating mode of the CPU, _ the transaction before data is sampied or DS rises. RIW designates the direction of data transfer (read ‘| this added cycle and all subsequent cycles to the CPU, write from the CPU), and B/W desig added due to WAIT being Low. WAIT is again nates the length of the data item being transferred. Sampledonthe falling edge and, ititis Low, another cycle is added to the transaction. In this way, the If the transaction requires an address, it too is valid transaction can be extended to an arbitrary length ‘onthe rising edge of AS. No address is requiredtor to accommodate (for example) slow memories or interrupt acknowledge, EPU transfer, or internal —_/O devices that are not yet ready for data transfer. operation transactions. (In the Z8001, the segment wat ; number lines SNo - SNe are valid one clock cycle _[t Must be emphasized that the WATT input is earier to allow for external memory management _SYNchronous. Thus, it must meet the setup and hold times in order for the CPU to function correctly. hardware. rf WRIT ex This requires asynchronously generated WAIT sig- The CPU uses Data Strobe (DS) to time the actual__nals to be synchronized before they are input the data transfer. (Note that refresh and internal oper-. CPU. Table 2-1. Status Code Kind of Transaction ST3-STO Additional Information Internal Operation 0000 | Refresh 0001 ‘| 0010 ‘Standard VO WO Transaction 0011 Special /O

0100 Segment Trap

Ack Porn 0101 Non-Maskable Interrupt Transaction 0110 Non-Vectored interrupt jansac ont Vectored Interrupt

1000 Data Address Space

1001 ‘Stack Address Space, | Memory 1010 Data Address Space, EPU Transfer | ‘Transaction 1011 ‘Stack Address Space, EPU Transfer

1100 Program Address Space,

1 1101 Program Address Space, First Word of Instruction | EPU Transter 1110 | Reserved aah {7 ScS-THOMSON a SO hry OM

Z8001,2 CPU Figure 2-6. Memory Read and Write Transaction Th: Th 12 13 cock A EP hre wast cveuts | rae wr XI es os a as Fe a eg we eer Tomo bs 7 _ Rw vROO1250 26. {77 SGS-THOMSON To ID Si

Z8001,2 CPU Transactions (Continued) Memory Transactions. Memory Transactions halves of the bus, and the proper byte must be move data to or from memory when the CPU selected by testing Ao. For word transfers, (B/W = makes amemory access. Thus, they aregenerated —_Low), all 16 bits are captured by the CPU (Read : during program execution to fetch instructions from RW = High) or stored by the memory (Write : memory and to fetch and store memory data. They R/W = Low). AZ8001 CPU and an Extended Pro- are also generated to store old program status and cessing Unit act like a single CPU with the CPU fetch new program status during interrupt and trap _ providing addresses, status and timing information handling and after reset. As shown in Figure 2-6,a _ and the EPU providing or capturing data. memory transaction is three clock cycles long un- VO Transactions. /O transactions move data to less extended as explained above in WAIT. The or from peripherals or CPU support devices (6.9., status pins, besides indicating a memory transac- ys). They are generated during the execution tion, give the following information : of /O instructions ~ Whether the memory access is to the data ag shown in Figure 2-8, /O transactions are four (1000, 1010), stack (1001, 1011), or program Glock cycles long at minimum, and they may be (1100, 1101) address space. lengthened by the addition of WAIT cycles. The — Whether the first word of an instruction is being extra clock cycles allow for slower peripheral oper- fetched (1101). ation. — Whetherthe data forthe accessis tobe supplied The status lines indicate whether the access is to (write) or captured (read) by an Extended Pro- _ the Standard VO (0010) or Special /O (0011) Ad- cessing Unit (1010, 1011). dress Spaces. The N/S line is always Low, indicat- ing system mode. The V/O address is found on Status codes 1000 and 1001 may also indicate that ADo - ADis when A$ rises. Since the /O address the EPU is to capture or supply the data. is always 16 bits long, the segment number lines For the Z8002, the full memory address willbe on are undefined on Z8001 CPUs. For byte transfers Do - AD1s when AS rises. For the Z8001, the (B/W = High) in Standard /O space, addresses offset portion of the segmented address willbe on Must be odd ; for byte transfers in Special /O ‘Do - ADs and the Segment number portion wil be space, addresses must be even. ‘on SNo - SNe when AS rises. The segment portion — Word data (B/W = Low) to or from the CPU is will also be on SNo - SNe approximately one cycle —_ transmitted on ADo - AD1s. Byte data (B/W = High) before ADo - ADis is valid. is transmitted on ADo - AD; for Standard I/O and on ADg - ADs for Special I/O. This allows peripheral Bytes transferred to or from odd memory (address bit 0 is 1) locations are always transmitted on lines devices or CPU support devices to attach to only ‘ADo - AD? (bit 0 on ADs). Bytes transferred to or —_—&ight of the 16 ADo - ADis lines. The Read/Write from even memory locations (address bit 0 is 0) are ine (RAV) fncates We apecton otthe gata trans. always transmitted on lines ADg-ADis (bit 0 on ‘ft: Peripheral-to-CPU (Read : = High) or ADs). Thus, the memory attached to a 28000 will CPU-to-peripheral (Write : RW = Low). look like that shown in Figure 2-7. For byte reads EPU Transfer Transactions. These transactions (BAW High, RAW High) the CPU uses only the byte move data between the CPU and an Extended whose address it output. For byte writes (B/W High, Processing Unit (EPU), thus allowing the CPU to R/W Low), the memory should store only the byte transfer data to or from an EPU or to read or write whose address was output. During byte memory —_an EPU’s Status Registers. They are generated writes, the CPU places the same byte on both —_during the execution of the EPA instruction. . 27

Z8001,2 CPU Figure 2-7. Memory Organization us omen CEES | [7 °o Or Po | es | a — | rasta vercn i wom | THON AND ere i | erie } jh ' be oe cworntoness) | || co toess ee ie es | efi —d>—— a i NA ‘ynooi2s 28. -THOMSON

Z8001,2 CPU Transactions (Continued) EPU transfer transactions have the same form as The data transferred is 16-bit words (B/W = Low), memory transactions (Figure 2-6) and thus are except for transfers between the Flags byte of the three clock cycles long, unless extended by WAIT. FCW and an EPU. In this case, a byte of data is No address is generated, and there is only one _ transferred on ADo- AD7 (B/W = High). The status code that can be used on the STo - STslines Read/Write line (R/W) indicates the direction of the (1110). In a multiple EPU system, the EPU which data transfer. The N/S line indicates either system is to participate in a transaction is selected implicit- _ mode (Low) or normal mode (High). ly, rather than by an address. Figure 2-8. Input/Output Transaction N 2 TWA 13 ast CHOLES Max Moses Arco wat ee ee @M, sto- sts) |X . Re a cr AD Teer aconecal = - ~ DS R/w » Kah curt? | artes Xai or ouTPUT at | \\ rf | ouTPUT R001 252 5 29

2Z8001,2 CPU $$$ Transactions (Continued) Interrupt/Trap Acknowledge Transactions. mary for more information on the operation of the These transactions acknowledge an interrupt or Priority daisy-chain.} trap and read a 16-bit identifier word from the The status lines j that device that generated the interrupt or trap. The being acinomodaed fhe postales oe oon transactions are generated automatically by the Trap(0100),Non-Maskable Interrupt (0101), Non-Vec: hardware when an interrupt or segment trap is torag Interrupt (0110), and Vectored Interrupt (0111) detected. No address is generated. The N/S line indicates sys- These transactions are eight clock cycles long ata _—_ tem mode (Low), the R/W line indicates READ (High), minimum (as_shown in Figure 2-9), having five _and the BIW line indicates Word (Low). automatic WATT cycles. The WAIT cycles are used the only item of data transferred is the identifier to give the interrupt priority daisy chain (or other org. which is always 16 bits long and is captured priority resolution device) time to settle before the FS the ADg - ADielines on the faling clock edge identiier word is tread. (Consult the Z-BUS Sum- ie ative OS is raised high Figure 2-9. Interrupt and Segment Trap Request an Acknowledge Transition wwsmucnon ast waging crcit OF AL eros ACKNOMEDSE CYCLE as (aoonre0) yroune at rams po ee cxocx | =m TT — WAT OGAES ADSED | / ard | ‘Ser bal | wa 7 | ow 1\\ Es ons

30 THOM:

Z8001,2 CPU As shown in Figure 2-9, there are twoplaceswhere and can come immediately after the final clock WAIT is sampied and thus a WAIT cycle may be —_cyde of any other transaction. The memory refresh inserted. The first serves to delay the falling edge _counter's 9-bit ROW field is output on ADO - ADB of DS to allow the daisy chain alongertimetosettie, during the normal time for addresses. This trans- and the second serves to delay the point at which action can be used to generate relreshes for dy- data is read. namic RAMs. The value of NS, RW, and BW is Internal Operations and Refresh Transactions. _‘ne same as for the immediately preceeding trans- There are two kinds of bus transactions made by action. the CPU that do not transfer data : internal oper- WAIT is not sampled during internal operation or ations and memory refresh. Both transactions look refresh cycles. like a memory transaction, except that Data Strobe remains High and no data is transferred. CPU and Extended Processing Unit Interaction For internal operation transaction (shown in Figure 78000 CPU and one or more Extended Process- 2-10), the Address and Segment Numberines Con- ing Units (EPUs) work together like a single CPU tain arbitrary data when the Address Strobe goes component, with the CPU providing address, High. The RAW line indicates Read (High) ; the BW Status and timing signals and the EPU supplying line is undefined, and N/S is the same as for the ang capturing data. The EPU monitors the status immediately preceding transaction. This transaction ang timing signals output by the CPU so that it will is intiated to maintain a minimum transaction rate Know when to participate ina memory or EPU while the CPU is doing a long internal operation. transfer transaction. When the EPUis to participate ‘A memory retresh transaction (shown in Figure 2-11) __ ina memory transaction, the CPU puts its AD lines is generated by the ZB000 CPU's refresh mechanism —_in 3-state while DS is Low, so that the EPU may use them. Figure 2-10. Internal Operation Timing Figure 2-11. Memory Refresh Timing : — pe ae ety oe . = | “ [e777 e/a nomen |_| oe ee eee ee vR001255 “e vrooi2s¢ y 31

Z8001,2 CPU In orderto know which transaction itis toparticipate © — Whether or not a memory access will be made in, the EPU must track the following sequence of and how many words of instruction will be events : fetched before the data is transferred. — When the CPU fetches the first word of an — The number of words of data to be transferred instruction (ST3-STo = 1101), the EPU must for memory or EPU-CPU transfers. also capture the instruction returned by mem- —__ The operation to be performed on its data ory. If the instruction is an extended instruction, itwill have an ID field which indicates (along with the second instruction) whether or not the EPU —- Requests is to execute the instruction. There are three kinds of request signals that the = If the instruction is to be executed by the EPU, __2-BUS supports and the 28000 CPU participates the next non-refresh transaction by the CPUwill__in. These are fetch the second word of the instruction (ST3 - — Interrupt/Trap requests, which another device STo = 1100). The EPU must also capture this initiates and the CPU accepts and acknow- word. ledges. = If the instruction involves a read or write to - Bus requests, which another potential bus mas- memory, there will be zero or more program ter initiates and the CPU accepts and acknow- fetches by the CPU (STs - STo = 1100) to obtain ledges. the address portion of the extended instruction. __ Resource requests, which any device capable The next one to 16 non-refresh transactions by of implementing the request protocol (usually the CPU will transfer data between memory and the CPU) can request. No component has con- the EPU (ST3-STo = 1000, 1001, 1010, or trol of the resource by defaut. 1011). The EPU must supply the data (Write, The CPU supporis an additional request beyond R/W Low) or capture the data (Read, R/W High) those of the 7-BUS. for each transaction, just as if it were part of the - CPU. In both cases, the CPU will 3-state its AD — Stop request, which another device initiates and lines while data is being transferred (DS Low). the CPU accepts. EPU memory tranfers are always word-oriented When a request is made, it is answered according (B/W Low). to its type : for interrupt/trap requests, an inter- — Ifthe instruction involves a transfer between the ruptitrap acknowledge transaction is initiated for CPU and EPU, the next one to 16 non-refresh bus request, an acknowledge signal is sent for Stop transactions by the CPU will transfer data be- _fequest, the CPU enters the Stop/Refresh state. In tween the EPU and GPU (STs - STo = 1110) all cases except Stop, the Z-BUS provides for a daisy-chain priority mechanism to arbitrate be- Note that in order to folow this sequence, a vie tween simultaneous requests. will have to monitor the ine to verify that the transaction it is monitoring on the bus was _Interrupt/Trap Request. The 28000 CPU sup- generated by the CPU. It should also be noted that —_—POTtS three interrupts and one external trap (seg- ina multiple EPU system, there is no indication on ‘Ment trap) as shown in Figure 2-9. The Interrupt the bus as to which EPU is cooperating with the Request line (INT) of a device that is capable of CPU at any given time. This must be determined generating an interrupt may be tied to _any of the by the EPUs from the extended instructions they _ three 28000 interrupt pins (NMI, NVI, Vi). Several capture. devices can be connected to one pin, the devices arranged in a priority daisy chain (see the Z-BUS Afinal aspect of CPU-EPU interaction is the use of Summary). The segment trap pin (SEGT) is acti- the CPU's STOP pin. When an EPU begins to _ vated by the memory management hardware. The execute an extended instruction, the CPU can CPU uses the same protocol for handling requests continue fetching and executing instructions. if the on any of these pins. Here is the sequence of CPU fetches another extended instruction before _ events that is followed : the first one has completed execution, the EPU . nui must activate the CPU's STOP pinto stop the CPU ~ ALY Tighvlo-tow Hanson on tne normal until the instruction completes execution. Aidilatch s set Atthe beginning f the last clock Besides determining whether or not to participate cycle in the last machine cycle of any instruction, in the exection of an EPA instruction, the EPU must the Vi, NVI, and SEGT inputs are sampled along determine from the first two instruction words with the state of the internal NMI latch.

32 THOM:

Z8001,2 CPU Requests (Continued) — Ifaninterruptortrapis detected, the subsequent _is initiated by pulling BUSREQ Low. Several bus initial instruction fetch cycle is exercised, but requesters may be wired to the BUSREQ pin ; aborted. priorities are resolved externally to the CPU, — The next machine cycles the interrupt acknow- _USUally by a priority daisy chain. ledge transaction that results in an identifier The asynchronous BUSREQ signal generates an word from the highest-priority interrupting de- internal BUSREQ, which is synchronous. If the vice being read off the AD lines. external BUSREQ is Low at the beginning of any — This word, along with the program status infor. ™achine cycle, the internal BUSREQ will cause the mation, is stored on the system stack, and new US acknowledge line (BUSACK) to be asserted status information is loaded after the current machine cycle is completed. The " CPU then enters Bus-Disconnect state and gives For more information about the system-level as- yp control of the bus. All CPU Output pins, except pects of the interrupt structure, consult the Z-BUS — BUSREQ and MO, are 3-stated. Summary. ; The CPU regains control of the bus two clock cycles Bus Request. To generate transactions on the —_ after BUSREQ rises. Any device desiring control of bus, a potential bus master (such as the DMA the bus must wait at least two cycles after BUSREQ Controller) must gain control of the bus by making has risen before pulling it down again. bus request (shown in Figure 2-12). Abus request Figure 2-12. Bus Request/Acknowledge Timing any M CYCLE —e}=—— BUS AVALABLE ——= __ ny» wl x wow ok tk ~ m( oa nea ain cod | | BUSACK aa | | : Ty a SREO.OS. __SlorSts oa on es a B/WR MIN/S Caceres uty vR001256 33,

2Z8001,2 CPU Resource Request. The CPUgeneratesresource cycle. If STOP is found Low, the CPU enters requests by executing the Multi-Micro Request —_Stop/Refresh state anda stream of memory refresh (MREQ) instruction. The CPU tests the availability cycles is inserted after the third clock cycle in the of the shared resource by examining Mi. If MI is instruction fetch. The ROW field in the Refresh High, the resource is available, otherwise the CPU _ Counter is incremented by two after every refresh must try again later. The MO pin is used to make _cycle. the resource request. MO is pulled Low, then, after When STOP is found High again, the next refresh a delay for arbitration of priority, Mlistested again. cycle ig completed, then the original instruction If itis Low, the CPU has control of the resource : if Continues. it is still High, the request was not granted. In the ie set (indicati case of failure, MO must be deactivated. But it |" the EPAbbit in the FOW's set (indicating an EPL successful, MO must be kept active until the CPU _iSin the system), the STOP line is also sampled on is ready to release the resource whereupon MO is _the falling clock edge immediately preceding the deactivated by an MRES instruction. second word of an instruction fetch -if the first word indicates an extended instuction. Thus, the STOP. The Z-BUS Summary describes an arbitration _|ine may be used by an EPU to deactivate the CPU Scheme that is implemented with a resource re- —_ whenever the CPU fetches an extended instruction quest daisy chain. before the EPU has finished processing an earlier Stop Request. As shown in Figure 2-13, the STOP one. The STOP line may also be used to externally pin is normally sampled on the falling clock edge _ single-step the CPU immediately preceding an initial instruction fetch Figure 2-13. Stop Timing cock ¢ S10 sawPceo wo Ce HE>-- wstaucnow BON SN ON a we Ne a ome Nf >= pm wow wroo1as7 34: -THOMSON

Z8001,2 CPU Reset A hardware reset puts the Z8000 in a known state —_ Within five clock cycles of the RESET line becom- and initializes selected control registers of the CPU _ing low (Figure 2-14), ADo - ADs are 3-stated ; AS, to system specifiable values (as Areset will begin DS, MREQ, BUSACK, Mo, and STo- ST3 are at the end of any clock cycle, if the RESET line is forced High ; SNo - SNe are forced Low. The R/W, Low. BMW and NV lines are undefined. Reset must be system reset overrides all other operations of the _‘"e!d Low at least five clock cycles. chip, including interrupts, traps, bus requests and After RESET has returned High for three clock stop requests. Areset should be used to initialize a__ cycles, consecutive memory-read transactions are system as part of the power-up sequence. executed in the system mode to initialize the Pro- gram Status Registers. Figure 2-14. Reset Timing x, a "5 oox TLE LILI ae mm \\ rr A Sess 7 vo |X oe [Xs we IN, a oy I\\ - || vroor2se . 38.

Z8001,2 CPU Hardware Interface Figure 3-3. 28000 Pin Functions Figure 3-3 shows the Z8000 pins grouped accord- ing to function. The 28001 is packaged in a 48-pin DIP and the Z8002 is packaged in a 40-pin DIP. The eight additional pins on the Z8001 are the seven segment-number lines and the segment trap. Ex- cept for those eight, all pins on the two CPU ver- a sions are identical. os [218 ees The Z8000 is a Z-BUS CPU ; thus, activity on the Chases we pins is governed by the Z-BUS protocols (see The [ Tafa 20 ES Z-BUS Summary). These protocols specify two preswere PEE | sonar types of activities = transactions, which cover all sans | ss 17h [omas data movement (such as memory references or //O. | = sr Zegon 225 operations), and requests, which cover interrupts a eS | and requests for bus or resource control. The fol- ome (aR 37 lowing is a brief overview of the Z8000 pin func- : mee tions ; complete descriptions are found in Chapter come (Tea oo PIN CONFIGURATION. pase EL Address/Data Lines. These 16 lines alternately tS a0 fea wees carry addresses and data. The addresses may be werctero ¢—fo ieee those of memory locations or /O ports. The bus conten (8 | an timing signal lines described below indicate what pop kind of information the Address/Data lines are car- ve oo cK FRY a rying. Segment Number (28001 only). These seven lines encode the addresses of up to 128 relocatable memory segments. The segment signals become valid before the address offset signals, thus sup- Porting address relocation by the memory manag- ment system, Bus Timing. These three lines include Address ‘Strobe (AS), Data Strobe (DS) and Memory Re- iuest (MREQ). They are used to signal the begin- ning ofa ue ranean and to determine when Table 9-1, Status Line Codes the multiplexed Address/Data Bus holds addresses. [ $7, stp Definition i or data, The Memory Request signal can be used + ee to time control signals to a memory system. 0000 | Internal operation . | 9001 Memory refresh | Status. These lines function to indicate the kind of 0010 | lO reference transaction on the bus (STo - STs), whether it is a 0011 | Special /O reterence read or write (R/W, where High is Read and Low is 0100 | Segment trap acknowledge ' Write), whether it is on byte or word data (B/W, | 0101 Non-maskabie interrupt acknowledge | High = byte, Low = word), and whether the CPU is 0110 Non-vectored interrupt acknowledge ‘operating in normal mode or system mode (N/S, Soo pecored interrupt scinowledge High = normal, Low = system). The STo - STs lines 1001 | Stack memory renaost i also encode additional characteristics of the bus | 9:0 | Data memory request (EPU) | transactions, as Table 3-1 shows. The availability 4011 | Stack memory request (EPU) of status information defining the type of bus trans- 1100 Instruction space access action in advance of data transmission allows bidi- ! 1101 Instruction fetch, first word rectional drivers and other external hardware 1110 | EPAtransfer elements to be enabled before data is transferred. 111 | Reserved _ 7 38 1

Hardware Interface (Continued) CPU Control. These inputs allow externaldevices Segment Trap Request (28001 only). This input to delay the operation of the CPU. The WAIT line, to the CPU is used by an external memory-man- when active (Low), causes the CPU to idle in the agement system to indicate that an illegal memory middle of a bus transaction, taking extra clock access has been attempted. cycles until the WAIT line goes inactive ; itis typi ulti-Micro Control cally used by memory or V/O peripherals which cro Contra’ operate more slowly than the CPU. The Stop The Multi-Micro In (Ml) and Multi-Micro Out (MO) orOP, P) line halts internal CPU operation when the __ lines are used in conjunction with instructions such first word of an instruction (or the second word of a8 MSET and MREQ to coordinate multiple-CPU an EPA instruction) has been retrieved. This signal systems. They allow exclusive use by one CPU of is useful for single-step instruction executionduring _@ Shared resource in a multiple-CPU system. debugging operations and for enabling Extended System Inputs. The four inputs shown at the Processing Units to halt the CPU temporarily. bottom of Figure 3-3 include +5V power, ground, a Bus Control. These lines provide the means for _ single-phase clock signal and a CPU reset. The other devices, such as direct memory access __ reset function is described in Chapter EXCEP- (DMA) controllers, to gain exclusive use of the TIONS. system bus, i.e., the signal lines that are common to several devices ina system. The externaldevice Timing requesting control of the bus inputs a bus request . (BUSHEG) IEG) ; the CPU responds with a bus acknow- Figure a4 shows the three basic timing periods of ledge (BUSACK) after three-starting, or electrically the 28000: a clon cycle, a bus transaction, and a neutralizing, the Address/Data Bus, Bus Timing Machine cycle. A clock cycle (sometimes called a lines, Status lines, and Control lines. The Z-BUS state) is one cycle of the CPU clock, starting with allows a daisy chain to be used to enforce a priority "isingedge. Abus transaction covers a single data among several external devices. movement on the CPU bus and will last for three or , ° more clock cycles, starting with a faing edge of AS Interrupts. Three Intomupt inputs are provided: and ending with a rising edge of DS. A machine non-maskable interrupts (NMI), vectored interrupts cycle covers one basic CPU operation and always (VI) and non-vectored interrupts (NVI). These per- starts with a bus transaction. A machine cycle can mit external devices to suspend the CPU's execu- extend beyond the end of a transaction by an tion of its current program and begin execution an unlimited number of clock cycles. interrupt service routine. Figure 3-4. Basic Timing Periods WACHINE CYCLE ous TRANSACTION Tl cru cock BO \\S... \\SO aS \\/S \\S 001229 s 39 hy S6S-Tomsom

Z8001,2 CPU Address Spaces The Z8000 supports two main address spaces _ (such as the Z8010 MMU) are generally required Corresponding to the two different kinds of locations _to take full advantage of them. Chapter ADDRESS that can be addressed : SPACES contains an extensive discussion of seg- — Memory Address Space. This consists of the entation and the 28001. addresses of all locations in the main memory VO Address Space. 1/O addresses are represented of the computer system. as 16-bit words for both the 28001 and 28002. — WO Address Space. This consists of the ad- There are two I/O address spaces, Standard /O dresses of all /O ports through which peripheral and Special /O, which are both separate from the devices are accessed, memory address space. Each V/O space is ac- For more information on address spaces, consult HrewrehibleciRebeirel bird bined the cou Chapter ADDRESS SPACES. operating in system mode. Memory Address Space. eso Ba8E8S Standard VO instructions transfer data between the Memory address space, Data Memory adress CPU and peripherals and Special /O instructions : transfer data to or from external CPU support cir- Bbace, and Slack Memory address space, each for its ich as the 28010 MMU. Access to Standard both normal and system modes. or Special /O space is distinguished by the status The particular space addressed is determined by ines (STo - STs). the external circuitry from the code appearing at the CPU's output status pins (STo - STs) and the state . i of the Normal/System signal (N/S pin). Datamem- General-purpose Registers ory reference, stack memory roference, and pro- iiinapeenaid bts wide. Boy ganar pornee gram memory reference each correspond to a q - i different status code at the STo - STs outputs, allow- _‘fegister_can be used for any instruction operand ing three address spaces tobe distinguished foreach (except for minor exceptions described at the be- of two operating modes, giving six address space in _ ginning of Chapter ADDRESSING MODES). all. Each of the six address spaces has a range aS Figure 3-5 shows these general-purpose registers, great as the addressing ability of the processor. For They allow data formats ranging from bytes to quad. the nonsegmented 28002, each address space can —_ryple words. The word registers are specifiedin assem- have up to 64K bytes, giving a potential total system —_ply-language statements as RO through R15. Sixteen Capacity of 384K bytes of directly addressable mem- byte registers, RHO - RL7, which may be used as ory. The segmented 28001, on the other hand, pro-_acoumulators, overlap the first eight word registers, vides up to 48M bytes of directly addressable Register grouping for larger operands includes eight memory due to the 23-bit segmented addresses. double-word (32-bit) registers, RRO - R14, and four Segmentation is a means of partitioning memory —_ quad-word registers, ROO - RQ12, which are used by into variable-size segments so that a variety of few instructions such as Mutiply, Divide, and Extend useful functions may be implemented including : Sign. — Protection mechanisms that preventauserfrom AS Figure 3-5 illustrates, the CPU has two hard- referencing data belonging to others, attempting ware stack pointers, one dedicated to each of the to modify read-only data or over-flowing a stack. two basic operating modes, system and normal. Virtual , The segmented Z8001 uses a two-word stack ~ Wirtual memory, which permits a user to write pointer for each mode (R147A15" or R14/R15), functioning programs under the assumption that Whereas the nonsegmented Z8002 uses only one the system contains more memory than is ¢- Word for each mode (15 or R15) tually available. fe — Dynamic relocating which allows the placement infonseton when ar tert a a caving satus of blocks of data in physical memory inde- Sse oting call in system mode. The rormal slack Pendently of user addresses, allowing better Potter ig Used for subroutine callin user programs, In management of the memory resources and Tormamode operation only the notmal stack potter sharing of data and programs is accessible. Insystem mode, the normal stackpointer The signals provided on the segmented 28001 _can be directly accessed as a special control register. CPU assist in implementing these features, al- The normal mode stack pointer can be accessed as a ng though additional software and external circuitry special control register. 40. .

oo 28001,2 CP Figure 3-5a. 28001 General-Purpose Registers Figure 3-5b. Z8002 General-Purpose Registers (Register Address Space) (Register Address Space) 22001 220002 | . J |e | ee a 6) Se s14! [Syste STAC PONTER TSEGNOT prov | so? Special-purpose Registers In addition to the general-purpose registers, there Carry (C), which generally indicates a carry out are special-purpose registers. These include the of the high-order bit position of a register being Program Status registers, the Program Status Area used as an accumulator. Pointer, and the Refresh Counter ; they are illus- teh | trated for both CPU versions in Figure 3-6. Each ~ Zero (Z), whichis generally used to indicate that register can be manipulated by software executing the result of an operation is zero. in system mode, and some are modified automat- — Sign (S), which is generally used to indicate that ically by certain operations. the result of an operation is a negative number. Programs Status Registers. These registers in- —Parity/Overflow (P/V), which is generally used clude the Flag and Control Word (FCW) and the to indicate either even parity (after logical oper- Program Counter (PC). They are used to keep track ations on byte operands) or overflow (after arith- of the state of an executing program. metic operations) In the nonsegmented Z8002, the Program Status — Decimal-Adjust (D), which is used in BCD registers consist of two words : one each for the arithmetic to indicate the type of instruction that FCW and the PC. In the segmented 28001, there was executed (addition or subtraction). are four words : one reserved word, one word for Half Car i = irry (1H), which is used to convert the binary the FCW and two words for the segmented PC. result of a previous decimal addition or subtraction The low-order byte of the Flag and Control Word into the correct decimal (BCD) result. (FCW) contains the six status flags, from which the condition codes used for control of program looping and branching are derived. The six flags are : yz S5S:THOMSON ‘

Z8001,2CPU The 28001,2 CPU Programming Manual gives © - Segmentation Mode (SEG). This bit is im- gi more information about these flages. plemented only in the 28001 ; it is always i leared in the nonsegmented Z8002. When set The control bits, which occupy the high-order byte a e J of the FCW, are used to enable various interrupts to one, the CPU 15 operating in foamented orto contro! CPU operating modes. The control bits mode, and when cl eared to Zerg. tne CPU is are. operating in nonsegmented mode (see page ~ Non-Vectored Interrupt Enable (NVIE), Vec- tored Interrupt Enable (IE). Thee bis deter- gan Sates wee Come PSAP). Ale mi whett rt wil ept Monaeclored or Cech interrupts (see, ‘page Program status values (FCW and PCs) in main 48), memory called the Program Status Area. New Pro- nD 7 gram Status register values are fetched from this ~ System/Normal Mode (SIN). When this bit Is area when an interrupt or trap occurs. As shown in set to one, the CPU is operating Cpe Figure 3-6, the PSAP comprises either one word mode ; when cleared to roves e PU cutout (RORSegmented 28002) or two words (segmented normal mode {see page 43). The CPU output 75993)": for either configuration, the kawe. byte of Beis ine (NS pin) is the complement of this the pointer must be zero. Refer to Chapter EXCE bit TIONS for more details about the Program Status ~ Extended Processor Architecture (EPA) Area and its layout. Mode. When this bitit set to one, it indicates that 7 Refresh Counter. The CPU contains a programm- ihe system nameins Extended Processing able counter that can be used to refresh dynamic Unto ie are oektegeG instructions en- Temory automaticaly. The elfesh courier ouiees executed (see page 48), Wren the bie ean consists of a9-bit row counter, a bit rate counter executed (see page 45). When this bitis clear and an enable bit (Figure 3-6). Refer to Chapter 0 aro. extended instructions are trapped for BEE RESH for details of tho setvocn mechamane software emulation. Figure 3-6. CPU Special Registers Jaca? (RP oo, Tees papA HTS] Fess! EEAPPRTS, STTTP TTS) Yeni hea

28002 PROGRAM STATUS REGISTERS

22007 PROGHAW STATUS REOITERS

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28002 PHOORAW STATIS ARCA =ONTES

2800) PROGRAM STATUS ARCA PONTER 28001 REFRESH COUNTER wROG?232 78002 REFRESH COUNTER vR00"233 42 =]

Z8001,2 CPU Instruction Execution In the normal course of events, the 28000 CPU will — Load and Exchange for register-to-register spend most of its time retrieving instructions from and register-to-memory operations, including memory and executing, them. This process is stack management, called the running state of the CPU. The CPU also __ arithmetic for arithmetic operations, including has two other states that it occasionally enters. multiply and divide, on data in either registers or — Stop/Refresh State. This is really one state, memory. Compare, increment, and decrement although it may be entered in two different functions are included. ways : either automatically fora periodicmem- _ . . In this state, program execution is temporarily . suspended and the CPU makes use of the ~ Program Control for program branching (con- Refresh Counter to generate refreshes. For Gitional or unconditional), calls, and returns. more information, consult Chapter REFRESH. — Bit Manipulation for setting, resetting and test- — Bus-Disconnect State. This is the state the ing individual bits of bytes or words in registers CPU enters when the DMA, or some other bus or memory. requester, takes over the bus. Program execu — Rotate and Shift for bytes, words, or, for shifts tion is suspended and the CPU disconnects only, long words within registers itself from the bus. — Block Transfer and String Manipulation for While the CPU is the running state, it can either be automatic memory-to-memory transfers of data handling interrupts or executing instructions. If it is blocks or strings, including compare and trans- executing instructions, the Z8000 can be in the late functions. system or normal execution mode. In system — — Input/Output for transfers of data between /O mode, privileged instruction (such as those which ports and memory or registers. perform I/O) canbe executed ;innormalmodethey —__ i cannot. This dichotomy allows the creation of oper- Processing tor erations involving Extended ating system software, which controls CPU resour- " ces and is protected from application program - CPU Control for accessing special registers, action controlling the CPU operating state, synchroniz~ In addition, the CPU will be in either segmented or ened “mode selection, and momory nonsegmented mode. In segmented mode, which refresh. is available only on the 28001, the program uses 23-bit segmented addresses for memory ac- The 28001,2 CPU Programming Manual contains cesses ; in nonsegmented mode, which is avail- __ full details of the instruction set. able on both CPUs, the program uses 16-bit Instruction Formats. Formats of the instructions nonsegmented addresses for memory accesses. are shown in Figure 3-7. The two most significant While executing instructions, the mode of the CPU _ its in the instruction word determine whether the is controlied by bits in the FCW (see Figure 5-2). cOmpact instruction format (A) or the general in- While handling interrupts, the CPU is always in __ Struction format (B) is used. Compact formats en- system mode and, for the Z8001, in segmented __00de the four most frequently used instructions into mode single words, thereby saving on instruction-mem- ory usage and increasing execution speed. As jong 7 as the two most significant bits are not logic ones, Instructions the general format applies. In the general format, The 28000 instruction set contains over 400 differ-__the two most significant bits in conjunction with the ent instructions which are formed by combining the _source-register field are sufficient for specifying 110 distinct instruction types (opcodes) with the —_any of the five main addressing modes. Source and various data types and addressing modes. The destination fields are four bits wide for addressing complete set is divided into the following groups: _the 16 general-purpose registers . 43 i ko SSTHomson

Z8001,2 CPU Figure 3-7. Instruction Formats oe ya Nor LL Toscobe" Ta] Soveck pcb og DECREMENT AND UWP ON NON-ZERO eee owe GOOEY wl" ort 7) Data Types The Z8000 supports manipulation of eight data — Register Mode. The data element is located in types. Five of these have fixed lengths ; the other one of the 16 general-purpose registers. three have lengths that can vary dynamically. Each _ ' data type is supported by a number of instructions immediate Mode. The data element is located which operate upon it directly. These data types are : — Bit — Indirect Register Mode. The data element can be found in the location whose address is in a — Signed and unsigned byte, word, long word, or register. Quadruple word binary integer ~ Direct Address Mode. The data element can — Byte or word-length logical value be found in the location whose address is in the - Word (nonsegmented) or long word (seg- instruction. mented) address — Index Mode. The data element can be found in — Unsigned byte decimal integer the location whose address is the sum of the _ contents of a 16-bit index value in a register and Bynamicvengin string of wore data — Relative Address Mode. The data element can ~ Dynamic-length stack of word data be found in the location whose address is the Bits can be manipulated in registers or memory sum of the contents of the program counter and Binary and decimal integers and logical values can a 16-bit displacement in the instruction. be manipulated in registers only, although oper- __ Bage Address Mode. The data element can be ands can be fetched directly from memory. Ad- found in the location whose address is the sum dresses are manipulated only in registers, and of a base address in a register and a 16-bit strings and stacks are manipulated only in memory. displacement in the instruction. — Base Index Mode. The data element can be Addressing Modes found in the location whose address is the sum The information included in 28000 instructions con- of a base address in one register and an index sists of the function to be performed, the type and value in another register. size of data elements to be manipulated, and the 7 locatonof he data elements Locations are esi. haber ADDRESSING MODES defines anus nated using one of the following eight addressing a ‘9 ‘9 modes 44 “THOMSON St Ome a

2Z8001,2 CPU Extended Processing Architecture The extended Processing Architecture (EPA) pro- pansion of design capability - a powerful micropro- vides an extremely fiexible and modular approach —_cessor architecture capable of connecting single- to expanding both the hardware and software ca-_ chip EPUs that permits very effective parallel abilities of the Z8000 CPU. Features of the EPA processing and makes for a smoothly integrated include : instruction stream from the Z8000 programmer's — Specialized instructions for external processors _Pointof view. Atypical adsition to the current 28000 or software traps may be added to CPU instruc- _'Nstruction set is Floating Points Instructions. tion set. The Extended Processing Units connect directly to — Increases throughput of the system by using up _the Z-BUS and continuously monitor the CPU in- to four specialized external processors in paral-__ struction stream. lel with the CPU. When an extended instruction is detected, the ap- — Permits modular design of Z8000-based sys- _propriate EPU responds, obtaining or placing data tems. or status information on the Z-BUS using the ~ Provides easy management of multiple micro- 76000-generated ontrol signals and performing processor configurations via "single instruction _itS function as directed. stream” communication. The Z8000 CPU is responsible for instructing the — Simple interconnection between extended pro. EPU and delivering operands and data to it. The cessing units and Z8000 CPU requires no addi. EPU recognizes instructions intended for it and tional extemal supporting logic. executes them, using data supplied with the in- f h struction and/or data within its internal registers. ~ Supports debugging of suspect hardware There are four classes or EPU instructions : against proven software. , , . — Data transfers between main memory and EPU. Specific benefits include : registers ~ EPUs can be added as the system grows and —__ Data transfers between CPU registers and EPU as EPUs with specialized functions are de- registers. veloped. egisters. ; — Control of EPUs is accomplished via a “single ~ EPU internal operations. instruction stream” in the Z8000 CPU, eliminat- ~ Status transfers between the EPUs and the ing many significant system software and bus 28000 CPU Flag and Control Word register contention management obstacles that occur in (FCW). other multiprocessor (e.g., master-slave) organ-__ Foyr 28000 addressing modes may be utilized with ization schemes transfers between EPU registers and the CPU and The processing power of the Z8000canbeboosted | main memory: beyondits intrinsic capability by Extended Process- _ Register, ing Architecture. Simply stated, EPA allows the Indirect Regist Z8000 GPU to accomodate up to four Extended ~ [direct Register, Processing Units (EPUs), which perform spe- | — Direct Address, cialized functions in parallel with the CPU's main _ indexed instruction execution stream. In addition to the harch ! ted iti in addition to the hardware-implemented capabilities The use of extended processors to boost the Main —_of the Extended Processing Architecture, there is an CPU's performance capability has been proven extended instruction trap mechanism to permit soft- with large mainframe computers and minicompu- ware simulation of EPU functions. Acontrol bit in the ters, In these systems, specialized functions such —_g099 FOW register indicates whether actual EPUs as array processing, special ipuvoutput process- are present or not. If nol, when an extended instruc- ing, and data communications processing are typi- tion is detected, the 28000 traps on the instruction, cally assigned to extended processor hardware. 9 that a software “trap handler" can emulate the These extended processors are complex compu: desired EPU function - a very useful development ters in their own right, tool. The EPA software trap routine supports the The Extended Processing Architecture combines —_ debugging of suspect hardware against proven sott- the best concepts of these proven performance ware. This feature will increase in significance as boosters with the latest in high-density MOS inte- designers become familiar with the EPA capability of grated-circuit design. The result is an elegant ex- the Z8000 CPU . 45 yy SSs-THOMSON

2Z8001,2 CPU Extended Processing Architecture (Continued) Exceptions This software trap mechanism facilitates the design Three events can alter the normal execution of a of systems for later addition of EPUs : initially, the 28000 program : hardware interrupts that occur extended function is executed as a trap subrou- _whena peripheral device needs service, synchron- tine ; when the EPU is finally attached, the trap —_ous software traps that occur when an error condi- subroutine is eliminated and the EPA control bit is tion arises, and system reset. Chapter 7 contains set. Application software is unaware of the change. —_a detailed description of exceptions and how they Extended Processing Architecture also offers pro- a” handled. interrupt requests and segmentation tection against extended instruction overlapping. trap requests are accepted after the completion of Each EPU connects to the 28000 CPU via the the instruction execution during which they were STOP line so that ifan EPU is requestedto perform Made. At the end of the instruction execution. a a second extended instruction function before it spurious instruction retrieve transaction is usually has completed the previous one, it can put the CPU performed before the interrupt or acknowledge se- into the Stop/Refresh state until execution of the quence begins, bul the Program Counter is not previous extended instruction is complete. affect y the spurious retrieval. EPA and CPU instruction execution are shown in Reset. Asystem reset overrides all other operating Figure 3-9. The CPU begins operation by fetching conditions. It puts the CPU in a known state and an instruction and determining whether it isa CPU _then causes a new program status to be retrieved or an EPU command. The EPU meanwhile moni. _ {fom a reserved area of memory to reinitialize the tors the Z-BUS for its own instructions. Ifthe CPU Flag and Control Word (FCW) and the Program encounters an EPU command, it checks to see Counter (PC). whether an EPU is present ; if not, the EPU may be simulated by an EPU instruction trap software rou- Traps. nes Sy synchronous events frat are tine ; if an EPU is present, the necessary data eee aoe toy eee ice edadth the same ndior ddr is placed th Z-BUS. If the EPU each time the instruction is executed with the same Fab ale sehr Laban balpalbe ine set of data and the same process or state. The four is tree when the instruction and data for it appear, Kinds of traps are : the extended instruction is executed. If the EPU is. : still processing a previous instruction, it activates © — Extended instruction attempted in non-EPA the CPU's STOP line to lock the CPU of the Z-BUS mode. The current instruction is an EPU instruc- until execution is complete. After the instruction is tion, but the system is not in EPA mode. This finished, the EPU deactivates the STOP line and trap allows system software to either simulate CPU transactions continue. instruction or abort the program. = 47 Oe SS THOMSON

Z8001,2 CPU — Privileged instruction attempted in normal — Non-vectored interrupts (NVI). These inter- mode, The current instruction is privileged (I/O rupts are maskable interrupts which are all for example), but the CPU is in normal mode. handled by the same interrupt procedure. ~ System Call (SC) instruction. This instruction Trap and Interrupt Service Procedures. Inter- provides a controlled access from normal-mode __rupts and traps are handled similarly by the Z8000 to system-mode operation. CPU. The 8000 CPU automatically acknowledges : interrupts and processes traps in system mode. In ~ Segmentation violation (supplied by exter- tho ate ot the. segmented Pao ‘the CPU uses nal circuit). A segmentation violation, such 25 the segmented mode regardless of its mode at the using an ofset larger than the defined length of time of interrupt or tap the rogrars slates mien tre segments can be made to cause an external mation in effect just prior to the interrupt or trap is ier " 7 managemen system to san thine pushed onto the system stack. An additional word, cogent aboot C2" Coeur only with the Which servesas anidentifier for the nterruptor trap, egmente aiso is pushed onto the system stack, where it can Interrupts. Interrupts are asynchronous events be accessed by the interrupt or trap handler, The typically triggered by peripheral devices needing Program Status registers are loaded with new attention. The three kinds of interrupts associated status information obtained from the Program with the three interrupt lines of the GPU are : Status Area of memory. Then control is transferred Non iW to the service procedure, whose address is now Nopemaskabe interrupts (NM). Fee ee located in the Program Counter. For details of reserved for critical external events that require interrupt and trap handling, refer to Chapter EX- immediate attention. — Vectored interrupts (Vi). These interrupts cause eight bits of the vector output by the interrupting device to be used to select a par- ticular interrupt service procedure to which the program automatically branches. 48 1

2Z8001,2 CPU ADDRESS SPACES Introduction Programs and data may be located in the main _but rather in the organization and maximum size of memory of the computer system or in peripheral each space. Forthe Z8001, each of the six memory devices. In either case, the location of the informa- address spaces contains 8M byte addresses tion must be specified by an address of some sort grouped into 128 segments, for a total memory before that information can accessed. A set of addressing capability of 48M bytes. For the 28002, these addresses is called an address space. gach memory space is a homogeneous. collection of te addresses. In both the and the The 28000 Gupports two diferent ‘ypes 3 ad- 78002, the /O address spaces contain 64K port dresses an lus two categories of address addresses. When an address is used to access spaces data, the address spaces may be distinguished by — Memory addresses, which specify locations in the state of the status lines (STo - ST3) (which is main memory. determined by the way the address was generated) = VO addresses, which specify the ports through _and by the value of the Normal/System line (N/S) which peripheral devices are accessed. (which is determined by the state of the S/N bit in : the FCW). The CPU generates addresses during four types of operations : ~ Instruction Space (status = 1100 or 1101), nor. 4 mal mode (N/S = 1) or system mode (N/S = 0). = Instruction retrievals, decribed in Chapter CPU These spaces typically address memory that OPERATIONS. contains user programs (normal) or system pro- — Operand retrievals and stores, described in grams (system). Chapter ADDRESSING MODES. — Data Spaces (status = 1000 or 1010), normal = Exception processing, described in Chapter mode (N/S = 1) or system mode (NS = 0) EXCEPTIONS These spaces may be used to address the data — Refreshes, described in Chapter REFRESH. that user or sytem programs operate on. i - ick Spaces (status = 1001 or 1011), normal Timing information concerning addresses is de: Sta mode (N/S= 1) or system mode (N/S = 0). scribed in Chapter PIN CONFIGURATION. Taaee fpaces can be deed to axtroce te bye tem and normal program stacks. f Address S| Types of Address Spaces — Standard VO Space (status = 0010). This space Within the two general types of address spaces addresses all the /O ports that are used for (memory and I/O), it is possible to distinguish sev- 78000 peripherals. eral subcategories. Figure 4-1 shows the address ; " spaces that are available on both the 28001 and ~ Special VO Space (status = 0011). This space the 28002. addresses pots in CPU suppor chips (such as the lemor Janagement Unit). The difference between the Z8001 and the 28002 ry Manag "0 lies not in the number and type of address spaces, Figure 4-1. Address Spaces on the 28001 and Z8002 \\ MEMORY ADDRESS SPACES VO ADDRESS ‘SPACES | ‘SYSTEM MODE NORMAL MODE ‘SYSTEM MODE | INSTRUCTIONS INSTRUCTIONS STANDARD VO DATA DATA SPECIAL 1/0 STACK STACK i ~ 49 ep seston

Z8001,2 CPU VO Address Spaces All VO addresses are represented by 16-bit words. long words. Moreover, only certain instructions can Each of the ports addressed Is elther eight or 16 address bits. bits wide. Transter to or from 16-bit ports always A bit canbe addressed by specifying a byte or word involves word data and, for 8-bit ports, byte data address and the number of the bit within the byte The address of a 16-bit port may be even or odd —_(0-7) or word (0-18). Bits are numbered right-to-let, for both address spaces. In standard I/O space, from the least to the most significant. This is con. byte ports must have an odd address ; in special _sistent with the convention that bit n corresponds VO space, byte ports must have an even address. to position 2° in the conventional representation of binary numbers (see Figure 4-2) Memory Address Spaces The address of a data type longer than one byte (word or long word) is the same as the address of soument haat dese speed eee the byte with the lowest memory address within the 28001, canbe viewed as addressinga string of64k | W0rd or long word (Figure 4-2). Thisis the leftmost, bytes numbered consecutively in aacorcingerder_highest-order, or most significant byte of the word The 8-bit byte is the basic addressable element in 101g word. 28000 memory address spaces. However, there Word or long word addresses are always even- are three other addressable data elements : numbered. Low bytes of words are stored at odd- oe aie , numbered memory locations and high bytes at Bits, in either bytes or words. even-numbered locations. Byte addresses can be ~ 16-bit words. either even -or odd- numbered. — 32-bit words. Certain memory locations are reserved for system- Addressable Data Elements. The nature of the "Set handling, These are described fully in Chap- data element being addressed depends on the ter EXCEPTIONS. Except for these reserved instruction being executed. As Chapter EXCEP. locations, there are not memory addresses speci- TIONS explains in detail, different assembler mne- _fically designated for a particular purpose. monics are used for addressing bytes, words, and Figure 4-2. Addressable Data Elements OWT) Ss wa Bre ui NOG eT ESE S210 ADDRESS. 0 one vor s00Res5 » AO0RESS 9 +1 ADDRESS n + 2 ADDRESS » = 3 f ONS WOR J 001238 50 =)

Z8001,2 CPU Segmented and Nonsegmented Addresses. ment circuit can translate logical addresses into The two versions of the 28000 CPU generate two _ physical (actual) memory addresses and perform kinds of addresses with different lengths. The certain checks to insure data and programs are 28002 generates a 16-bit address specifying one _ properly accessed. of 64K bytes. The 28001 generates a 23-bit seg- mented address. A segmented address consists of he 28010 Memory Management Lint (MM) per 27-bit segment number which spectfiesone ot 128 f9"™s this function for the segmented addresses segments, and a 16-bit offset, which specifies one Produced by the 28001 CPU. A single MMU keeps ° descriptor for each of 64 segments. This descrip- of up to 64K bytes in the segment. Each segment 2 iptor for hyaloal i. i is anindependent collection of bytes : thus, instruc-_{2r tes where inphysical memory ine segment lies, tions and multiple byte data elements cannot cross ‘NOW long the segment is, and what kind of ac- segment boundaries. Some of the advantages of eee thas descriptors Fe eeecicalscartent address segmentation are outlined in this Chapter. Se Shes i ant physwaladdioosos Figure 4-3 shows the format of segmented and (as shown in Figure 4-4). At the same time, the nonsegmented addresses. Nonsegmented ad- — MMU checks for errors such as writing into a read- dresses are 16 bits long and thus can be stored in only segment ora system segment being accessed word registers (Rn) or in memory as word-lenght —_by a nonsystem program. MMUs are designed to addressable elements. The 23-bit segmented ad- be combined so that more than 64 segments can dresses are embedded in a 32-bit long word and be supported at once. The CPU does not require thus can be stored in a long word register (RRn) or ~~ MMUS ; the segment number can be used directly a long word memory element. There is a short as part of a physical address. encoding of segmented addresses that appears in instructions and requires only 16 bits. Some of the benefits of the memory management Itis important o realize that even though the Zg001_—_‘(@atures provided by the MMU are can operate in nonsegmented mode (Chapter CPU — Provision for flexible and efficient allocation of OPERATIONS), it always generates segmented physical memory resources during the execu- addresses. The segment number is supplied by the tion of programs. Program counter segment number. — Hardware stack overflow protection. = Support for multiple, independently executin dress Formats code and data. — Protection from unauthorized or unintentional access to data or programs. | — Detection of obviously incorrect use of memory NON-SEGMENTED MEMORY ADDRESS by an executing program. 28602" ONC) . 5 = Separation of users from system functions. Segmentation in the Z8001 helps support memory management in two ways SEGMENTED MEMORY ADDRESS (e008 OnLy) — By allowing part of an address (the segment iste a7 ° number) to be output by the CPU early in a memory cycle. This keeps access to the seg- ment descriptor in the MMU from adding to the 5 basic access time of the memory. | veoo2s7 | — By providing a standard, variable-sized unit of memory for the protection, sharing, and move- ment of data Segmentation and Memory Management. Ad- In addition, segmentation is the natural model for dresses manipulated by the programmer, used by the support of modular programs and data in a instructions, and output by the 28001 are called —_multi-programming environment. It efficiently sup- “logical addresses”. An external memory-manage- _ ports reentrant programs by providing data reloca- tion for different tasks using common code. 7 51 Be S8scTuoMsom

2Z8001,2 CPU Figure 4-4. Segmented Address Translation ees, | care oscn re _ tot fs , ot BS i oi i ee ee _ lat Tet \\ seouent 2 ' : ! | 15 © OFFSET 12 CE ad Si. L | ! a) LA | SEGMENT N 4 ‘SEGMENT 127, L--4 sepoosslt os EPelsS, 52 1

Z8001,2 CPU Instruction Execution While the CPU is in Running state and executing Cause the PC to be set to a value generated by the instructions, itis controlled by the Program Status __instruction. This causes a transfer of contro! with registers (Figure 5-2). The Program Counter gives. _@xecution continuing at the new address in PC. Te eae cre eemich instructions are forced: The 28000 CPU is able to overlap the fetching of 4 fe tags on rol Dranct ep ee CPU. ro! Bits one instruction with the operation of the previous oe tha nea e mode in which the operates instruction. This facility, called Instruction Look- 8nd the interrupts that are maeked Ahead. is illustrated in Figure 5-3. This shows the Instruction execution consists of the repeated ap- execution of a series of memory-to-register instruc- plication of two steps : tions, such as a value in memory being added to Fetch ds . ingle the value in a general-purpose register. Part of netruchon hom the masoeqcomerising 2 single each instruction is fetched while the previous in- Saco at he dhe a MeMOYY address struction execution is being completed. This mech- space at fhe address specified by the Program anism provides faster execution speed than the ‘ounter (PC). typical alternative of fetching each instruction only — Perform the operation specified by the instruc- _after the prior instruction has completed execution. in Pr fl 7 inthe Troan States etter andilags ater executing an instruction and in some cases : during an instruction’s execution, the CPU checks The operation performed by an instruction and the _to see if there are any traps or interrupts pending way the flags are updated depends on the particu. and not masked. If So, it temporarily suspends lar instruction being executed For most instruc- _ instruction execution and begins a standard excep- tions, the PC value is updated to pointto the word _tion-handling sequence. This sequence, causes immediately following the last word of the instruc- the value of the Program Status registers to be tion. The effect of this is that instructions are saved and a new value loaded. Instruction execu- fetched sequentally from memory. Exceptions to tion then continues with a new PC value and Flag this are Branch, Call, Interrupt Return and Load —_ and Control Word value. The effect is to switch the Program Status, and Return instructions, which —_ execution of the CPU from one program to another. Figure 5-2. Program Status Registers { Fy ere (aT 5 Aces pbATos) yes" ERPS ERT Tep) Vsti? Seer pxocsane 28002 PROGRAV STATUS REGISTERS 7800! PROGRAW STATUS REGSTERS 15 9 F ¢

28002 PROGRAN STATUS AREA POMTER

20001 PROGRAM STATUS AAEA PONTER

28001 XEFRESe COUNTER yro9!232 7a002 REFRES- COUNTER vaooi233

54 SGs-

Z8001,2 CPU Running-State Modes. While the CPU is execu- _ Because the 28001 supports segmented and non- ting instructions, its mode will be controlledby three segmented modes, it is possible to run programs contro! bits in the FCW : the System/Normal Mode written for the Z8002 on the Z8001 without alter- bit (S/N), the Segmentation Mode bit (SEG), and _ation. The reverse is not possible. The Z8001 CPU the EPA Mode bit. always generates segmented addresses, even when operating in nonsegmented mode. When a Segmented and Nonsegmenied Modes. The memory access is made in nonsegmented mode, Segmentation mode of te CPL Seamenied Of the offset of the segmented address is the 16-bit eee ee eee ae ir ano, address generated by the program. and the seg- addresses that are directly manipulated by pro” ment number is the value of the segment number grams. In segmented mode (SEG = 1), programs —_fieid of the Program Counter. manipulate 23-bit segmented addresses ; in non- segmented mode (SEG = 0), programs generate Normaland System Modes. The operation mode 16-bit nonsegmented addresses. There are also of the CPU (system mode or norma! mode) deter- the following differences in the address portions of | Mines which isntructions can be executed and instructions, which are due to the difference in which Stack Pointer register is used. address size In system mode (S/N = 1), all instructions can be — Indirect and Base Registers are 32-bit registers ©xecuted. While in normal mode, certain privileged in segmented mode and 16-bit registers in non-_instructions that alter sensitive parts of the machine segmented mode state (such as VO operations or changes to control registers) cannot be executed. = Addresses embedded ininstructions are always, dist J 16-bits in nonsegmented mode. They consist of second distinction between system and nor abit segment number and either and 8.bit or Tal Mode is access to the system or normal Stack . Pointer. As shown in Figure 5-4, there are two 16-bit offset in segmented mode. copies of the Stack Pointer registers (Register 15 ‘Segmented mode is available only on the 28001 —_in the Z8002 and Registers 14 and 15 in the CPU ; on the Z8002, the segment bit is always Z8001) : one for normal mode and one for system forced to zero, indicating nonsegmented mode, — mode. When in normal mode, a reference to the Figure 5-3. Instruction Look-Ahead fon] foal aoe SLPS ULL LLL woos Table 5-1. Registers Accessed by References to R14 and R15 | Register ‘System Mode Normal Mode Referenced by T Instruction Segmented Nonsegmented Segmented Nonsegmented Ria system R14. | Normal A14 Normal R14 Normal R14 RIS. System R15 System R15 | Normal R15. Normal R15. RRS System R14 Normal R14 Normal R14 Normal R14 | System R15 i ‘System R15 Ll Normal R15 | Normal R15 Note : 28002 always runs in nonsegmented mode. - yz SSS-THOMSON 88

Z8001,2 CPU Instruction Execution (Continued) Stack Pointer register by an instruction will access _to process the operation encoded in the extended the normal Stack Pointer. When in system mode, _ instruction. The CPU will fetch the extended in- an access to the Stack Pointer register will refer- struction and perform any address calculation re- ence the system Stack Pointer, unless the Z8001 quired by that instruction. If the instruction specifies is running in nonsegmented system mode, inwhich _the transfer of data, the CPU will generate the case a reference to R14 will access the normal __ timing signals for this transfer. The CPU will fetch mode R14, This is summarized in Table 5-1. and begin executing the next instruction in its in- f struction stream. The Extended Processing Unit is n normal mode, the system Stack Pointer is not eae eeUee ctvity, participate accessible ; in system mode the normal Stack 1 ingtrvetlon dea Sore iiiated b Pointeris accessed by using a specialLoadControl IN extended instruction data transfers initiated by Register instruction the CPU, and execute the extended instruction. men While the Extended Processing Unit is executing The CPU switches modes whenever the Program the instruction, the CPU can be fetching and execu- Status Control bits change. This can happen when ting further instructions. If the CPU fetches another a privileged load contro! instruction is executed or —_ extended instruction before the Extended Process- when an exception (interrupt, trap, or reset) occurs ing Unitis finished executing a previous instruction, There is a special instruction (system call) whose the STOP line may be used to delay the CPU until sole purpose is to generate a trap and thus provide the previous instruction is complete. a controlled transition from normal to system mode. The distinction between normal/system mode allows the construction of a protected operating General-P Register system. This isa program that runs in system mode gure 5-4. General-Purpose Registers and controls the system's resources, managing the execution of one or more application programs which run in normal mode. Normal and system modes, along with Memory Protection, provide the basis for protecting the operating system from mal- wo, ees as 9} functions of application programs. «fs ae ce Extended Instructions eS SS The Z8000 CPU supports seven types of extended SY as( Swe ms], instructions, which can be executed cooperatively ose ee ee by the CPU and an external Extended Processing 2 a Ce — Unit. The execution of these instructions is control- moj ES SD) yee led by the EPA control bit in the FCW. Us ee When the EPA bit is zero, it indicates that there is {4 ————=——— no Extended Processing Unit connected to the (feels oS CPU and causes the CPU to trap when it en: mlm - 1 counters an extended instruction on ae eee? This allows the operation of the extended instruc- =e SL Ee eT tion to be simulated by software running on the ee aes CPU. If the EPA bit is set, it indicates that an Extended Processing Unit is connected to the CPU in order 56 -THOMSON

Z8001,2 CPU ADDRESSING MODES Introduction This chapter describes the eight addressing modes —_ operands may reside in CPU registers or memory used by instructions to access data in memory or —_locations. The modes by which references are CPU registers. Separate sets of examples for the made to operands are called "addressing modes”, Nonsegmented and segmented modes of oper- _ Figure 6-1 illustrates these modes. Not all instruc- ation are given at the end of the chapter. tions can use all addressing modes ; some instruc- An instruction is a consecutive list of one or more Hons can use only a few and some instructions se words aligned at even-numbered byte addresses. data to be. ‘erated upon. per in memory. Most instructions have operands in ops upo! addition to an operation code (opcode). These Figure 6-1. Addressing Modes ~ Addressing Mode ‘Operand Addressing ‘Operand Value | in the Instruction ina Register in Memory | i Register [~ REGISTER ADDRESS +[orenano 7) The content of the register IM Immediate OPERAND Inthe instruction | indirect The content ot the “IR Rogister [REGISTER ADDRESS]. [ADDRESS location whose address is in the register Direct The content ofthe location Instruction ‘ ‘The content of the location BASE ADDRESS |—__—+( {arena} struction plus the content oS Te wong aster ‘The conlent ofthe location ‘elative ‘tent of the program | displacement inthe : instruction - ~ The content of he location ‘BA Base [ REGISTER ADDRESS |——+[ BASE ADDRESS ra sees ithe at A ress inthe register, ! Adoress | ysptacement | —_+(+ of GPERAND sty the displacement | ‘in the instruction ‘The content of the acation | I AN ress ina rep index J"newisten apres} | mpex}-+(+) sf OPERAND the index value in anoter i register —— ee rr Note : Do not use RO or RRO as indirect. index, or base registers,

57 Scs:THOMSON 57

Z8001,2 CPU Use of CPU Registers The 16 general-purpose CPU registers can, with —_next instruction to be executed ; whenever an in- the exceptions noted below, be used in any of the struction is fetched from memory, the PG is in- following ways : cremented to point to the next instruction. For i r ated resides within the register. “tar ig (elative to the location of an instruction, Operands ~ As pointers, where the value in the register is specified by relative addressing reside in the pro- the memory address ofthe operand, ratherthan gram address space if the memory system distin- the operand itself. In string and stack instruc quishes between program and data or stack tions, the pointers may be automatically address spaces Merton eeatene Nae OF Backward through 14 oF the addressing modes, Direct Address and Index, involve an I/O or memory address as part of ~ As index or base registers, where the contents the instruction. /O addresses are always 16 bits of the register and the word(s) following the jong. as are nonsegmented memory addresses instruction are combined to produce the ad- (28002), so these addresses occupy one word in dress of the operand. This allows efficient ac- the instruction. Segmented addresses generated cess to a variety of data structures. by the Z8001 are 23 bits long. Within an instruction, There are two exceptions to the above uses of segmented address may occupy either two words general-purpose registers : (16-bit long offset) or one word (8-bit short offset) ~ Register RO (or the double register RRO in seg: As Figure 6-2 illustrates, bit 7 of the segment mented mode) cannot be used as an indirect number byte distinguishes the two formats. When register, base register, index register, or soft- this bit is set, the long-offset representation is im- ware stack pointer. plied. When the bit is cleared, the short-offset ad- — Register R15’ (or the double register RR14’ in "ess representation is implied. For a short-ottset ing ti - dress is reduced the 28001) is used in acknowledging interrupts address, the 23-bit segmented address is andtherefore can never be used.asan accumu- {2 T6Bits by omitng the eight most sigicant bts lator in system-mode operation. The system- _ Of the offset, which are assumed to be zero. mode registers. R14’ and R15’, are automatically accessed when R14, R15, or RR14 are referenced by instructions executed Figure 6-2. Segmented Memory Address in system mode. Within instruction In addition to the general-purpose use of 28000 registers, the following registers are used for spe- cial purposes 7 as . — Register R15 (or the double register RR14 in the [REN OUR Reema) 28001) is used as a stack pointer for subroutine calls and returns. i ° — The byte register RH1 is used in the translate bulleted item instructions (TRDB, TRDRB, TRIB, TRIRB) and the translate and testinstruc- tions (TRTDB, TRTDRB, TRTIB, TRTIRB) — Register RO is used in extended instructions. 15 57 2 In Relative Address (RA) mode, the Program “ Counter (PC) is used instead of a general-purpose vacor2ee CPU register to supply the base address for an effective address calculation, The Program Counter normally is used only to keep track of the Note : Shaded area is reserves 58 5

Z8001,2 CPU Addressing Mode Descriptions Example of R mode : The following pages contain descriptions of the LD R2, R3 'load the contents of! addressing modes of the Z8000. Each description RQ into R2! - Explains how the operand address is calcu: Botre Execution = Indicates which address space (Register, VO, po ‘| ape Special /O, Data Memory, Stack Memory, or Program Memory) the operand is located in, R3 | 9A20 | — Shows the assembly language format used to : specify the addressing mode, and After Execution = Works through an example, ; po [enzo] The descriptions are grouped into two sections } | -one for nonsegmented CPUs, the other for seg- 3 | 9A20 mented CPUs. Users of the 28002 need refer to — the first section only ; users of the 28001 in non- segmented mode should also refer to the fit . the only mode that does not indicate a register should refer tothe secondsection. Intheexampies, © hexadecimal notation is used for memory ad- St memory addioss as tne source operand. The dresses and the contents of registers and memory fara P ¥ i mu locations. The % symbol precedes hexadecimal " numbers in assembly language text. INSTRUCTION Descriptions and Examples (28002 and 28001 Nonsegmented Mode) WORD(S) OPERATION In this section, the addressing modes of both the WORD(S) ‘OPERAND 28002 and the nonsegmented mode 28001 are described. ‘THE OPERAND VALUE IS IN THE INSTRUCTION. Register (R). In the Register addressing mode the instruction processes data taken from a specified Because an immediate operand is part of the in- general-purpose register. Storing data ina register _struction, itis always located in the program mem- allows shorter instructions and faster execution _ory address space. Immediate mode is often used than occur with instructions that access memory. _to initialize registers, The 28000 is optimized for this function, providing several short immediate Lcsihieaon saieilail instructions to reduce the length of programs. ‘THE OPERAND VALUE IS THE CONTENTS OF THE REGISTER. # data The operand is always in the register address Example of IM mode : space. The registerlength (byte, word, registerpair, LOB RH2 #%55 oad hex 55 into RH2! orregiser quadruple) is specified by the instruction iors Execution R2 6789 Assembler language format : After Execution RHn, Rin Byte register Rn Word register RRn Double-word register Re | 5589 RQn Quadruple-word register i577 SSS:THomson 59

Z8001,2 CPU Indirect Register (IR). In the Indirect Register Direct Address (DA). In the Direct Addressing addressing mode, the data processed is not the mode, the data processed is found at the address value in the specified register. Instead, the register. _ specified in the instruction holds the address of the data. msTmucTION INSTRUCTION REGISTER memory OPERATION OATA MEMORY ‘THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS 1$ IN REGISTER, ADDRESS I$ INTHE INSTRUCTION Depending upon the instruction, the operand spe- A single word register is used to hold the address. oie by oan Ne will bo oithar it (0 spac a vO Ary general-purpose word register can be used in crictions), in Special 1! space (Specal VO in. 8 Pt ding on th Ch 4 structions), or in data memory space. epending on the instruction, the operand speci- z - . fied by IR mode willbe ocatedineither /Oaddress TS wee is Fayripiny i Apr saloon space (VO instructions), Special VO address space 15,58 executed. (Actually, the address serves as an {Special VO instructions), or data or stack memory immediate value thal i¢ loaded into the Program address spaces. For non-l/O references, the oper eel and will be in stack memory space if the stack pointer (R15) is used as the indirect register ;other- Assembler language format : ise, the operand will be in data memory space. we ane ope ’ "y SPs address either memory, /O, or The Indirect Register mode way save space and Special 10 reduce execution time when consecutive locations are referenced. This mode can also be used 10 Example of DA mode : simulate more complex addressing modes, since : \\ “oe thet addresses can be computed before the data is LOB RH2,%5E23 pag Be with the! accessed. \\5E23! Assembler language format : Before Execution Memory @Rn a Example of IR mode : Re | 6769 pl LD R2, @RS lload R2 with the! After Execution 5E22 ee Idata addressed by the! on ‘contents of RS! re | 0689 5E24 | 0304 Before Execution Memory Index (X). In the Index Addressing mode, the ro [osor . instruction processes data located at an indexed 030F | _ address in memory. The indexed address is com- R3 0005 170A | A023 puted by adding the address specified in the in- i — struction to an “index” contained in a word register, R4 | 2000 | 170C | OBOE also specified by the instruction. Indexed address. ing allows random access to tables or other com- RS | 1706 170E | 1000 plex data structures where the address of the base After Execution _ of the table is known, but the particular element index must be computed by the program. R2 OBOE | INSTRUCTION: REGISTER R3 005 | OPenATiON] REGISTER --+[woe J — DATA MEMORY ps 5000" wos | ar] - THE OPERAND VALUE|S THE CONTENTS OF THE LOCATION WHOSE RS 170C | [ADDRESS IS THE ADDRESS IN THE INSTRUCTION, OFFSET BY THE ~ CONTENTS OF THE REGISTER. 60 .) a SS THOMSON

2Z8001,2 CPU Any word register can be used as the index register. An operand specified by RA mode is always in the except RO. program memory address space. Operands specified by X mode are always in the As with the Direct Addressing mode, the Relative data memory address space except when Index Addressing mode is used by certain program con- Addressing is used with the Jump and Calllinstruc- trol instructions to specify the address of the next tions. In these cases, the destination, computed by _ instructions to be executed (specifically, the result adding the index register contents to the base _of the addition of the Program Counter value and address, is in program memory space. the displacement is loaded into the Program ! . Counter, except when executing the DJNZ or Assembler language format : CALR instructions. The displacement is then sub- address (Rn) tracted from the PC, not added to it). Relative . addressing allows references forward or backward Example of X mode : from the current Program Counter value and is used LD R4,%231A(R3) load into Ré the con-! only for such instructions as Jumps or Calls and {tents of the memory! special loads (LDR) that can cross the normally strict location whose! boundary between program and data memory. laddress is 231A +! ithe value in R3! Assembler language format : Before Execution Memory address Example of RA mode : (Note that the symbol "$" R3 O1FE ji. is used for the value of the current program ~ — counter.) R4 203A 2516 | F3C2 2518 | 3D0E| LOR R2,$+%6 load into R2 the con-! — tents of the memory! Address Calculation 251A | 7ADA location whose! 231A address is the current! : \\ 1 1 !program counter! aoe ly hex 6! After Execution — Because the program counter will be advanced to R3 | O1FE point to the next instruction when the address R \\ apoE calculation is performed, the constant that occurs 4 | 8001 in the instruction will actually be +2. Before Execution Relative Address (RA). In the Relative Address- Program Memory ing mode, the data processed is found at an ad- © R2_— | AOFO dress relative to the current instruction. The pq | gogo . instruction specifies a two's complement displace- ment which is added to the Program Counter to 0202 | 3102 instruction form the target address. The Program Counter 0204 Tooo2 | setting used is the address of the first instruction Address Calculation | following the currently executing instruction. (The 0206 | E801! assembler will take this into account in calculating 0206 t | the constant that is assembled into the instruction.) +__2 0208 | FFFE! INSTRUCTION PC 9208 . ‘OPERATION —+[[pooness ] MeMoRY After Execution THE OPERAND VALUE ISTHE CONTENTS OFTHE LOCATION WHOSE sp.) 20G ADDRESS IS THE CONTENTS OF PC OFFSET BY THE DISPLACEMENT IN — THE INSTRUCTION: = 61

Z8001,2 CPU Base Address (BA). The Base Addressing mode After Execution Memory is similar to Index mode in that a base and offset are combined to produce the effective address. In RR2 R2 OAOO | . Base Addressing, however, a register contains the | L base address, and the displacement is expressed R3 1500; 20C0 | OABE as a 16-bit value in the instruction. The two are }~ 4 added and the resulting address points to the data R4 3100, 202 OAD to be processed. This addressing mode may be 4 used only with the Load instructions. Base Ad- R5 | 204A 20C4 1500 dressing mode, as a complement to Index mode, i allows random access to tables or other data struc: 20c6 | BODt tures where the displacement of an element within the structure is known, but the base of the particular structure must be computed by the program. Any word register can be used forthe baseaddress Base Index (BX). The Base Index addressing except RO. mode is an extension of the Base Addressing mode {An operand specitied by BA made will be in stack G6, "7a Be used only with the Load instructions, pomter Ara andin date maniee) cose cious (displacement) are held in registers. This mode ~ allows access to memory locations whose physical addresses are computed at runtime and are not INSTRUCTION REGISTER fully known at assembly time. OPERATION | REGISTER —-fooness] ~ | DMAMEMGRY Any word register can be used for either the base owsptacement. | + ) +[_orenao |] address or the index except RO. ‘THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE An operand specified by BX mode will be in stack ADDRESS 1S THE ADORESS IN THE INSTRUCTION, OFFSET BY THE memory space if the base register is the stack CONTENTS OF THE REBISTER. pointer (R15) and in data memory otherwise. Assembler language format : Assembler language format : Rn (#disp) Rn (Rm) Example of BA mode : Example of B mode : LDL R5(#%18),AR2 load the long word! LD R2,R5(R3) load into R2 the! lin RR2 into the! value whose address! Imemory location! tis the value in! [whose address is the! IRS + value in R3! \\value in RS + hex! 118! Before Execution Data Memory Before Execution Memory Re | 1F3A ie RR2 R2 ~~ | OAD | . R30 | FFFE 14FE | 0101 ns | 1500 2000 | OABE R4 | 0300 1500 | BODE R4 3100 20C2 FS50D RS | 1502 1502 F732 R5 | 200A 20C4 | BADE . 20€6 | BOD1 Address Calculation Address Calculation i ee? 20A1A ae + __18 2002 62. 1 Re SSTHOMSON

2Z8001,2 CPU After Execution R2 | BOIS | R30 FFFE Ra 0300 R5 1502 INSTRUCTION REGISTER ‘REGISTER : THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS 1S THE CONTENTS OF THE ONE REGISTER OFFSET BY THE OISPLACEMENT IN THE SECOND REGISTER, Descriptions and Examples (Segmented Example of R mode : 28001) LDL RR2, RR4 load the contents of! In this section, <<nn>> will often be used to refer IRR4 into RR2! to segment number nn. Register (R). In the Register addressing mode, fore Execution the instruction processes data taken from a speci- om fied general-purpose register. Storing data in a RR2 R2 AGBE | register allows shorter instructions and faster exe- R T oaac cution than occurs with instructions that access S| 9420 memory. RR4 RA 38A6 INSTRUCTION REGISTER R5 | 745E THE OPERAND VALUE IS THE CONTENTS OF THE REGISTER. RR2 Re | 38A6 The operand is always in the register address na | 7a5e space. The registerlength (byte, word, register pair, | 7A8E | or register quadruple) is specifiedby the instruction pry p4 | 3ga6 opcode. : | Assembler language format : RS | 745E RHn, RLn Byte register Rn Word register RRn Double-word register RQn Quadrupie-word register G57 S¢S-THOMSON 63

2Z8001,2 CPU Immediate (IM). The Immediate addressing mode A 16-bit register is used to hold an VO or Special is the only mode that does not indicate a register VO address ; a register pair is used to hold a or memory address as the location of the source — memory address. Any general-purpose register or operand. The data processed by the instruction is _register pair may be used except RO or RRO. in the instruction. The Indirect Register mode may save space and reduce execution time when consecutive locations INSTRUCTION are referenced, This mode can also be used to OPERATION simulate more complex addressing modes, since ia addresses can be computed before the data is WORD(S) ‘OPERAND accessed. THE OPERAND VALUE ISIN THE INSTRUCTION Assembler language format : @Rn Contains VO or Because an immediate operands is part of the Special /O address. instruction, it is always located in the program memory address space. Immediate mode is often © @RAn Contains memory used to initialize registers. The Z8000 is optimized address. for this function, providing several short immediate . instructions to reduce the length of programs. Example of memory Bowes using IR move : Assembler language format : LD R2, @R4 Nae Whe momneret tata location addressed! 'by the contents of! Example of IM mode : IRA! LOB RH2 #%55 load hex 55 into RH2! Belore Execution Memory T ti Before Execution pre Re [000 . Re 6789 | R3 0005] +—-170A" A023 ‘After Execution RR4 R4 — 2000| 1706 | OBOE R5 170C | 170E ‘| 1003 R2 5589 | - After Execution , ° - = Note : Segment Number 20. Indirect Register (IR). In the Indirect Register RR2 R2 | OBOE addressing mode, the data processed is not the —— value in the specified register. Instead, the register R3 0005 holds the address of the data. RR4 R4 | 2000 INSTRUCTION REGISTER ‘MEMORY R5 170C Example of /O using IR mode : THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS IN REGISTER. OUTB @At,RLO ; Before Execution Depending upon the instruction, the operand spe- cified by IR mode will be located in either VO i address space (V/O instructions), Special VO ad- 7° —| 0A23 Execution sends the dress space (Special /O instructions), or data or Rt 0011 data "23" to the VO stack memory address spaces. For non-/O refer- ences, the operand will be in stack memory space device addressed by if the stack pointer (RR14) is used as the indirect “ort” register, otherwise the operand will be in data . memory space. 64 a

Z8001,2 CPU Direct Address (DA). In the Direct Addressing _The offset of the operand address is computed by mode, the data processed is found at the address__ adding the 16-bitindex value to the 8 or 16-bitotfset specified as an operand in the instruction. portion of the address in the instruction. The seg- ment numberof the operand address comes direct- INSTRUCTION ly from the instruction. (Any overflow is ignored -it DATA MEMORY neither sets the Overflow flag nor increments the segment number). Indexed addressing aliows ran- WoROs) +L oremno] dom access to table or other complex data struc- THE OPERAND VALUES TEGONTENTS OF THE LOCATION WHose -—~«(tWT@S Where the address of the base of the table is, "ADDRESS IS IN THE INSTRUCTION known, but the particular element index must be computed by the program. Depending upon the instruction, the operand spe- cified by the Direct Address (DA) mode will be either WesTRUCTION REGITER in VO space (standard VO instructions), or in data aay [oPemaTion] REGISTER —+[ wer J — memony memory space. /O and Special /O addresses are "g) i” ‘one word long ; memory addresses can be either ‘ADDRESS ——& ~+[prerann] one or two words long, depending on whether the ye oPERAND VALUE I THE CONTENTS OF THE LOCATION WHOSE long or short format is used. [ADDRESS IS THE ADDRESS IN THE INSTRUCTION, OFFSET BY This mode is also used by Jump and Call instruc ‘THE CONTENTS OF THE REGISTER. tions to specify the address of the next instruction any word register can be used as the index register to be executed. (Actually, the address servesasan —Grdgor RO. The address inthe instruction can be immediate value that is loaded into the Program Gre or two words, depending on whether a long or Counter.) short offset is used in the address. Assembler language format : Operands specified by X mode are always in the address either memory, VO, or data memory address space. Special /O where dou- Assembler language format : ble angle brackets address (Rn) the segment , number, Example of X mode : and vertical lines *|" and *!" enclose short-form LD R4, Nload into R4 the con-! memory addresses. <<15>>%231A(R3) _ tents of the memory! ‘location whose! Example of DA mode : laddress is segment 5 LDB RH2, |c<15>>%23 load RH2 with the! (displacement 231A + value in memory! ‘segment 15, dis-! Before Execution Memory iplacement 23 (hex)! _ Before Execution Memory R3 [2 FE . ro | eveo| | ry R4 203A | ——_| 4 DOE <<15>> 0022 | 0206 2518 r 300 ‘After Execution oo24 | ogo Address Calculation 251A | 7ADA <<S>> %231A ,. ne [0688] "OIE <<5>> %2518 Index (X). In the Index addressing mode, the pier Exeout instruction processes data are located at an in- er Execution dexed address in memory. The indexed address is computed by adding the address specified in the R3 O1FE instruction to an "index" contained in a word regis- a ter, also specified by the instruction. Re 3DOE G57 S¢S-THOMSON 85

Z8001,2 CPU Relative Address (RA). In the Relative Address- the segment number is unchanged relative ad- ing mode, the data processed is found at an ad- dresses are located in the same segment as the dress relative to the current instruction. The instruction. instruction specifies a two's complement displace- _aggembler language format : ment which is added to the offset of the Program guage Counter to form the target address. The Program address Counter setting used is the address of the instruc- . tion following the currently executing instruction. Example of RA mode : (The assembler will take this info account in calcu: LOR R2g46 load into R2 the! lating the constant that is assembled into the in- ‘contents of the! struction.) !memory location! ‘whose address is the! INSTRUCTION PC Icurrent program! loseucewon] a [ren Because the program counter will be advanced to pispuacement] 4). O—[_orewvo ] point to the next instruction when the address THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE calculation is performed, the constant thal occurs ADDRESS IS THE | CONTENTS OF rc OFFSET BY ‘THE DISPLACEMENT IN. in the instruction will actually be +2. Before Execution Memory ‘An operand specified by RA mode is always in the program memory address space. Either long or 2 | short format addresses may be used. 43>» 0202 Iet02 <<13>> . As with the Direct Addressing mode, the Relative > — Instr Addressing mode is also used by certain program After Execution 0204 0002: Control instructions to specify the address of the Next instruction to be executed (specifically, the PC oD00 0206 | E801 result of the addition of the Program Counter value 208 | FFFE and the displacement is loaded into the Program R4 | 0202 9 Counter, except when executing the DJNZ or _ bad CALR instructions ; the displacement is then sub- tracted from the PC, not added to it). Relative Address Calculation addressing allows short references forward or 135> 0206 backward from the current Program Counter value <<!5>> 2 andis used only for such instructions as Jumps and 5-8 Calls and special loads (LDR). Note that because <<!9>> 66 = IMSON

ess 28001,2 CPU Base Address (BA). The Base Addressing mode Assembler language format : is similar to Index mode in that a base and displace- - ment are combined to produce the effective ad- RAn(#disp) Add the immediate dress. In Base Addressing, a register pair contains yaue towne contents of the 23-bit segmented base address and the dis- address of the operand placement is expressed as a 16-bit value in the P instruction. The displacement is added to the offset . of the base address, and the resulting address Example of BAmode: : points to the data to be processed. (The segment LOL RR4(#9618),RR2 load the long word! number is not changed.) This addressing mode jin BRE ine the j may be used only with the Load instructions. Base whose’ re eae Addressing mode, as a complement to Index tho unluo of RRA! mode, allows random access to records or other hee 16! data structures where the displacement of an ele- ment within the structure is known, but the base of the particular structure must be computed by the Before Execution Data Memory program, INSTRUCTION EGISTER(S) RR2 R2 AOFO ford +[rooness MEMORY R3 1500 | <<31>> 20C0 | OABE - © Lorem] pre ee | 2500 20c2 | F50D THE OPERAND VALUE IS THE CONTENTS OF THE LOCATION WHOSE 2004 | BADE [ADDRESS 1S ADDRESS IN THE REGISTER, OFFSET BY THE DISPLACE- RS 20AA ee MENT IN THE INSTRUCTION 20C6 BoD1 Any double-word register can be used for the base | . address except RAO. The Base Address mode Address Calculation allows access to locations whose segment num- <<13>>_ 1502 bers are not known at assembly time. + FEEE An operand specified by BA mode will be in stack <<13>> 1500 memory space if the base register is the stack pointer (RR14) and in data memory space other After Execution Data Memory wise. If the segment number is known when the program RR2 R2 [ oaoo | * is assembled (or loaded, for example, if the loader —— TOABE | can resolve symbolic segment numbers), the In- RB | 1500 | <<3t>> 20C0 | OABE | dexed addressing mode may be used to simulate pay py | 3509 | 2062 | 0A0d the based addressing mode. For example, if R2 is — known to hold segment number 18, then the oper- RS 200A 20C4 | 1500 and specified using the based address RR2 (#93) ae zoce | Bont | can also be referenced by the indexed address <<18>> %98 (R3). The advantage of this simula i tion is that indexing mode is supported for most operations, whereas based is restricted to LOAD and LOAD ADDRESS. Thus, using Indexed ad- dressing is faster and leads to compact code. -THOMSON 67

z001,2CPU Base Index (BX). The Base Index addressing modes an extension of the Base Addressing mode and may be used only with the LOAD and LOAD ADDRESS instructions. In this case, both the base address and index are held in register. The index value is added to the offset of the base address to produce the offset of the operand address. The segment number of the operand address is the same as the base address. This mode allows ac- cess to memory locations whose physical ad- dresses are computed at runtime and are not fully known at assembly time. IwstaucTiON REGISTER : REGISTER i THE OPERANO VALUE |S THE CONTENTS OF THE LOCATION WHOSE ADDRESS IS ‘THE CONTENTS OF THE ONE REGISTER OFFSET BY THE DISPLACEMENT IN THE SECOND REGISTER. Any register pair can be used for the base address Before Execution Data Memory except RRO. Any word register except RO can be _ used {or the index. Note thatthe Short Otfsetformat_ Ro. RO (3695 : for base addresses is illegal in registers. [= a ‘An operand specified by BX mode will be in stack R30 FFFE| <<t3>> 14FE 0101 memory space if the base register is the stack pR4 R4 | oDOO 1500 [ede pointer (RR14) and in data memory otherwise. _~ Assembler language format RS 1502 1502 | F732_ (see also Chapter 6) : Ty i RRn (Rn) Address Calculation Example of BX mode : eatde> 1508 LD R2,RR4 (R3) lload into Re the value! — *jgp5 SSE ‘whose address is the! ‘contents of RR4 +! Ithe contents of R3! Alter Execution Data Memory AR2 R2 BODE — RR4 R4 —_-0D00 1500 BODE RS 7 1502 F732 68 I yp sss-tromsom

28 001,2 CPU EXCEPTIONS Introduction ‘The Z8000 CPU supports three types of exceptions __the identifier as a vector to select a service routine : (conditions that can alter the normal flow of pro- _ all non-vectored interrupts are serviced by the gram execution) : same routine. They can be disabled by software. — interrupts — traps Traps — reset The 28001 and 28002 CPUs support three traps - generated internally. The Z8001 supports a fourth Interrupts are asynchronous events typically trig- trap, which is generated externally (but synchron- gered by peripheral devices needing attention. —_gusly) by the Memory Management Unit. Since a They cause the processor to temporarily suspend —_ trap always occurs when all its defining conditions its present program execution in order to service are present, traps cannot be disabled the requesting device. Traps are synchronous events that are responses by the CPU to certain Extended Instruction Trap. This trap occurs events detected during the attempted execution of when the CPU encounters an extended instruction an instruction, Thus, the major distinction between _ While the EPA bit in the FCW is cleared. This trap traps and interrupts is their origin : a trap condition _ allows the program to simulate the operations of is always reproducible by re-executing the program the EPU when none is present in the system or to that created the traps, whereas an interrupt is abort the program. generally independent of the currently executing Privileged Instruction Trap. This trap occurs task. A reset overrides all other conditions, includ- whenever an attempt is made to execute a privi- ing all interrupts and traps. It occurs when the —_leged instruction while the CPU is in normal mode RESET line is activated, and it causes certain (S/N bit in the FCWis cleared). This trap allows the control registers tobe initialized. The action thatthe CPU to detect and prevent operation (such as I/O) 28000 CPU takes in response to an interrupt, trap, that could disable the system. nthe chapter ‘hence, they are treated together system Call Trap. This trap occurs whenever a System Call (SC) instruction is executed. It allows an orderly transition to be made between normal Interrupts mode and system mode. Three kinds of interrupts are activated by three iment Trap. This trap occurs when ever the different pins on the 28000 CPU. SeeThine ie Sssoned on a 28001, regardless of Non-Maskable Interrupt (NMI). This type of inter-__ the state of the SEG bit in the FCW. This trap is rupt cannot be disabled (masked) by software. itis generated by external memory management hard- typically reserved for highest-priority external ware, such as the Z8010 Memory Management events that require immediate attention. Unit (MMU), ands the result of detecting a memory Vectored Interrupt (VI). One result of any inter- 0088s violation (such as an offset larger than the rupt or trapis that a 16-bitidentifier wordispushed signed segment length) or a write waming (a onto the system stack write into the lowest 256 bytes of a stack). See the MMU Technical Manual for more information on This word may be used to identify the source ofthe ~~ memory management hardware. interrupt or trap. In vectored interrupts, this identi- fier is also used by the CPU hardware as a pointer to select a particular interrupt service routine. The Reset processing of vectored interrupts is thus consider- _A reset initializes selected control registers of the ably faster than would be the case if ageneral rap CPU to system specifiable values. A reset can handler had to first examine the identifier, then occur at the end of any clock cycle, provided the branch off to the appropriate service routine. These RESET line is Low. interrupts can be disabled by software. A system reset overrides all other considerations, Nonvectored Interrupts (NVI). These interrupts _ including interrupts, traps, bus requests, and stop also result in an identifier word being pushed onto _requests. A reset should be used to initialize a the system stack. However, the CPU does not use _system as part of the power-up sequence. 5] 69

868 THOMSON 8

Z8001,2 CPU Reset (Continued) Within five clock cycles of the RESET becomin, Acknowledge Cycle. An external acknowledge Low, ADo - ADis are 3-stated ; AS. DS, MEO cycle is required only for externally generated re- BUSACK, and MO are forced High ;STo- STs are quest. forced High and SNo - SNs are forced Low. The The main effect of such a cycle is to receive trom RWW. B/W, and NI lines are undelined. RESET the external device a 16-bit identifier word, which must be held Low five clock cycles to properly reset _will be saved with the old program status. Before the CPU, the acknowledge cycle, the CPU enters segmented Three clock cycles after RESET has returned to _ (28001 only) system mode. (The N/S line indicates High, consecutive memory read cycles are ex- that a transition has been made to system mode.) ecuted in system mode to initialize the Program The old FCW is not affected by this change in Status registers. In the 28001, the first cycle reads mode. The CPU remains in this mode unti it begins the FCW from location 0002, the nextreads the PC _0 execute the exception service routine, at which from location 0004, and the following initial instruc- _ time its mode is dictated by the FCW. tion fetch cycle starts the program. Each of these Status Saving. The old program status informa- fetches is made from system program address tion is saved by being pushed on the system stack Space. In the 28002, the first cycle reads the PC _in the following order : The Program Counter (PC : from location 0004 and the following initial instruc- 16 bits for 28002 ; 16-bit offset followed by a word tion fetch cycle starts the program. Each of these containing the 7-bit segment number for 28001) : fetches is made from the program address space. _the Flag and Control Word (FCW) ; and finally, the interrupttrap identifier word. The identifier word Interrupt Disabling contains the reason or source of the trap or inter- Tupt. For internal traps, the identifier is the first word Vectored and nonvectored interrupts can be en- [YP trapped instruction. For segment trap or seting or tice eerie Loner ote ey interrupts, the identifier is the value on the data bus Flag and Control Word (FCW). Two control bits in ors eda fee a tls jhe ECW control the maskable interrupts : VIE and garam status in the system stack is illustrated in NVIE. Any control bit may be changed by automat. Praga’? § ically loading a new FCW during an interrupt or trap . acknowledge sequence and may be restored to its 7 previous setting by an Interrupt Return (IRET) in- rae rar Format of Saved Program Status in struction. When VIE is 1, vectored interrupts are y' enabled ; when NVIE is 1, non-vectored interrupts Zeon = are enabled. These two flags may be set or cleared Low 28, together or separately. In addition, these control sestty erase one — bits are set when the FCW is loaded. Any control Powe aren J — ioe aan bit may be changed by the occurence of an inter- | ita a ane rupt or trap and then be restored to its previous Le | setting by an Interrupt Return (IRET) instruction. Suny pase a When a type of interrupt has been disabled, the wee OF nEaacr CPU ignores any interrupt request on the corre- | sponding input pin. Because maskable interrupt request are not retained by the CPU, the request | signal must be asserted until the CPU acknow- ledges the request. + oro won Interrupt And Trap Handling es The CPU response to a trap or interrupt request consists of five steps : acknowledging the external request (for interrupts and segment traps), saving the old program status information, loading anew The following table shows i PC value that is program status, executing the service routine, and Pushed on the stack for each type of interrupt an returning to the interrupted taks. trap. 70/ =] Kz S6s:THOMSON

$28 001,2 CPU Exception PC Value is Address of identifier value 0 selects the first PC value, the value 1 selects the second PC, and so on up to the Extended Next Instruction identifier value 255. On the Z8001, the identifier Instruction Trap (Single Word Privileged Instruction) value 0 selects the first PC value, the value 2 selects the second PC, and so cn up to the identifier Frivieged , Gacond Word of Instruction value 254, which selects the 128th PC value. All Instruction Trap i (Multiple Word Privileged Instruction) vectors on 28001 systems must be even System Cal Trap | Next Instruction The program Status Area is addressed by a special Segment Trap ‘wou Instruction «>. 2 control register, the Program Status Area Pointer, | or PSAP. This pointer is one word for the nonseg- All Interrupts | Next Instruction ; 2) mented 28002 and two words for segmented Noteo: _ 28001. As shown in Figure 7-2, the pointer contains 1. Assumes successtul completion of instruction fetch. @ segment number (if applicable) and the high- 2. executing an interruptable instruction (e.g. LDIA) and the: order byte of a 16-bit offset address. The low-order instruchon's the curtent insttuction byte is assumed to contain zeros ; thus the Pro- gram Status Area must start on a 256-byte address boundary. The programmer accesses the PSAP Loading New Program Status. After saving the using the Load Contro! Register instruction current program status, the new program status (LDCTL) (PC and FCW) is automatically loaded from the Program Status Area in system program memory. The particular status words fetched from the Pro- Executing the Service Routine. Loading the new gram Status Area are a function of the type of trap program status automatically initializes the Pro- or interrupt and (for vectored interrupt) of the inter- gram Counter to the starting address of the service rupt vector. Figure 7-2 shows the format of the routine to process the interrupt or trap. This pro- Program Status Area gram is now executed. Because a new FCW was ; foaded, the maskable interrupts can be disabled for For each kind of interrupt or trap other than @ the jnitial processing of the service routine by a vectored interrupt, there is a single program status suitable choice of FCW. This allows critical informa- block that is automatically loaded into the Program —_tign to be stored before subsequent interrupts are Status registers (which includes the Flag andCon- handled. Service routines that enable interrupts trol Word and the Program Counter). before exiting permit interrupts to be handled in a Note that the size of each program status block Nested fashion. depends on the version of the 28000 (two words —_ Returning from an Interrupt or Trap. Upon com- for the nonsegmented 28002 and four words forthe —_pletion, the service routine can execute an Interrupt segmented 28001). Return instruction, IRET, to cause execution to continue at the point where the interrupt or trap for al Woe (ECW ieade same F120 279 occurred. IRET causes information to be popped from the system stack in the following order : the sponding program status block. However, the ap: iF d identifier is discarded, the saved FCW and PC are propriate Program Counter (PC) value is selected from up to 286 (28002) or 128 (28001) diferent “stored. The newly loaded FCW takes effect with values in the Pro, Si 7 the next fetched instruction, which is determined by gram Status Area. The low-order the Ne-torag Program Covator eight bits of the identifier placed on the data bus by ‘ u the interrupting device is multiplied bytwo andused On Z8001 CPUs, IRET can be executed only in as an offset into the Program Status Area following segmented mode ; in nonsegmented mode the the FCW for vectored interrupts. On the Z8002, the operation is undefined. . ral

Z8001,2 CPU Figure 7-2. Program Status Area PROGRAM STATUS AREA POINTER (PSAP) SEGNO 700.079} BYTE OFFSET OFFSET IMPLIED BYTE OFFSET HEX DECIMAL 28001 28002 DECIMAL, HEX 8 8 EXTENDED FCW 4 4 INSTRUCTION 10 16 PRIVILEGED Fow 8 8 INSTRUCTION CALL RESERVED [~~ SEGMENT 2 82 ee sear NOT USED 6 10 pcorrseT | RESERVED 2840 row] won-masxaere| FCW % “ | RESERVED [~ | 30 48 [Few] non-vecroreo | FC a we RESERVED [ 38 56 FCW 28 1c INTERRUPTS. . . . . . . . . . . . . . . . ° . . . . | ae 234 570 TT 540 21c vR001246 72 =

Z8001,2 CPU Priority Because it is possible for several exceptions to saved, and the new status is loaded. Note that occur simultaneously, the CPU enforces a priority in this case, the old status is the PC and FCW scheme for deciding which event will be honored of the previous exception’s service routine. first. The following gives the descending priority __ This process is repeated until no enabled ex- order : ceptions remain. At that point, the current PC — Reset and FCW will contain the status values for the = Internal Trap (i.e. privileged instruction, system lowest priority exception that was acknow- call, extended instruction) ledged. — Non-Maskable Interrupt = The execution of the service routines now pro- ceeds in reverse priority order. That is, the lo- ~ Segment Trap (28001 only) west priority exception is serviced first. ~ Vectored Interrupt — After all the exceptions have been serviced, the — Nonvectored Interrupt original status is restored and execution re- This is how the priority system works : sumes. — Whenever a resetis requested, itis immediately Within each of the classes above, there can be performed, multiple-interrupt sources. The internal traps are mutually exclusive and therefore need no priority — If several non-reset exceptions occur simulta- resolution within that class. The other types arise neously, the one that has the highestpriorityand from external sources : thus when multiple devices is also enabled (traps and non-maskable inter- share the same request line, the possibility arises rupts are always enabled) is acknowledged, old that more than one device may request service status is saved, and new status is loaded. The from the CPU simultaneously. Either all the inter- new status consists of the starting address of —_rypt sources must be serviced simultaneously (as the service routine (PC) and a new FCW that with the MMU) or competing requests must be may disable vectored and nonvectored inter- —resoived externally to the CPU, for example, by rupts. means of a daisy-chain or priority interrupt control- = Iany enabled exceptions remain, the highest- ler. This resolution is done during the interrupt priority one is acknowledged, the old status is acknowledge cycle.

57 S6S-THOMSON 73

BILE 28028,—§~

Z8001,2 CPU REFRESH Introduction The 28000 CPU has an internal mechanism for _RE is set to one, the value of the 6-bit RATE field refreshing dynamic memory. This mechanism can _ determines the time between successive refreshes be activated in two ways : (the refresh period). When RATE = 0, the refresh — When the Refresh Enable (RE) bit in the CPU _Period is 256 clock cycles ; when RATE =n, the Refresh Counter is set to one (Figure 8-1), _ Tefresh period is 4n clock cyles. (Thus, if there is a memory refresh is performed periodically at a. 4MHz clock, the refresh period can be from 11s to rate specified by the RATE field in the counter. 64us.) — When the STOP line is activated, the CPU The LDCTL instruction is used to set the refresh generates memory refreshes continuously. rate, to set or clear RE, or to initialize or read the ROW field Figure 8-1. Refresh Control Register The refresh cycle is generated as soon as possible after the refresh period has elapsed. This usually means after the last clock cycle of the current transaction. If the CPU receives a trap or an inter- | rupt simultaneously with a Periodic Refresh re- | TTTTTTTT quest, the refresh operation is performed first. | Fh a ho oi When the CPU _does not have control of the bus veoo247| (that is, when BUSACK is asserted and the CPU enters Bus-Disconnect state) or when the WAIT lines is deactivated, the CPU issues the skipped refresh cycles. To deal with this situation, both Refresh Cycles 28000 CPUs have internal circuitry that records when the refresh period has elapsed and refresh ire ee a aie generating a cycles cannot be generated. When the CPU re- oyole gains control of the bus, or when the WAIT line is * reactivated, it immediately issues the skipped re- A refresh cycle is three clock cycles long and may —_ fresh cycles. The internal circuitry can record up to be inserted immediately after the last clock cycle of two such skipped refresh operations. any transaction. ; After a reset operation, Periodic Refreshis disabled During a refresh cycle, the status lines are set to (RE is cleared) and the internal circuitry that counts 0001 and the address lines AD; - ADsare set tothe —_ skipped refreshes is cleared value of the row address counter. Address lines ADs - ADisare undefined, and ADo is always 0. The fresh ROW value determines the memory row that is StoP-State Retres being refreshed on this cycle. Since memory is The CPUhas three internal operating states : Run- word-organized, ADo is aways zero. Alter the re-__‘Ning, Stop, and Bus-Disconnect states Stop state fresh cycle is complete, the ROW field is in- isqrered duing ine Jistwordtetch rachine ayae cremented by two, thus stepping through 256 rows." 'S activated be} " ¥ two. thus stepping through 256 rows. oy quring the second word fetch of an EPA instruction if the STOP line is activated before the Periodic Refresh start of the machine cycle. When STOP is found The Refresh Enable (RE) bit controls only Periodic High again, one more refresh cycle is performed, Refresh ; refresh cycles may be generated using _then the remaining clock cycles of the instruction the STOP line, regardless of the state of RE. When _ fetch are executed. 74, . hy S@S-THOMSON

2Z8001,2 CPU SSS «2 007,2 CPU CHARACTERISTICS AND TIMING AC Characteristics Z9001/28002 /AZ80028 1Bz80028 | No. Symbol Parameter 2001 2800 Minin) Bie (oe) Minne) Max (re) Min. (09) Max. (ne) |

1 Tee Clock Cycle Time 250 2000 765-2000 100-2000 |

2 Twex Clock Width (High) 105 2000 7 2000 40

3 Twe Clock Width (Low) 105 2000 70 2000 40

4 Tre Clock Fall Time 20 10 10

5 The Clock Rise Time 20 18 10,

| (1) 6 Too Clock T to Segment Number Valid _ Coot oa 130 110 7 (1) 7 Tooiswy Clock T to Segment Number Not Valid 20 10 5

8 Teow, Clack T to Bus Float 65 55 «|

2 Tocm Clock To Address Valid 100 75 50 |

| 10 Tocus Clock T 10 Address Float 65 55 40! 11 Toxom Address Valid to Read Data _ ” . “ye0" ! Requred Valid “78 30s: 180" | 42 Tsonc; Read Data to Clock ! Setup Time 30 20 10 | | 19 Toon DS To Address Active 80" 45° 20"

14 Tocow, Clack T to Write Data Vaid 100 75 50

15 Themos Read Datato DS t Hold Time ° ° °

16 Toowos) Write Data Valid to DS T Delay 295° 195" 110°

17 Toawn Address Valid to MREO ! Delay (65 5)" 20"

18 Tocwm Clock J to MEG 4 Delay 80 70 40 |

| 19 Tare MEQ Wieth (High) 210° 135" 80" i | 20 Townay —- MRIEG L to Address Not Active 70" 38° 20" [21 Toowssm Wt Data Vato DS | wre) 55° 35° 1s | 22 Tonnon, MEQ 4 to Read Data Required avs" 230° 140" | Valid 23° Tocwm Clock | MREQ T Delay 80 60 45

24 Tocass) Clock T toAS 4 Delay 80 60 40

25 Tonss) _ Address Vali to AS t Delay 55 35" 20"

26 Tocusa) Clock | to. AS 7 Delay 90 80 40

27 Toxin) AS 7 to Read Data Required Valid 360° 220° 140"

28 Toosias; DST t0 AS J Delay 70" 35° 18° :

| 29 Twas AS Width (Low) 8s" 55° 30" | 30 Tors __AS To Address Not Active Detay 70 45 20° i

31 Toazosa) Address Float to DS (Read) 1 Delay 0 0 ° |

32 Toasosn, AS T to DS (Read) | Delay 80" 55° 30" |

1. Tooseom) DS (Read) | to Read Data . . . | Required Valid 205 130 70 |

34 Toons) Clock + toDS 7 Delay 70 65 45

35 Toosom DS 7 to Write Data Not Valid 7 45" 25"

Notes : 1. Only for 28001 * Clock eycle-table dependent, See table on next page. G57 SSS:THOMSON 75. SYA. fucnownsraones

28001,2 CPU AC Characteristics (Continued) No. Symbol Poremeter 8001728002 2800187280028 280018/28002B

36 Toxcsa, Address Valid toDS (Read) J Delay —«180"—SS 110" ca

37 Tociosm) Clock T to DS (Read) 4 Delay 120 85 60

38 Twosn DS (Read) Width (Low) 275" 185" 110"

39 Toowsm Clock | to DS (Write) 4 Delay 95 80 60

40 Twosw DS (Write) Width (Low) 185" 110" 75°

41 Toson, BS (VO) | to Read Data Required a0 20 120"

42 Tooosr Clock 4 to DS (VO) Delay 120 80 60

43° Twos DS (vO) Width (Low) 410° 255° 160"

44 Teasiosa, AS T to DS (Acknowledge) | Delay 1065" 690" 410°

45 Tocase Glock TDS (Achnowedgo) | 120 8s 6

148° Towson) DS Ackrowiedge | to Read Data “55° 295° 165"

47 Toes) Clock 7 to Status Valid Delay 110 85 60

48 Toss) Status Valid to AS T Delay 50" 30" 10"

49° Tec) RESET to Clock 7 Setup Time. 180" 70 50

50 Traci RESET to Clock 7 Hold Time: ° ° °

"St Tamas NMI Width (Low) i 100 70 50

52 Tsreuic; NMI to Clock t Setup Time 140 70 50

83° Tso Vi, NVI to Clock T Setup Time no 50 40

54 Tracy Vi, NVi to Clock T Hold Time 20 20 10

88 Tsscrio) __ SEGT to Clock T Setup Time 70 55 40

"56 Trsane) — SEGT to Clock T Hold Time o “oO ° ~

57 Towne Mito Clock 1 Setup Time 180 140 80

58 Thamcy Mito Clock 7 Hold Time o ° °

59 Tocwo) Clock T to MO Delay 120 85 70

60 Tssreic) STOP to Clock J Setup Time 140 100 50

61 Tisimc: STOP to Clock J Hold Time ° ° 0

62 Tomer WAIT to Clock J Setup Time 50 30 20

63 Tracy WAIT to Clock 4 Hold Time. 10 10 5

64 Tsenac; BUSREQ to Clock T Setup Time 90 80 60

65 Trenajc) _ BUSREQ to Clock T Hold Time 10 10 5

66 —Toowakm Clock T to BUSACK T Delay 100 75 60 67 —Toojpaxr) Clock 7 to BUSACK 1 Delay 100 75 60

68 Tw Address Valid Width 150° 95° 50"

69 Toosis) DS 7 to STATUS Not Valid 80° 55" 30"

Note : Clock cycle-table dependent. See table on next page.

Z8001,2 CPU Composite AC Timing Diagram wee al NV i is composite timing diagram __ pees eee Seovences” Refer to tis secr if oe nem ¥, f_TT.9 ot the worour timing’ sequences Fy war les ea ae FR fot Bev Sav — Float BV 405V ausREO ‘in 4) ws Ee SUSAR |? clock nl Y ‘ Pe 4 aD Si a Sw -- bay [ed AooRess Damn sca DATA OUT 4” Wo} 1-5 I — ! Hee Tt Red WREQ NF aa |} --- _ Tj ptt tt as | hs a Po [oper ( sere 7S Th 2 | a own — K+ | | ae INTERRUPT H 46. ACKNOWLEDGE j : _ ‘ “ ( Sp- Sty” h---- READ /WRITE, — NORMAL /SYSTEM, s P BYTE/WORD ‘vRO01240, I] 77;

Z8001,2 CPU Clock-Cycle-Time-Dependent Characteristics Number symbol 28001/Z8002 28001 A/Z8002A 28001B/Z8002B Equation Equation Equation

11 Toxom 2Tec + Twon - 130ns 2Teo + Twon - 95ns 2Toc + Twox - 60ns

13 Tossa) Twoe - 25ns Twou - 25ns Tweu- 20ns

16 Toowos) Tec + Twon - 60ns Too + Twen - 40ns Too + Twor - 30ns

17 Toawey Two - 50s Twox - 36ns Two - 20ns

19 Tyan Tec - 40ns Tec - 30ns Toc - 20ns

20 Towa Twou-38ns Twos - 35ns Two - 20ns

21 Toowinsw) Twex - 50ns Twex - 35ns Twex - 25ns

22 Towaior) 2Tee - 130ns 2Tcc - 100ns 2Tce - 6Ons

25 Toaas) Twen - 50ns Twou -36ns Twon - 20ns

27 Tpaior) 2Tec - 140ns 2Tcc - 110ns 2Tce - 6Ons

28 Toosias) —Tweu- S5ns Two -35ns Two - 25s

29 Twas Twex - 20ns Twer - 15ns Twex - 10ns

30 Toasiay Two - 35ns Twoi -25ns Tweu - 20ns

32 Toasiom) = Twen- 25ns Twou - 16ns Twet - 10ns

33 Toosor) Tec + Twox - 150ns Too + Twen - 108ns Too + Two - 70ns

35 Toosiow) Twei - 30ns Twet - 25ns Twet - 150s

36 Towosr) Tec - 70ns Teo - 85 ns Tec - 38ns

38 Twosr Tec + Twer - 80ns Toe + Twex - 50ns- Toc + Twer = 30ns

40 Twosw Tec - 65ns Toe - 55ns Toc - 25ns

41 Toosyor) _-2Toc- 170ns 2Too - 120ns 2Tec- Bons

43 Twos 2Tec - 90ns 2Too - 75ns 2Toc- 4ons

44 Toasiosa) Tec + Two - 40ns 4Too + Twou - 40ns 4Toc + Twou -30ns

48 Toosaoay —-2Too + Twn - 150ns 2Too + Twou - 105ns 2Too + Two - 75ns

48 Tosis) Twou - 55s Twor = 40ns Twou - 30ns

68 Twa Toc - 90ns To + 7ons Tee = 50ns

69 Toosis) Twer - 25ns Twet - 15ns Twee - 10ns

Z8001,2 CPU Absolute Maximum Ratings Voltages on all inputs and outputs with respect 4 ; Yoo | teGND 0.310 +7.0 v Ta Operating Ambient Temp 00470 ; oc! Note: Stresses greater than those isteg under Absolute Maximum Ratings may cause permanent damage io he device. This is a sress rating Gly seperation! the device at ary corditon above those indicated inthe operational sections of these specticalions isnot implied. Exposure to absolute maximum raing condidons for extended periods may affect device rekabity Test Conditions The characteristics below apply for the following - test conditions, unless otherwise noted. All volt- ages are referenced to GND (OV). Positive current 2 flows into the referenced pin. Available operating «aoe oa . temperature range is : 0°C to +70°C, Veo = 5V + 5% F ane t | 1 fT ANAC parameters assume a load capacitance ot 100pF max., except for parameter 6 (S0pF max). ring. references between two output Sighals assume a load dterence 0 S0pF max DC Characteristics Symbol Parameter Min. | Max. | Unit Condition i Vow | Clock Input High Voltage Veo 0.4 | Veo +03 | v__| Riven by External Clock j Driven by External Clock | Yor Clock input Low Voge | 99 | 94s |v | Borate | Via | Input High Voltage 20 |Vcc+03' V Vo. | Output Low Voltage i lo. = +2.0mA lo | Ouput Leakage a eee 0.45 Vins 42.4V | le | Vee Supply Current | 300 | mA | aMH2- 6MHz | lec | Voc Supply Current i 40MHz | G57 S6S:THOMSON 79.

Z8001,2 CPU

ORDERING INFORMATION

Type Package Temperature Clock © 28001 B1V | 4MH2 ZB001AB1V Plastic DILas. 0/+70°C 6MH2

28001 BBIV 10MHz

78002 B1V | 4MHz

78002 ABIV | Plastic | DIL4o | 0/+70°C 6MHz

78002 BB1V | 10MHz

Irlormatonturshedsbateed 10 be acute and robe, However, SGS THOMSON Meyoeactones assures no esponity fr ne ‘Sane den Suh tah yy ras un ar esate hay eae NS ican pry alr ose a tar pastes of S66 PGMS Keroaesne Westesen ees Fee ee vein or ned era ait er to THOMSON eros peale mentnes SGS-THOMSON Microolecironics pronucts are ‘not authorized for use as critical components in lite suy devices or systems without express Sito shea SSS PRS Reena ia © 1991 SGS-THOMSON Micoetcorics ~Pntedin lay - Al gis Reserved SGSTHOMSON crooucroncs GROUP OF COMPANIES Australia - Brazil - France - Germany Borg Kong ~ Ntaly - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - ‘Singapore - Spain - ‘Switzerland - Taiwan - United Kingdom - U.S.A. ae 2728 osesea VW _