XPSM82866AA0PRCFR

TPSM82864A TI | Alldatasheet

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Technical content

TPSM8286xA 2.4V to 5.5V Input, 4A/6A, Step-Down Power Module With Integrated Inductor in a Thin, Overmolded QFN and MagPack™ Package

1 Features

• Up to 96% efficiency
• Excellent thermal performance
• 1% output voltage accuracy
• DCS-Control topology for fast transient response
• Designed for low EMI requirements – MagPack technology shields inductor and IC – No bond wire package – Simplified layout through optimized pinout
• 2.4V to 5.5V input voltage range
• Same device part number provides: – 0.6V to VIN adjustable output voltage – 13 integrated fixed output voltage options – Forced PWM or power save mode
• Power-good indicator with window comparator
• 2.4MHz switching frequency
• 4µA operating quiescent current
• Output voltage discharge
• 100% duty cycle mode
• –40°C to 125°C operating temperature range
• QFN package with 0.5mm pitch: – RDJ, RDM: 3.5mm × 4.0mm – RCF (MagPack): 2.3mm × 3.0mm
• Small design size: – RDJ, RDM: 35mm2 design size – RCF (MagPack): 28mm2 design size
• Also available with I2C interface: TPSM82866C

2 Applications

• Core supply for FPGAs, CPUs, ASICs
• Optical modules
• Industrial transport
• Factory automation and control
• Aerospace and defense

3 Description

The TPSM8286xA device family consists of 4A and 6A step-down converter power modules designed for small solution size and high efficiency. The power modules integrate a synchronous step-down converter and an inductor to simplify design, reduce external components, and save PCB area. The low-profile and compact solution is designed for automated assembly by standard surface mount equipment. Tight output voltage accuracy, even with small output capacitors, is achieved though the DCS-Control architecture and the excellent load transient performance. At medium-to-heavy loads, the converter operates in PWM mode and automatically enters power save mode operation at light load to maintain high efficiency over the entire load current range. The devices can also be forced in PWM mode operation for the smallest output voltage ripple. The EN and PG pins, which support sequencing configurations, bring a flexible system design. An integrated soft start reduces the inrush current required from the input supply. The RDJ package supports thin designs with 1.4mm height. Device Information PART NUMBER(3) OUTPUT CURRENT PACKAGE(1) BODY SIZE (NOM) TPSM82864A 4A RDJ or RDM (B0QFN, 23) 3.50mm × 4.00mmTPSM82866A 6A TPSM82864A(2) 4A RCF (QFN- FCMOD, 15) 2.30mm × 3.00mmTPSM82866A 6A (1) For more information, see Section 11. (2) Preview information (not Production Data). (3) See the Device Options table. VOUT AGND PGND VOS EN VIN 2 × 22 µF or 1 × 47 µF 22 µF VIN 2.4 V to 5.5 V VOUT 1.8 V VSET/ MODEPG FBR3 VPG 133 kΩ Typical Application Schematic – Fixed Output Voltage Option Output Current (A) Efficiency (%) 100 1100m10m1m100u 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V FPWM PSM TPSM82866AA0HRDMR – Efficiency Versus Output Current; VIN = 5.0V TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

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4 Device Options

NUMBER(1) OUTPUT CURRENT OPERATING FREQUENCY NOMINAL INDUCTANCE BODY SIZE DEVICE HEIGHT TPSM82864AA0SRDJR 4 A

2.4 MHz

220 nH 3.5 mm × 4.0 mm 1.4 mm TPSM82866AA0SRDJR 6 A TPSM82864AA0HRDMR 4 A 1.8 mm TPSM82866AA0HRDMR 6 A TPSM82864AA0PRCFR(2) 4 A 200 nH 2.3 mm × 3.0 mm 1.95 mm TPSM82866AA0PRCFR 6 A TPSM82864BA0PRCFR(2) 4 A

1.2 MHz

TPSM82866BA0PRCFR(2) 6 A (1) For more information, see Section 11. (2) Preview information (not Production Data).

5 Pin Configuration and Functions

Figure 5-1. TPSM82864A, TPSM82866A - RCF (15 Pin) QFN-FCMOD TOP VIEW BOTTOM VIEW PGND SW PGND PGND PGND VOUT SW PGND PGND VOS FB AGND AGND PGND PGND VIN VIN EN PGND VSET/MODE PG EN VOUT VOUT VOUT VOUT Exposed Thermal Pad PGND SW PGND PGND PGND VOUT SW PGND PGND VOS FB AGND AGND PGND PGND VIN VIN EN PGND VSET/MODE PG EN VOUT VOUT VOUT VOUT Exposed Thermal Pad 78 9 101112 18 19 20 21 22 1 7 8 9 10 11 12 1819202122 Figure 5-2. TPSM82864A, TPSM82866A - RDJ (23 Pin) and RDM (23 Pin) B0QFN www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPSM82864A TPSM82866A

Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME RDJ and RDM RCF AGND 18 11 P Analog ground pin. Must be connected to a common GND plane. EN 1 2 I Device enable pin. To enable the device, this pin must be pulled high. Pulling this pin low disables the device. Do not leave floating. FB 17 10 I Voltage feedback input. Connect the output voltage resistor divider to this pin. When using a fixed output voltage, connect directly to VOUT. PG 2 3 O Power-good open-drain output pin. The pullup resistor can be connected to voltages up to 5.5 V. If unused, leave this pin floating. This pin is pulled to GND when the device is in shutdown. PGND 4, 5, 6, 8, 9, 10, 11, 19, 8, 9, 12, 13 P Power ground pin. Must be connected to common GND plane. SW 7 15 O Switch pin of the power stage. This pin can be left floating. VIN 21, 22 1, 14 P Power supply input voltage pin VOS 16 7 I Output voltage sense pin. This pin must be directly connected to the output capacitor. VOUT 12, 13, 14, 15 5, 6 P Output voltage pin VSET/ MODE 3 4 I Connecting a resistor to GND selects one of the fixed output voltages. Tying the pin high or low selects an adjustable output voltage. After the device has started up, the pin operates as a MODE input. Applying a high level selects forced PWM mode operation and a low level selects power save mode operation. Exposed Thermal Pad 23 - P Internally connected to PGND. Must be soldered to achieve appropriate power dissipation and mechanical reliability. Must be connected to common GND plane. (1) I = Input, O = Output, P = Power TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage(2) VIN, EN, VOS, FB, PG, VSET/MODE –0.3 6 VSW (DC), VOUT –0.3 VIN + 0.3 SW (AC, less than 10ns)(3) –2.5 10 ISINK_PG Sink current at PG 2 mA TJ Junction temperature –40 125 °C Tstg Storage temperature –40 125 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to network ground terminal. (3) While switching.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

VIN Supply voltage range 2.4 5.5 V VOUT Output voltage range 0.6 VIN V tF_VIN Falling transition time at VIN (1) 10 mV/µs IOUT Output current, TPSM82864A 4 A Output current, TPSM82866A 6 RVSET Nominal resistance range for external voltage selection resistor (E96 resistor series) 10 249 kΩ External voltage selection resistor tolerance 1% External voltage selection resistor temperature coefficient ±200 ppm/°C TJ Junction temperature –40 125 °C (1) The falling slew rate of VIN must be limited if VIN goes below VUVLO (see Power Supply Recommendations). www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSM82864A TPSM82866A

6.4 Thermal Information

THERMAL METRIC(1) TPSM8286xA UNITRDM (23 PINS) RDJ (23 PINS) RCF (15 PINS) JEDEC 51-5 EVM JEDEC 51-5 EVM JEDEC 51-7 EVM RθJA Junction-to-ambient thermal RθJC(top) Junction-to-case (top) thermal resistance 42.5 n/a(2) 34.3 n/a(2) 31.8 n/a(2) °C/W Rθ JC(bottom) Junction-to-case (bottom) thermal resistance 21.1 n/a(2) 22.2 n/a(2) n/a(3) n/a(2) °C/W RθJB Junction-to-board thermal resistance 14.9 n/a(2) 10.8 n/a(2) 19.5 n/a(2) °C/W ΨJT Junction-to-top characterization ΨJB Junction-to-board characterization (1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. (2) Not applicable to an EVM. (3) Only applicable for packages with exposed thermal pad. (4) The junction temperature is lower than the inductor temperature leading to a temperature increase towards the top of the package TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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6.5 Electrical Characteristics

TJ = –40°C to 125°C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ_VIN Quiescent current into VIN pin EN = High, no load, device not switching 4 10 µA IQ_VOS Quiescent current into VOS pin EN = High, no load, device not switching, VVOS = 1.8 V 8 µA ISD Shutdown current EN = Low, TJ = －40℃ to 85℃ 0.24 1 µA VUVLO Undervoltage lockout threshold VIN rising 2.2 2.3 2.4 V VIN falling 2.1 2.2 2.3 V TJSD Thermal shutdown threshold TJ rising 150 °C Thermal shutdown hysteresis TJ falling 20 °C LOGIC INTERFACE VIH High-level input threshold voltage at EN and VSET/MODE 1.0 V VIL Low-level input threshold voltage at EN and VSET/MODE 0.4 V IEN,LKG Input leakage current into EN pin 0.01 0.1 µA START-UP, POWER GOOD tDelay Enable delay time Time from EN high to device starts switching with a 249-kΩ resistor connected between VSET/ MODE and GND 420 650 1100 µs tRamp Output voltage ramp time Time from device starts switching to power good 0.8 1 1.5 ms VPG(low) Power-good lower threshold VFB referenced to VFB(nominal) 85 91 96 % VPG(high) Power-good upper threshold VFB referenced to VFB(nominal) 103 111 120 % VPG,OL Low-level output voltage Isink = 1 mA 0.4 V IPG,LKG Input leakage current into PG pin VPG = 5.0 V 0.01 0.1 µA tPG,DLY Power good delay Rising and falling edges 34 µs OUTPUT VOUT Output voltage accuracy Fixed voltage operation, FPWM, no load, TJ = 0°C to 85°C –1 1 % Fixed voltage operation, FPWM, no load –2 2 % VFB Feedback voltage Adjustable voltage operation 594 600 606 mV IFB,LKG Input leakage into FB pin Adjustable voltage operation, VFB = 0.6 V 0.01 0.4 µA RDIS Output discharge resistor at VOS pin 3.5 Ω Load regulation VOUT = 1.2 V, FPWM 0.04 %/A POWER SWITCH RDP Dropout resistance TPSM8286xAA0SRDJ 100% mode. VIN = 3.3 V, TJ = 25°C 28 35 mΩ TPSM8286xAA0PRCF 100% mode. VIN = 3.3 V, TJ = 25°C 26 mΩ TPSM8286xAA0HRDM 100% mode. VIN = 3.3 V, TJ = 25°C 26 mΩ ILIM High-side FET forward current limit TPSM82864A 5 5.5 6 A TPSM82866A 7 7.9 9 A Low-side FET forward current limit TPSM82864A 4.5 A TPSM82866A 6.5 A Low-side FET negative current limit –3 A fSW PWM switching frequency TPSM82866Ax, IOUT = 1 A, VOUT = 1.2 V 2.4 MHz www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSM82864A TPSM82866A

6.6 Typical Characteristics

Input Voltage (V) Quiescent current IQ_VIN (uA) TJ = -40°C TJ = 25°C TJ = 85°C TJ = 125°C Figure 6-1. Quiescent Current into VIN IQ_VIN Input Voltage (V) Shutdown current ISD (uA) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 TJ = -40°C TJ = 25°C TJ = 85°C TJ = 125°C Figure 6-2. Shutdown Current ISD Input Voltage (V) Output Discharge Resistance RDIS (Ohms) TJ = -40°C TJ = 25°C TJ = 85°C TJ = 125°C Figure 6-3. Output Discharge Resistance RDIS Input Voltage (V) Dropout Resistance RDP (mOhms) TJ = -40°C TJ = 25°C TJ = 85°C TJ = 125°C TPSM8286xAA0SRDJ Figure 6-4. Dropout Resistance RDP Input Voltage (V) Dropout Resistance R DP (m) TJ = -40C TJ = 25 C TJ = 85 C TJ = 125C TPSM8286xAA0HRDM Figure 6-5. Dropout Resistance RDP Input Voltage (V) Dropout Resistance RDP (m) TJ = -40C TJ = 25 C TJ = 85 C TJ = 125C TPSM8286xAA0PRCF Figure 6-6. Dropout Resistance RDP TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The TPSM8286xA synchronous step-down converter power module is based on DCS-Control (Direct Control with Seamless transition into power save mode). This topology is an advanced regulation topology that combines the advantages of hysteretic, voltage, and current mode control. The DCS-Control topology operates in PWM (pulse width modulation) mode for medium-to-heavy load conditions and in PSM (power save mode) at light load currents. In PWM, the converter operates with the nominal switching frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. As the load current decreases, the converter enters power save mode, reducing the switching frequency and minimizing the quiescent current of the IC to achieve high efficiency over the entire load current range. DCS-Control supports both operation modes using a single building block and, therefore, has a seamless transition from PWM to PSM without effects on the output voltage. The TPSM8286xA offers excellent DC voltage regulation and load transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits. The TPSM8286xxxxP versions in the RCF package use MagPack technology to deliver the highest-performance power module design. Leveraging our proprietary integrated-magnetics MagPack packaging technology, these power modules deliver industry-leading power density, high efficiency and good thermal performance, ease of use, and reduced EMI emissions.

7.2 Functional Block Diagram

VPG(high) VFB VPG(low) RDIS AGND PG FB VOUT PG delay LVREF selection

7.3 Feature Description

7.3.1 Power Save Mode

As the load current decreases, the device seamlessly enters power save mode (PSM) operation. In PSM, the converter operates with a reduced switching frequency and a minimum quiescent current to maintain high efficiency. Power save mode is based on a fixed on-time architecture, as shown in Equation 1. The inductance used in the RCF package using MagPack technology is 200 nH typical where the inductance used in the RDJ and RDM packages is 220 nH typical. t ON = V OU T V I N × f SW (1) www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSM82864A TPSM82866A

For very small output voltages, an absolute minimum on time of approximately 50ns is kept to limit switching losses. The operating frequency is thereby reduced from the nominal value, which keeps efficiency high. The switching frequency in PSM is estimated as: f PS M = 2 × I OU T t O N 2 × V I N V OU T × V I N − V OU T L (2) The load current at which PSM is entered is at one half of the ripple current of the inductor and can be estimated as: I L oad PS M − en tr y = V I N × t O N 2 × 1 − V O U T V I N L (3) In power save mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized by increasing the output capacitance.

7.3.2 Forced PWM Mode

After the device has powered up and ramped up VOUT, the VSET/MODE pin acts as a digital input. With a high level on the VSET/MODE pin, the device enters forced PWM (FPWM) mode and operates with a constant switching frequency over the entire load range, even at very light loads. This reduces the output voltage ripple and allows simple filtering of the switching frequency for noise-sensitive applications but lowers efficiency at light loads.

7.3.3 Optimized Transient Performance from PWM to PSM Operation

For most converters, the load transient response in PWM mode is improved compared to PSM, because the converter reacts faster on the load step and actively sinks energy on the load release. As an additional feature, the TPSM8286xA automatically stays in PWM mode for 128 cycles after a heavy load release to bring the output voltage back to the regulation level faster. After these 128 cycles of PWM mode, it automatically returns to PSM (if VSET/MODE is low). See Figure 7-1. Without this optimization, the output voltage overshoot is higher. VOUT IOUT FPWM mode for 128 switching cycles Device operates in PWM because of high load current PSM mode PSM mode Figure 7-1. Optimized Transient Performance from PWM to PSM TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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7.3.4 Low Dropout Operation (100% Duty Cycle)

The device offers a low dropout operation by entering 100% duty cycle mode if the input voltage comes close to the target output voltage. In this mode, the high-side MOSFET switch is constantly turned on. This is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain a minimum output voltage is given by: VIN (min) = VOUT (min) + IOUT (max) × RDP (4) where

• VOUT (min) = Minimum output voltage the load can accept
• IOUT (max) = Maximum output current
• RDP = Resistance from VIN to VOUT (high-side RDS(on) + RDC of the inductor)

7.3.5 Soft Start

After enabling the device, there is a 650-µs enable delay (t Delay) before the device starts switching. The t Delay time varies with the VSET/MODE resistor used and is longest with a resistance of 249 k Ω or higher. After the enable delay, an internal soft-start circuit ramps up the output voltage in 1 ms (t Ramp). This action avoids excessive inrush current and creates a smooth output voltage ramp up. This action also prevents excessive voltage drops of batteries that have a high internal impedance. Figure 7-2 shows the start-up sequence. VIN VOUT EN tDelay tRamp tStart-up Figure 7-2. Start-Up Sequence The device is able to start into a prebiased output capacitor. The device starts with the applied bias voltage and ramps the output voltage to the nominal value.

7.3.6 Switch Current Limit and HICCUP Short-Circuit Protection

The switch current limit prevents the device from high inductor current and from drawing excessive current from the battery or input voltage rail. Excessive current can occur with a heavy load or shorted output circuit condition. If the inductor current reaches the threshold I LIM, cycle by cycle, the high-side MOSFET is turned off and the low-side MOSFET is turned on until the inductor current ramps down to the low-side MOSFET current limit. When the high-side MOSFET current limit is triggered 256 times, the device stops switching. The device then automatically re-starts with soft start after a typical delay time of 16 ms has passed. The device repeats this mode until the high load condition disappears. This HICCUP short-circuit protection reduces the current consumed from the input supply because the device only draws input current approximately 10% of the time during an overload condition. Figure 8-37 shows the hiccup short-circuit protection. The low-side MOSFET also contains a negative current limit to prevent excessive current from flowing back through the inductor to the input. If the low-side sinking current limit is exceeded, the low-side MOSFET is turned off. In this scenario, both MOSFETs are off until the start of the next cycle. The negative current limit is only active in forced PWM mode. www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPSM82864A TPSM82866A

7.3.7 Undervoltage Lockout

To avoid mis-operation of the device at low input voltages, undervoltage lockout (UVLO) disables the device when the input voltage is lower than V UVLO. When the input voltage recovers, the device automatically returns to operation with soft start.

7.3.8 Thermal Shutdown

When the junction temperature exceeds T JSD, the device goes into thermal shutdown, stops switching, and activates the output voltage discharge. When the device temperature falls below the threshold by the hysteresis, the device returns to normal operation automatically with soft start. TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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7.4 Device Functional Modes

7.4.1 Enable and Disable (EN)

The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is pulled low. In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal switch smoothly discharges the output through the VOS pin in shutdown mode. Do not leave the EN pin floating. The typical enable threshold value of the EN pin is 0.66 V for rising input signals and the typical shutdown threshold is 0.52 V for falling input signals.

7.4.2 Output Discharge

The purpose of the output discharge function is to make sure of a defined down-ramp of the output voltage when the device is disabled and to keep the output voltage close to 0 V. The output discharge is active when the EN pin is pulled low, when the input voltage is below the UVLO threshold or during thermal shutdown. The discharge is active down to an input voltage of 1.6 V (typical).

7.4.3 Power Good (PG)

The device has an open-drain power-good pin, which is specified to sink up to 2 mA. The power-good output requires a pullup resistor connected to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. Table 7-1 shows the typical PG pin logic. Table 7-1. PG Pin Logic DEVICE CONDITIONS LOGIC STATUS HIGH IMPEDANCE LOW Enable 0.9 × VOUT_NOM ≤ VVOUT ≤ 1.1 × VOUT_NOM √ VVOUT < 0.9 × VOUT_NOM or VVOUT > 1.1 × VOUT_NOM √ Shutdown EN = low √ Thermal shutdown TJ > TJSD √ UVLO 1.8 V < VIN < VUVLO √ Power supply removal VIN < 1.8 V undefined The PG pin has a 34-μs delay time on the falling edge and a 34-μs delay before PG goes high. See Figure 7-3. VO VPG(low) PG tPG,DLY tPG,DLY tPG,DLY tPG,DLY tPG,DLY tPG,DLY VPG(high) Figure 7-3. Power-Good Transient and Delay Behavior www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPSM82864A TPSM82866A

7.4.4 Output Voltage and Mode Selection (VSET/MODE)

The TPSM8286xA family devices are configurable as either an adjustable output voltage or a fixed output voltage, depending on the needs of each individual application. This feature simplifies the logistics during mass production, as one part number offers several fixed output voltage options as well as an adjustable output voltage option. During the enable delay (t Delay), the device configuration is set by an external resistor connected to the VSET/MODE pin through an internal R2D (resistor to digital) converter. This configures the V REF input to the error amplifier (EA) to be either the V FB voltage (0.6-V typical) or the selected output voltage. Table 7-2 shows the options. Table 7-2. Output Voltage Selection Table RESISTOR AT VSET/MODE PIN (E96 SERIES, ±1% ACCURACY, 200 ppm/°C OR BETTER) FIXED OR ADJUSTABLE OUTPUT VOLTAGE 249 k or logic high Adjustable (through a resistive divider on the FB pin) 205 k 3.30 V 162 k 2.50 V 133 k 1.80 V 105 k 1.50 V 68.1 k 1.35 V 56.2 k 1.20 V 44.2 k 1.10 V 36.5 k 1.05 V 28.7 k 1.00 V 23.7 k 0.95 V 18.7 k 0.90 V 15.4 k 0.85 V 12.1 k 0.80 V 10 k or logic low Adjustable (through a resistive divider on the FB pin) The R2D converter has an internal current source, which applies current through the external resistor, and an internal ADC, which reads back the resulting voltage level. Depending on the detected resistance, the output voltage is set. After this R2D conversion is finished, the current source is turned off to avoid current flowing through the external resistor. Make sure that the additional leakage current path is less than 20 nA and the capacitance is not greater than 30 pF from this pin to GND during R2D conversion, otherwise a false V OUT value is set. For more details, refer to the Benefits of a Resistor-to-Digital Converter in Ultra-Low Power Supplies White Paper . When the device is set to a fixed output voltage, the FB pin must be connected to the output directly. See Figure 7-4. VOUT AGND PGND VOS EN VIN 2 × 22 µF or 1 × 47 µF 22 µF VIN 2.4 V to 5.5 V VOUT 1.8 V VSET/ MODEPG FBR3 VPG 133 kΩ Figure 7-4. Fixed Output Voltage Application Circuit TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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After the start-up period (t Start-up), a different operation mode can be selected. When VSET/MODE is set to high, the device is in forced PWM mode . Otherwise, the VSET/MODE resistor pulls the pin low and the device operates in power save mode. www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSM82864A TPSM82866A

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TPSM8286xA is a synchronous step-down converter power module family. The following section discusses the selection of the external components to complete the power supply design. The required power inductor is integrated inside the TPSM8286xA. The integrated shielded inductor has a value of 220 nH with a ±20% tolerance for the RDJ and RDM packages. The RCF MagPack package not only has a 200 nH shielded inductor but also shields the IC for a better EMI performance. The TPSM82864A and TPSM82866A in the RDJ and RDM packages are pin-to-pin and BOM-to-BOM compatible. The TPSM8286xAA0HRDMR devices give a higher efficiency than the TPSM8286xAA0SRDJR devices due to the increased height. For a given package height (RDM or RDJ), the 4A and 6A version give the same efficiency and performance and are different only in the rated output current. The RCF package, using MagPack technology, is less than half the size of the other package versions (RDM and RDJ), thus shrinking the total design size by about 20%, while maintaining the same high efficiency as the other packages.

8.2 Typical Application

2 × 22 µF or 1 × 47 µF 22 µF VIN 2.4 V to 5.5 V VOUT 1.2 V VSET/ MODE PG FB VPG Figure 8-1. Typical Application

8.2.1 Design Requirements

For this design example, use Table 8-1 as the input parameters. Table 8-1. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 2.4 V to 5.5 V Output voltage 1.2 V Maximum output current 6 A TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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Table 8-2 lists the components used for the example. Table 8-2. List of Components REFERENCE DESCRIPTION MANUFACTURER(1) C1 22 µF, Ceramic capacitor, 6.3 V, X7R, size 0805, GRM21BZ70J226ME44 Murata C2 47 µF, Ceramic capacitor, 6.3 V, X6S, size 0805, JMK212BC6476MG-T or GRM21BC80J476ME01L Taiyo Yuden or Murata R1 Depending on the output voltage, Chip resistor, 1/16 W, 1% Std R2 100 kΩ, Chip resistor, 1/16 W, 1% Std R3 100 kΩ, Chip resistor, 1/16 W, 1% Std (1) See the Third-party Products disclaimer.

8.2.2 Detailed Design Procedure

8.2.2.1 Setting The Output Voltage

With the VSET/MODE pin set high or low, an adjustable output voltage is set by an external resistor divider according to Equation 5: OUT OUT FB V V R 1 R2 1 R2 1V 0.6V © ¹ © ¹ (5) To keep the feedback (FB) net robust from noise, set R2 equal to or lower than 100 k Ω to have at least 6 µA of current in the voltage divider. Lower values of FB resistors achieve better noise immunity but lower light-load efficiency, as explained in the Design Considerations for a Resistive Feedback Divider in a DC/DC Converter Technical Brief. When a fixed output voltage is selected, connect the FB pin directly to the output. R1 and R2 are not needed, as VOUT is set through a resistor on the VSET/MODE pin. Select the recommended resistor value from the list in Table 7-2.

8.2.2.2 Input and Output Capacitor Selection

For the best output and input voltage filtering, low-ESR ceramic capacitors are required. The input capacitor minimizes input voltage ripple, suppresses input voltage spikes, and provides a stable system rail for the device. The input capacitor must be placed between VIN and PGND as close as possible to those pins. For most applications, 22 μF is sufficient, though a larger value reduces input current ripple. The input capacitor plays an important role in the EMI performance of the system as explained in the Simplify Low EMI Design With Power Modules White Paper. The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. The capacitor value can range from 2 × 22 µF up to 150 µF. The recommended typical output capacitors are 2 × 22 µF or 1 × 47 µF with an X5R or better dielectric. Values over 150 µF can degrade the loop stability of the converter. Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance. Choose the right capacitor carefully in combination with considering the package size and voltage rating. Make sure that the effective input capacitance is at least 10 µF and the effective output capacitance is at least 22 µF. www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSM82864A TPSM82866A

8.2.3 Application Curves

VIN = 5.0 V, V OUT = 1.2 V, T A = 25°C, BOM = Table 8-2, unless otherwise noted. Solid lines show the FPWM mode and dashed lines show PSM. Output Current (A) Efficiency (%) 100 1100m10m1m100u 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V TPSM8286xAA0PRCF PSM and FPWM Figure 8-2. Efficiency VIN = 5.0 V and TA = 25°C Output Current (A) Efficiency (%) 100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V TPSM8286xAA0PRCF FPWM Figure 8-3. Efficiency VIN = 5.0 V and TA = 85°C Output Current (A) Efficiency (%) 100 1100m10m1m100u 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V TPSM8286xAA0PRCF PSM and FPWM Figure 8-4. Efficiency VIN = 3.3 V and TA = 25°C Output Current (A) Efficiency (%) 100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V TPSM8286xAA0PRCF FPWM Figure 8-5. Efficiency VIN = 3.3 V and TA = 85°C Output Current (A) Efficiency (%) 100 1100m10m1m100u 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V TPSM8286xAA0PRCF PSM and FPWM Figure 8-6. Efficiency VIN = 2.8 V and TA = 25°C Output Current (A) Efficiency (%) 100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V TPSM8286xAA0PRCF FPWM Figure 8-7. Efficiency VIN = 2.8 V and TA = 85°C TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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Output Current (A) Efficiency (%) 100 1100m10m1m100u 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V TPSM8286xAA0HRDM PSM and FPWM Figure 8-14. Efficiency VIN = 5.0 V and TA = 25°C Output Current (A) Efficiency (%) 100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V Output Current (A) Efficiency (%) 100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V TPSM8286xAA0HRDM FPWM Figure 8-15. Efficiency VIN = 5.0 V and TA = 85°C Output Current (A) Efficiency (%) 100 1100m10m1m100u 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V TPSM8286xAA0HRDM PSM and FPWM Figure 8-16. Efficiency VIN = 3.3 V and TA = 25°C Output Current (A) Efficiency (%) 100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V TPSM8286xAA0HRDM FPWM Figure 8-17. Efficiency VIN = 3.3 V and TA = 85°C Output Current (A) Efficiency (%) 100 1100m10m1m100u 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V TPSM8286xAA0HRDM PSM and FPWM Figure 8-18. Efficiency VIN = 2.8 V and TA = 25°C Output Current (A) Efficiency (%) 100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V TPSM8286xAA0HRDM FPWM Figure 8-19. Efficiency VIN = 2.8 V and TA = 85°C TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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Output Current (A) Switching Frequency (MHz) 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 110m 100m 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V PSM and FPWM TA = 25°C Figure 8-26. Switching Frequency VIN = 5.0 V Output Current (A) Switching Frequency (MHz) 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 110m 100m 6 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V PSM and FPWM TA = 25°C Figure 8-27. Switching Frequency VIN = 3.3 V VIN = 3.3 V VOUT = 1.2 V COUT = 1 × 47uF Figure 8-28. FPWM Operation IOUT = 3 A VIN = 5.0 V VOUT = 1.2 V COUT = 1 × 47 uF Figure 8-29. PSM Operation IOUT = 0.1 A VIN = 3.3 V VOUT = 1.2 V COUT = 3 × 22uF Figure 8-30. FPWM Operation IOUT = 3 A VIN = 3.3 V VOUT = 1.2 V COUT = 3 × 22uF Figure 8-31. FPWM Operation IOUT = 0.1 A TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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Ambient Temperature (°C) Output Current (A) 75 80 85 90 95 100 105 110 115 120 1.5 2.5 3.5 4.5 5.5 6.5 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V RθJA = 29.9°C/W TJmax = 125°C Figure 8-38. Safe Operating Area VIN = 3.3-V TPSM82866AA0PRCFR Ambient Temperature (°C) Output Current (A) 75 80 85 90 95 100 105 110 115 120 1.5 2.5 3.5 4.5 5.5 6.5 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V RθJA = 29.9°C/W TJmax = 125°C Figure 8-39. Safe Operating Area VIN = 5.0-V TPSM82866AA0PRCFR Ambient Temperature (°C) Output Current (A) 75 80 85 90 95 100 105 110 115 120 1.5 2.5 3.5 4.5 5.5 6.5 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V RθJA = 25.4°C/W TJmax = 125°C Figure 8-40. Safe Operating Area VIN = 3.3-V TPSM82866AA0SRDJR Ambient Temperature (°C) Output Current (A) 75 80 85 90 95 100 105 110 115 120 1.5 2.5 3.5 4.5 5.5 6.5 80 120100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V RθJA = 25.4°C/W TJmax = 125°C Figure 8-41. Safe Operating Area VIN = 5.0-V TPSM82866AA0SRDJR Ambient Temperature (°C) Output Current (A) 75 80 85 90 95 100 105 110 115 120 1.5 2.5 3.5 4.5 5.5 6.5 80 120100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V RθJA = 25.9°C/W TJmax = 125°C Figure 8-42. Safe Operating Area VIN = 3.3-V TPSM82866AA0HRDMR Ambient Temperature (°C) Output Current (A) 75 80 85 90 95 100 105 110 115 120 1.5 2.5 3.5 4.5 5.5 6.5 80 120100 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V RθJA = 25.9°C/W TJmax = 125°C Figure 8-43. Safe Operating Area VIN = 5.0-V TPSM82866AA0HRDMR TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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8.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. The average input current of the TPSM8286xA is calculated as: (6) Make sure that the input power supply has a sufficient current rating for the application. The power supply must avoid a fast ramp down. The falling ramp speed must be slower than 10 mV/ μs if the input voltage drops below VUVLO.

8.4 Layout

8.4.1 Layout Guidelines

A proper layout is critical for the operation of any switched mode power supply, especially at high switching frequencies. Therefore, the PCB layout of the TPSM8286xA demands careful attention to make sure of best performance. A poor layout can lead to issues like the following:

• Bad line and load regulation
• Instability
• Increased EMI radiation
• Noise sensitivity Refer to the Five Steps to a Great PCB Layout for a Step-Down Converter Technical Brief for a detailed discussion of general best practices. The following are specific recommendations for the TPSM8286xA:
• Place the input capacitor as close as possible to the VIN and PGND pins of the device. This placement is the most critical component placement. Route the input capacitor directly to the VIN and PGND pins avoiding vias.
• Place the output capacitor close to the VOUT and PGND pins and route directly avoiding vias.
• Place the FB resistors R1 and R2 close to the FB and AGND pins and place R4 close to the VSET/MODE pin to minimize noise pickup.
• The sense traces connected to the VOS pin is a signal trace. Take special care to avoid noise being induced. Keep the trace away from SW.
• To improve thermal performance, use GND vias under the exposed thermal pad. Directly connect the AGND and PGND pins to the exposed thermal pad with copper on the top PCB layer.
• Refer to Figure 8-44 and Figure 8-45 for an example of component placement, routing, and thermal design.
• The recommended land pattern for the TPSM8286xA is shown at the end of this data sheet. For best manufacturing results, create the pads as solder mask defined (SMD) when some pins (such as VIN, VOUT, and PGND) are connected to large copper planes. Using SMD pads keeps each pad the same size and avoids solder pulling the device during reflow. www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPSM82864A TPSM82866A

8.4.2 Layout Examples

Figure 8-44. Layout Example RCF package VIN GND VOUT GND FB VOS VOUT VOUT VOUT VOUT PGND PGND PGND PG VSET/ MODE P G N D P G N D A G N D P G N D P G N D P G N D P G N D S WE N V IN V IN To tal Solution Size 35 m m ² Figure 8-45. Layout Example RDJ and RDM package TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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8.4.2.1 Thermal Considerations

The TPSM8286xA power module temperature must be kept less than the maximum rating of 125°C. The following are three basic approaches for enhancing thermal performance:

• Improve the power dissipation capability of the PCB design.
• Improve the thermal coupling of the component to the PCB.
• Introduce airflow into the system. To estimate the approximate module temperature of the TPSM8286xA, apply the typical efficiency stated in this data sheet to the desired application condition to compute the power dissipation of the module. Then, calculate the module temperature rise by multiplying the power dissipation by the thermal resistance. Using this method to compute the maximum device temperature, the Safe Operating Area (SOA) graphs demonstrate the required derating in maximum output current at high ambient temperatures. For more details on how to use the thermal parameters in real applications, see the Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report and Semiconductor and IC Package Thermal Metrics Application Report. www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPSM82864A TPSM82866A

9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Benefits of a Resistor-to-Digital Converter in Ultra-Low Power Supplies White Paper
• Texas Instruments, Design Considerations for a Resistive Feedback Divider in a DC/DC Converter Technical Brief
• Texas Instruments, Simplify Low EMI Design With Power Modules White Paper

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

MagPack™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (June 2024) to Revision D (November 2024) Page Changes from Revision B (November 2022) to Revision C (June 2024) Page

• Added TPSM82864AA0PRCFR (preview), TPSM82864BA0PRCFR (preview), TPSM82866AA0PRCFR

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPSM82864A TPSM82866A

www.ti.com QFN-FCMOD - 2 mm max heightPLASTIC QUAD FLAT PACK- NO LEADRCF0015AA 0.08CSEATING PLANE PIN 1 INDEX AREA C B 2.42.2 3.12.9 1214 SYMM 10X 0.60.4PIN1 ID 6X 0.5 SYMM 8X (0.12) 18X (0.15) 4X 1 4X 0.75 0.60.50.30.215 8X (0.05) (0.12) TYP TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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www.ti.com QFN-FCMOD - 2 mm max heightRCF0015APLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 25X 0.05 MAXALL AROUND0.05 MINALL AROUNDMETALSOLDER MASKOPENINGEXPOSED METALSOLDER MASKOPENINGMETAL UNDERSOLDER MASKEXPOSEDMETALNON- SOLDER MASKDEFINEDSOLDER MASKDEFINED 18X (0.25) 10X (0.7) SYMM 5 8 (R0.05) TYP 4X (0.72)4X(0.825) (0.75)(2)SYMM 4X (0.5)4X (0.4) 1214 (0.55)(0.25)15 www.ti.com TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPSM82864A TPSM82866A

www.ti.com QFN-FCMOD - 2 mm max heightRCF0015APLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCILSCALE: 25X NOTES: (continued)4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations. 18X (0.25) 10X (0.7) SYMM 5 8 (R0.05) TYP 4X (0.72)4X(0.825) (0.75)(2)SYMM 4X (0.5)4X (0.4) 1214 (0.55)(0.25)15 TPSM82864A, TPSM82866A SLUSEF1D – SEPTEMBER 2021 – REVISED NOVEMBER 2024 www.ti.com

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Product Folder Links: TPSM82864A TPSM82866A

www.ti.com 14-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) M8864AA0SRDJRG4 Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM864AA0S M8864AA0SRDJRG4.A Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM864AA0S M8866AA0HRDMRG4 Active Production B0QFN (RDM) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM866AA0H M8866AA0HRDMRG4.A Active Production B0QFN (RDM) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM866AA0H M8866AA0SRDJRG4 Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM866AA0S M8866AA0SRDJRG4.A Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM866AA0S TPSM82864AA0HRDMR Active Production B0QFN (RDM) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM864AA0H TPSM82864AA0HRDMR.A Active Production B0QFN (RDM) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM864AA0H TPSM82864AA0SRDJR Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM864AA0S TPSM82864AA0SRDJR.A Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM864AA0S TPSM82864AA0SRDJR.B Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R - Call TI Call TI -40 to 125 TPSM82866AA0HRDMR Active Production B0QFN (RDM) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM866AA0H TPSM82866AA0HRDMR.A Active Production B0QFN (RDM) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM866AA0H TPSM82866AA0PRCFR Active Production QFN-FCMOD (RCF) | 15 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 T8866A TPSM82866AA0PRCFR.A Active Production QFN-FCMOD (RCF) | 15 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 T8866A TPSM82866AA0PRCFR.B Active Production QFN-FCMOD (RCF) | 15 2500 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 T8866A TPSM82866AA0SRDJR Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM866AA0S TPSM82866AA0SRDJR.A Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 TM866AA0S TPSM82866AA0SRDJR.B Active Production B0QFN (RDJ) | 23 3000 | LARGE T&R - Call TI Call TI -40 to 125 XPSM82866AA0PRCFR Active Preproduction QFN-FCMOD (RCF) | 15 2500 | LARGE T&R - -40 to 125 XPSM82866AA0PRCFR.A Active Preproduction QFN-FCMOD (RCF) | 15 2500 | LARGE T&R - Call TI Call TI -40 to 125 (1) Status: For more details on status, see our product life cycle. Addendum-Page 1

www.ti.com 14-Oct-2025 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPSM82866AA0PRCFR QFN- FCMOD Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) M8864AA0SRDJRG4 B0QFN RDJ 23 3000 336.0 336.0 48.0 M8866AA0HRDMRG4 B0QFN RDM 23 3000 336.0 336.0 48.0 M8866AA0SRDJRG4 B0QFN RDJ 23 3000 336.0 336.0 48.0 TPSM82864AA0HRDMR B0QFN RDM 23 3000 336.0 336.0 48.0 TPSM82864AA0SRDJR B0QFN RDJ 23 3000 336.0 336.0 48.0 TPSM82866AA0HRDMR B0QFN RDM 23 3000 336.0 336.0 48.0 TPSM82866AA0PRCFR QFN-FCMOD RCF 15 2500 367.0 367.0 35.0 TPSM82866AA0SRDJR B0QFN RDJ 23 3000 336.0 336.0 48.0 Pack Materials-Page 2

www.ti.com QFN-FCMOD - 2 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RCF0015A A 0.08 C SEATING PLANE PIN 1 INDEX AREA C B NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 2.4 2.2 3.1 2.9 1.9 0.05 (0.2) TYP 4X 0.72 0.52 4X 0.62 0.42 10X 0.35 0.15

0.1 C A B

0.05 C SYMM 10X 0.6 0.4 PIN1 ID 6X 0.5 SYMM 8X (0.12) 18X (0.15) 4X 1 4X 0.75 0.6 0.5 0.3 0.2 8X (0.05) (0.12) TYP

www.ti.com QFN-FCMOD - 2 mm max heightRCF0015A PLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 25X NOTES: (continued) 3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK DETAILS

0.05 MAX

0.05 MIN

18X (0.25) 10X (0.7) SYMM 5 8 (R0.05) TYP 6X (0.5) 4X (1) (2.7) 4X (0.72) (0.825) (0.75) (2) SYMM 4X (0.5) 4X (0.4) (0.55) (0.25)

www.ti.com QFN-FCMOD - 2 mm max heightRCF0015A PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 25X NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 18X (0.25) 10X (0.7) SYMM 5 8 (R0.05) TYP 6X (0.5) 4X (1) (2.7) 4X (0.72) (0.825) (0.75) (2) SYMM 4X (0.5) 4X (0.4) (0.55) (0.25)

www.ti.com B0QFN - 1.45 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RDJ0023A A 0.08 C 4.1 3.9 1.45 1.35 SEATING PLANE PIN 1 INDEX AREA C (0.20) TYP 0.01 0.00 PIN 1 ID B 3.6 3.4 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. 2X 2.5 2X 3 18X 0.3 0.2

0.05 C 1

8X 0.55 0.45 18X 0.6 0.4 26X (0.15) 1.6±0.1 0.05 C 1.8±0.1 7 12 PKG SYMM 22X 0.5 2X (0.3) 2X (0.45) 2X (0.3) 2X (0.9) 8X (0.125) (0.10) TYP 8X (0.05) (0.125) TYP

www.ti.com B0QFN - 1.45 mm max heightRDJ0023A PLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK DETAILS NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 2X (3) 26X (0.25) (3.7) 22X (0.5) 2X (2.5) 18X (0.7) (Ø0.2) TYP (1.8) (1.6) (3.2) SYMM PKG (R0.05) TYP (0.55) (0.95) 8X (0.5) 2X (0.3) (0.35)

www.ti.com B0QFN - 1.45 mm max heightRDJ0023A PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD: 83% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 2X (3) 26X (0.25) (3.7) 22X (0.5) 2X (2.5) 18X (0.7) (1.63) (1.47) (3.2) SYMM PKG (R0.05) TYP 8X (0.5) (0.3)

www.ti.com B0QFN - 1.85 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RDM0023A A 0.08 C 4.1 3.9 1.85 1.75 SEATING PLANE PIN 1 INDEX AREA C (0.20) TYP 0.01 0.00 PIN 1 ID B 3.6 3.4 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. 2X 2.5 2X 3 18X 0.3 0.2 8X 0.55 0.45 18X 0.6 0.4 26X (0.15) 1.6±0.1 0.05 C 1.8±0.1 7 12 PKG SYMM 22X 0.5 2X (0.3) 2X (0.45) 2X (0.3) 2X (0.9) 8X (0.125) (0.10) TYP 8X (0.05) (0.125) TYP

www.ti.com B0QFN - 1.85 mm max heightRDM0023A PLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK DETAILS NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 2X (3) 26X (0.25) (3.7) 22X (0.5) 2X (2.5) 18X (0.7) (Ø0.2) TYP (1.8) (1.6) (3.2) SYMM PKG (R0.05) TYP (0.55) (0.95) 8X (0.5) 2X (0.3) (0.35)

www.ti.com B0QFN - 1.85 mm max heightRDM0023A PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL EXPOSED PAD: 83% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 2X (3) 26X (0.25) (3.7) 22X (0.5) 2X (2.5) 18X (0.7) (1.63) (1.47) (3.2) SYMM PKG (R0.05) TYP 8X (0.5) (0.3)

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