TPSM82810 TI1 | Alldatasheet
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Technical content
ADVANCE□INFORMATION Output Current (A) Efficiency (%) 100 100P 1m 10m 100m 1 4 D002 VIN = 4.0 V VIN = 5.0 V VIN = 6.0 V V
2.75 V - 6 V
C 22 PF IN C 47 PF OUT VOUT RCF CSS Copyright © 2019, Texas Instruments Incorporated CFF MODE/SYNC VOUT FB VIN EN GND PG SS/TR COMP/FSET TPSM82810 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPSM82810, TPSM82813 SLUSDN6 –SEPTEMBER 2019 TPSM8281x2.75-Vto6-VAdjustable-FrequencyStep-DownConverterwithIntegrated Inductor
1 Features
1• Input voltage range: 2.75 V to 6 V
- 3-A and 4-A versions
- Quiescent current 15-µA typical
- Output voltage from 0.6 V to 5.5 V
- Output voltage accuracy ±1% (PWM operation)
- Adjustable soft-start
- Forced PWM or PWM/PFM operation
- Adjustable switching frequency of
1.8 MHz to 4 MHz
- Precise ENABLE input allows – User-defined undervoltage lockout – Exact sequencing
- 100% duty cycle mode
- Active output discharge
- Spread spectrum clocking - optional
- Power good output with window comparator
2 Applications
- Macro BTS and cloud RAN
- Microwave transmission system and backhaul
- Instrumentation
- Patient monitoring and diagnostics
- Optical networking
3 Description
TPSM8281x is a family of pin-to-pin 3-A and 4-A high efficiency and easy to use synchronous step-down DC/DC converters. They are based on a peak current mode control topology. They are designed for Telecommunication, Test and Measurement and Medical applications with high power density and ease of use requirements. Low resistive switches allow up to 4-A continuous output current at high ambient temperature. The switching frequency is externally adjustable from 1.8 MHz to 4 MHz and can also be synchronized to an external clock in the same frequency range. In PWM/PFM mode, TPSM8281x automatically enters Power Save Mode at light loads to maintain high efficiency across the whole load range. TPSM8281x provides a 1% output voltage accuracy in PWM mode which helps design a power supply with high output voltage accuracy. The SS/TR pin allows setting the start-up time or forming tracking of the output voltage to an external source. This allows external sequencing of different supply rails and limiting the inrush current during start-up. The TPSM8281x is available as an adjustable version, packaged in a 3-mm x 4-mm µSil module with integrated inductor. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPSM82810 µSil 3-mm x 4-mm TPSM82813 µSil 3-mm x 4-mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Schematic Efficiency vs Output Current; VOUT = 3.3 V; PWM/PFM; fS = 2.25 MHz
ADVANCE□INFORMATION TPSM82810, TPSM82813 SLUSDN6 –SEPTEMBER 2019 www.ti.com Product Folder Links: TPSM82810 TPSM82813 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents
13.4 Receiving Notification of Documentation Updates 32
14 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES September 2019 * Advance Information release.
ADVANCE□INFORMATION TPSM82810, TPSM82813 www.ti.com SLUSDN6 –SEPTEMBER 2019 Product Folder Links: TPSM82810 TPSM82813 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated
5 Device Comparison Table
DEVICE NUMBER FEATURES OUTPUT VOLTAGE TPSM82810SIL 4 A output current spread spectrum clocking = OFF adjustable TPSM82810SSIL 4 A output current spread spectrum clocking = ON adjustable TPSM82813SIL 3 A output current spread spectrum clocking = OFF adjustable TPSM82813SSIL 3 A output current spread spectrum clocking = ON adjustable
ADVANCE□INFORMATION TOP VIEW BOTTOM VIEW VIN GNDGND VOUT ENPG MODE /SYNC FB SS/TR COMP /FSET GND VIN VIN GND VIN GND GND VOUTEN PG MODE /SYNC FB SS/TR COMP /FSET GND VINVIN GND 1 2 3 4 5 678910 11 12 1314 12345 6 7 8 9 10 1112 13 14 TPSM82810, TPSM82813 SLUSDN6 –SEPTEMBER 2019 www.ti.com Product Folder Links: TPSM82810 TPSM82813 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
6 Pin Configuration and Functions
µSil Package
14 Pin (µSil)
NAME NO. EN 2 I This is the enable pin of the device. Connect to logic low to disable the device. Pull high to enable the device. Do not leave this pin unconnected. FB 7 I Voltage feedback input, connect the resistive output voltage divider to this pin. GND 6, 10, 13, 14 Ground pin MODE/SYNC 4 I The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high, the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can also be used to synchronize the device to an external frequency. See the electrical characteristics for the detailed specification for the digital signal applied to this pin for external synchronization. COMP/FSET 9 I Device compensation and frequency set input. A resistor from this pin to GND defines the compensation of the control loop as well as the switching frequency if not externally synchronized. If the pin is tied to GND or VIN, the switching frequency is set to 2.25MHz. Do not leave this pin unconnected. PG 3 O Open drain power good output. Low impedance when not "power good", high impedance when "power good". This pin can be left open or tied to GND if not used. SS/TR 8 I Soft-Start / Tracking pin. A capacitor connected from this pin to GND defines the rise time for the internal reference voltage. The pin can also be used as an input for tracking and sequencing - see the application section in this data sheet. VOUT 5 Output voltage pin. This pin is internally connected to the integrated inductor. VIN 1, 11, 12 Power supply input. Connect the input capacitor as close as possible between pin VIN and GND. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Pin voltage range(1) VIN -0.3 6.5 V VOUT -0.3 6.5 V FB -0.3 4 V PG, SS/TR, COMP/FSET -0.3 VIN+0.3 V Pin voltage range(1) EN, MODE/SYNC -0.3 6.5 V Storage temperature, Tstg -40 125 °C
ADVANCE□INFORMATION TPSM82810, TPSM82813 www.ti.com SLUSDN6 –SEPTEMBER 2019 Product Folder Links: TPSM82810 TPSM82813 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22- V C101(2) ±500 (1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.
7.3 Recommended Operating Conditions
VIN Supply voltage range 2.75 6 V VOUT Output voltage range 0.6 5.5 V COUT Effective output capacitance(1) 27 47 470 µF CIN Effective input capacitance(1) 5 10 µF RFSET 4.5 100 kΩ TJ Operating junction temperature -40 150 °C Tind Operating inductor temperature -40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) TPS82810 UNITµSil
14 PINS
RθJA Junction-to-ambient thermal resistance 67.5 °C/W ψJB Junction-to-board characterization parameter 19.2 °C/W
7.5 Electrical Characteristics
over operating junction temperature (TJ = -40 °C to +125 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25 °C. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching, TJ= 125 °C 21 µA IQ Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching 15 30 µA ISD Shutdown Current EN = 0 V, at TJ= 125 °C 18 µA ISD Shutdown Current EN = 0 V, Nominal value at TJ= 25 °C, Max value at TJ= 150 °C 1.5 26 µA VUVLO Undervoltage Lockout Threshold Rising Input Voltage 2.5 2.6 2.75 V Falling Input Voltage 2.25 2.5 2.6 V TSD Thermal Shutdown Temperature Rising Junction Temperature 170 Thermal Shutdown Hysteresis 15 CONTROL (EN, SS/TR, PG, MODE) VIH High Level Input Voltage for MODE Pin 1.1 V VIL Low Level Input Voltage for MODE Pin 0.3 V fSYNC Frequency Range on MODE Pin for Synchronization requires a resistor from COMP/FSET to GND, see application section 1.8 4 MHz
ADVANCE□INFORMATION TPSM82810, TPSM82813 SLUSDN6 –SEPTEMBER 2019 www.ti.com Product Folder Links: TPSM82810 TPSM82813 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating junction temperature (TJ = -40 °C to +125 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25 °C. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Duty Cycle of Synchronization Signal at MODE Pin 40% 50% 60% Time to Lock to External Frequency 50 µs VIH Input Threshold Voltage for EN pin; Rising Edge 1.06 1.1 1.15 V VIL Input Threshold Voltage for EN pin; Falling Edge 0.96 1.0 1.05 V ILKG Input Leakage Current for EN, MODE/SYNC VIH = VIN or VIL= GND 150 nA Resistance from COMP/FSET to GND for Logic Low internal frequency setting with f = 2.25 MHz 0 2.5 kΩ voltage on COMP/FSET for logic high internal frequency setting with f = 2.25 MHz VIN V VTH_PG UVP Power Good Threshold Voltage; dc Level Rising (%VFB) 92% 95% 98% UVP Power Good Threshold Voltage; dc Level Falling (%VFB) 87% 90% 93% OVP Power Good Threshold; dc Level Rising (%VFB) 107% 110% 113% OVP Power Good Threshold; dc Level Falling (%VFB) 104% 107% 111% Power Good De-glitch Time for a high level to low level transition on power good 40 µs VOL_PG Power Good Output Low Voltage IPG = 2 mA 0.07 0.3 V ILKG_PG Input Leakage Current (PG) VPG = 5 V 100 nA ISS/TR SS/TR Pin Source Current 2.1 2.5 2.8 µA Tracking Gain VFB / VSS/TR for nominal VFB = 0.6 V 1 Tracking Offset feedback voltage with VSS/TR = 0 V for nominal VFB = 0.6 V 17 mV POWER SWITCH RDS(ON) High-Side MOSFET ON- Resistance VIN ≥ 5 V 37 60 mΩ RDS(ON) Low-Side MOSFET ON- Resistance VIN ≥ 5 V 15 35 mΩ High-Side MOSFET leakage current TJ = 85 °C; VIN = 6 V; V(SW) = 0 V 1.5 µA High-Side MOSFET leakage current VIN = 6 V; V(SW) = 0 Vhigh-side MOSFET leakage current at TJ = 85°C 30 µA Low-Side MOSFET leakage current TJ = 85 °C; V(SW) = 6 V 3 µA Low-Side MOSFET leakage current V(SW) = 6 Vlow-side MOSFET leakage current at TJ = 85°C 55 µA SW leakage V(SW) = 0.6 V; current into SW pin -0.025 30 µA RDP Dropout resistance 100% mode. VIN = 3.3, TJ = 85°C 50 80 mΩ ILIMH High-Side MOSFET Current Limit dc value, for TPSM82810; VIN = 3 V to 6 V 4.8 5.6 6.55 A ILIMH High-Side MOSFET Current Limit dc value, for TPSM82813; VIN = 3V to 6 V 3.9 4.5 5.25 A ILIMNEG Negative Current Limit dc value -1.8 A fS PWM Switching Frequency Range see the fset function about setting the switching frequency 1.8 2.25 4 MHz fS PWM Switching Frequency with COMP/FSET tied to VIN or GND 2.025 2.25 2.475 MHz PWM Switching Frequency Tolerance using a resistor from COMP/FSET to GND, fs = 1.8 MHz to < 3 MHz -19% 18%
7.6 Typical Characteristics
Figure 1. Rds(on) of High Side Switch Figure 2. Rds(on) of Low Side Switch
8 Parameter Measurement Information
8.1 Schematic
Figure 3. Measurement Setup for TPSM82810 and TPSM82813 Table 1. List of Components
ADVANCE□INFORMATION GND FB VOUTVIN EN Oscillator Gate Drive and Control Device Control PG Thermal Shutdown Bias Regulator gm Ipeak Bandgap SS/TR COMP/FSET MODE Izero TPSM82810, TPSM82813 www.ti.com SLUSDN6 –SEPTEMBER 2019 Product Folder Links: TPSM82810 TPSM82813 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
The TPSM8281x synchronous switch mode DC/DC converters modules are based on a peak current mode control topology. The control loop is internally compensated. In order to optimize the bandwidth of the control loop to the wide range of output capacitance that can be used with TPSM8281x, one of 3 internal compensation settings can be selected. See COMP/FSET. The compensation setting is selected either by a resistor from COMP/FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable operation with small external components and low ESR ceramic output capacitors. The device can be operated without feed forward capacitor on the output voltage divider, however using a typically 10 pF feed forward capacitor improves transient response. The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN or in a range of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no need for additional passive components. External synchronization is only possible if a resistor from COMP/FSET to GND is used. If COMP/FSET is directly tied to GND or VIN, TPSM8281x can not be synchronized externally. An internal PLL allows to change from internal clock to external clock during operation. The synchronization to the external clock is done on a falling edge of the clock applied at MODE to the rising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is used to generate the synchronization signal for a second converter. When the MODE pin is set to a logic low level, the device operates in power save mode (PFM) at low output current and automatically transfers to fixed frequency PWM mode at higher output current. In PFM mode, the switching frequency decreases linearly based on the load to sustain high efficiency down to very low output current.
9.2 Functional Block Diagram
ADVANCE□INFORMATION 60( ) ( ) CF S MHz kR k f MHz /c215 /c87/c87 /c61 18( ) ( ) CF S MHz kR k f MHz /c215 /c87/c87 /c61 TPSM82810, TPSM82813 SLUSDN6 –SEPTEMBER 2019 www.ti.com Product Folder Links: TPSM82810 TPSM82813 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 Precise Enable
The voltage applied at the Enable pin of the TPSM8281x is compared to a fixed threshold of 1.1 V for a rising voltage. This allows to drive the pin by a slowly changing voltage and enables the use of an external RC network to achieve a power-up delay. The Precise Enable input provides a user programmable undervoltage lockout by adding a resistor divider to the input of the Enable pin. The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The TPSM8281x starts operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown current of typically 1 μA. In this mode, the internal high side and low side MOSFETs are turned off and the entire internal control circuitry is switched off.
9.3.2 COMP/FSET
This pin allows to set two different parameters independently:
- internal compensation settings for the control loop (3 settings available)
- the switching frequency in PWM mode from 1.8 MHz to 4 MHz A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change in compensation allows to adapt the device to different values of output capacitance. The resistor should be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting is sampled at start-up of the converter, so a change in the resistor during operation only has an effect on the switching frequency but not on the compensation. In order to save external components, the pin can also be directly tied to VIN or GND to set a pre-defined switching frequency / compensation. Do not leave the pin floating. The switching frequency has to be selected based on the input voltage and the output voltage to meet the specifications for the minimum on-time and minimum off-time. Example: VIN = 5 V, VOUT = 1 V --> duty cycle (DC) = 1 V / 5 V = 0.2
- with ton = DC * T --> ton,min = 1/fs,max * DC
- --> fs,max = 1/ton,min * DC = 1/0.075 µs * 0.2 = 2.67 MHz The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be increased from the minimum value as given in Table 2 up to the maximum of 470 µF in all of the 3 compensation ranges. If the capacitance of an output changes during operation, e.g. when load switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the minimum capacitance on the output. With large output capacitance, the compensation should be done based on that large capacitance to get the best load transient response. Compensating for large output capacitance but placing less capacitance on the output may lead to instability. The switching frequency for the different compensation setting is determined by the following equations. For compensation (comp) setting 1: Space (1) For compensation (comp) setting 2: Space (2) Space For compensation (comp) setting 3:
Table 2. Switching Frequency and Compensation for TPSM82810 (4 A) and TPSM82813 (3 A) Refer to Output Capacitor for further details on the output capacitance required depending on the output voltage. A too high resistor value for RCF is decoded as "tied to VIN", a value below the lowest range as "tied to GND". capacitance is distributed, a lower compensation setting may be required.
9.3.3 MODE / SYNC
COMP/FSET to GND but the pin is pulled high or low, external synchronization is not possible.
9.3.4 Spread Spectrum Clocking (SSC); optional
typically between the nominal switching frequency and up to 288kHz above the nominal switching frequency.
9.3.5 Undervoltage Lockout (UVLO)
input voltage trips below the threshold for a falling supply voltage.
9.3.6 Power Good Output (PG)
defined in the electrical characteristics, the output is high impedance.
Table 3. PG Status
9.3.7 Thermal Shutdown
delay, the device will not detect a too high junction temperature.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
operate at, taking the minimum on-time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
output current becomes smaller than half of the inductor´s ripple current. In power save mode the switching frequency decreases linearly with the load current maintaining high efficiency.
9.4.4 Current Limit and Short Circuit Protection
ADVANCE□INFORMATION ( ) 50 IN OUT peak typ LIMH V VI I ns L /c45/c61 /c43 /c215 TPSM82810, TPSM82813 www.ti.com SLUSDN6 –SEPTEMBER 2019 Product Folder Links: TPSM82810 TPSM82813 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Device Functional Modes (continued) L is the effective inductance at the peak current (typical 470nH) VL is the voltage across the inductor (VIN - VOUT) and tPD is the internal propagation delay of typically 50 ns. The current limit can exceed static values, especially if the input voltage is high and very small inductances are used. The dynamic high side switch peak current can be calculated as follows: (5)
9.4.5 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge feature is only active once TPSM8281x has been enabled at least once since the supply voltage was applied. The discharge function is enabled as soon as the device is disabled, in thermal shutdown or in undervoltage lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output discharge is not activated during a current limit or fold-back current limit event.
9.4.6 Soft Start / Tracking (SS/TR)
The internal Soft-Start circuitry controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a delay of about 200 μs then the internal reference and hence VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. Leaving the SS/TR pin un-connected provides the fastest startup ramp with 150 µs typically. A capacitor connected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start until it reaches the reference voltage of 0.6 V. The capacitance required to set a certain ramp-time (tramp) therefore is: (6) If the device is set to shutdown (EN = GND), undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new startup sequence. A voltage applied at SS/TR can be used to track a master voltage. The output voltage follows this voltage in both directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load current. The SS/TR pin must not be connected to the SS/TR pin of other devices. An external voltage applied on SS/TR is internally clamped to the feedback voltage (0.6 V). It is recommended to set the target for the external voltage on SS/TR slightly above the feedback voltage. Given the tolerances of the resistor divider R5 and R6 on SS/TR, this makes sure the device "switches" to the internal reference voltage when the power-up sequencing is finished. See Figure 65.
ADVANCE□INFORMATION 1 2 1 OUT FB VR R V /c215 /c230 /c246/c61 /c45 /c231 /c247 /c232 /c248 TPSM82810, TPSM82813 SLUSDN6 –SEPTEMBER 2019 www.ti.com Product Folder Links: TPSM82810 TPSM82813 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPSM8281x is adjustable. It can be programmed for output voltages from 0.6 V to 5.5 V, using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of the output voltage is set by the selection of the resistor divider from Equation 7. It is recommended to choose resistor values which allow a current of at least 2 µA, meaning the value of R2 should not exceed 400 kΩ. Lower resistor values are recommended for highest accuracy and most robust design. (7)
10.1.2 External Component Selection
10.1.3 Capacitor Selection
10.1.3.1 Input Capacitor
For most applications, 22 µF nominal is sufficient and is recommended. The input capacitor buffers the input voltage for transient events and also decouples the converter from the supply. A low ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and should be placed between VIN and GND as close as possible to those pins.
10.1.3.2 Output Capacitor
The architecture of the TPSM8281x allows the use of tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to use dielectric X7R, X7T or equivalent. Using a higher value has advantages like smaller voltage ripple and a tighter DC output accuracy in power save mode. By changing the device compensation with a resistor from COMP/FSET to GND, the device can be compensated in 3 steps based on the minimum capacitance used on the output. The maximum capacitance is 470 µF in any of the compensation settings. The minimum capacitance required on the output depends on the compensation setting as well as on the current rating of the device. TPSM82810 and TPSM82813 require a minimum output capacitance of 27 µF while the lower current versions TPSM82812 and TPSM82811 require 15 µF at minimum. The required output capacitance also changes with the output voltage. For output voltages below 1 V, the minimum increases linearly from 32 µF at 1 V to 53 µF at 0.6 V for TPSM8281x with the compensation setting for smallest output capacitance. Other compensation ranges are equivalent. See Table 2 for details.
10.2 Typical Application
Figure 4. Typical Application
10.2.1 Design Requirements
10.2.2 Detailed Design Procedure
Table 4. Setting the Output Voltage
10.2.3 Application Curves
Figure 5. Efficiency vs Output Current Figure 6. Efficiency vs Output Current Figure 7. Efficiency vs Output Current Figure 8. Efficiency vs Output Current Figure 9. Efficiency vs Output Current Figure 10. Efficiency vs Output Current
10.3 System Examples
10.3.1 Voltage Tracking
voltage according to the 0.6 V feedback voltage. the output voltage close to 0 V. Figure 65. Schematic for Output Voltage Tracking
Figure 66. Scope Plot for Output Voltage Tracking
10.3.2 Synchronizing to an external Clock
close to each other. This ensures a smooth transition from internal to external frequency and vice versa. Figure 67. Schematic using External Synchronization
Figure 68. Switching from External Syncronization to Figure 69. Switching from External Synchronizaion to
10.4 Do's and Don'ts (Recommended)
11 Power Supply Recommendations
12 Layout
12.1 Layout Guidelines
and accuracy weaknesses, increased EMI radiation and noise sensitivity. ground connections. The input capacitor should be placed as close as possible between the VIN and GND pin. and R2, should be kept close to the IC and connect directly to those pins and the system ground plane.
12.2 Layout Example
Figure 70. Example Layout
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
- TPSM82810EVM-015 Evaluation Module, SLVUBG0
13.3 Related Links
resources, tools and software, and quick access to order now. Table 5. Related Links
13.4 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
13.5 Community Resources
from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.
13.6 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.8 Glossary
This glossary lists and explains terms, acronyms, and definitions.
ADVANCE□INFORMATION TPSM82810, TPSM82813 www.ti.com SLUSDN6 –SEPTEMBER 2019 Product Folder Links: TPSM82810 TPSM82813 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C 2X 1.3 4X 0.65 10X (0.05) 6X 0.27 0.23 6X 0.57 0.53
2.4 MAX
4X 0.8 0.1 2X 1.8 4X 0.3 0.1 2X 0.9 2X 3.175 4X 0.845 0.805 4X 1.22 1.18 2X 1.15 B 3 A (3.2) (2.5) 4X (0.075) MicroSiP - 2.4 mm max heightSIL0014B MICRO SYSTEM IN PACKAGE 4225112/A 07/2019 AREA PIN 1 INDEX NOTE 3 PICK AREA 0.08 C
0.1 C A B
0.05 C 1 10 SYMM SYMM 5 6 12 13 (OPTIONAL) PIN 1 ID MicroSiP is a trademark of Texas Instruments TM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Pick and place nozzle 1.3 mm or smaller recommended. 4. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance. 0.05 C SCALE 3.000 ADVANCE□INFORMATION TPSM82810, TPSM82813 SLUSDN6 –SEPTEMBER 2019 www.ti.com Product Folder Links: TPSM82810 TPSM82813 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
www.ti.com EXAMPLE BOARD LAYOUT 6X (0.75) 4X (1)
0.05 MIN
0.05 MAX
(0.3) (3.25) 6X (0.25) (2.65) 4X (0.65) 2X (2) 2X (3.35) 4X (0.8) 4X (0.3) 4X (0.575) 4X (0.45) (0.05) TYP (R0.05) TYP 4X (1.4) (0.3) MicroSiP - 2.4 mm max heightSIL0014B MICRO SYSTEM IN PACKAGE 4225112/A 07/2019 PKG PKG SCALE:20X LAND PATTERN EXAMPLE 12 13 METAL UNDER SOLDER MASK TYP SOLDER MASK OPENING TYP SEE DETAILS COPPER KEEP-OUT AREA NOTES: (continued) TM 5. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). NON SOLDER MASK DEFINED SOLDER MASK DEFINED PADS 1, 5, 6, 10 AND 11 - 14 METAL UNDER SOLDER MASK SOLDER MASK OPENING NOT TO SCALE SOLDER MASK DETAILS SOLDER MASK OPENING METAL ADVANCE□INFORMATION TPSM82810, TPSM82813 www.ti.com SLUSDN6 –SEPTEMBER 2019 Product Folder Links: TPSM82810 TPSM82813 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated
www.ti.com EXAMPLE STENCIL DESIGN (R0.1) TYP 6X (0.25) 6X (0.75) 6X (0.65) (2.65) 4X (0.8) 2X (2) 2X (3.35) 4X (0.3) 4X (0.575) 4X (0.45) 4X (1) 4X (1.4) MicroSiP - 2.4 mm max heightSIL0014B MICRO SYSTEM IN PACKAGE 4225112/A 07/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. TM SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:25X 5 6 ADVANCE□INFORMATION TPSM82810, TPSM82813 SLUSDN6 –SEPTEMBER 2019 www.ti.com Product Folder Links: TPSM82810 TPSM82813 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated
www.ti.com 3-Oct-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples XPSM82810SILT ACTIVE uSiP SIL 14 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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