XPS82480MOPT

TPSM82480 TI1 | Alldatasheet

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ADVANCE□INFORMATION COUT VOUT/6A RS SS/TR AGND PGND VIN1 VIN2 2.4 to 5.5V 10µF 10µF TPSM82480 3.3nF MODE VSEL EN PG TG VOUT FB Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPSM82480 SLVSDT1 –JULY 2017 TPSM824805.5-VInput,6-A,Step-DownConverterwithIntegratedInductor

1 Features

1• Ultra Small 7.9 x 3.6 x 1.5 mm Power Module

Output Current of 6 A
Input Voltage Range 2.4 to 5.5 V
Output Voltage Range 0.6 to 5.5 V
Typical Quiescent Current of 23 µA
Feedback Voltage Accuracy of ±1% (PWM Mode)
Output Voltage Select
Phase Shifted Operation
Automatic Power Save Modes
Forced PWM Mode
Adjustable Soft Start
Power Good / Thermal Good Outputs
Undervoltage Lockout
Over-current and Short-Circuit Protection
Over-temperature Protection
-40°C to 125°C Operating Junction Temperature Range

2 Applications

Low Profile Point-of-Load Supply
Solid State Drives
Ultra Portable/Tablet/Embedded PC
Optical Modules, CMOS Cameras
Wireless Modules, Network Cards

3 Description

The TPSM82480 is a synchronous step-down DC-DC converter module for low profile point-of-load power supplies. The input voltage range of 2.4 to 5.5 V enables operation from typical 3.3-V or 5-V interface supplies as well as from backup circuits dropping down as low as 2.4 V. The output current is up to 6 A continuously provided by two phases of 3 A each. These run out-of-phase, reducing pulse current noise significantly. The TPSM82480 provides automatically entered power save modes to maintain high efficiency down to very light loads. This incorporates an automatic phase adding and shedding feature using both or only one phase according to the actual load. The pulse skip mode for very light loads can be switched off by using the MODE feature. The device features a Power Good signal and an adjustable soft start. Also, the device features a Thermal Good signal to detect excessive internal temperature. The output voltage can be changed to a preselected value by VSEL pin. TPSM82480 is able to operate in 100% duty cycle mode. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPSM82480MOP QFM (24) 7.90 × 3.60 x 1.55 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space space Typical Application Schematic Efficiency vs Output Current, VIN= 12 V

11.2 Receiving Notification of Documentation Updates 24

12 Mechanical, Packaging, and Orderable

4 Revision History

July 2017 * Initial release.

ADVANCE□INFORMATION PIN1 Marker 3 4 10 9 15 1920 14 13 24 23 1 20 14 15 9 54 10 11 21 22 TOPVIEW BOTTOMVIEW TPSM82480 www.ti.com SLVSDT1 –JULY 2017 Product Folder Links: TPSM82480 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

5 Pin Configuration and Functions

NAME NO. VOUT1 1 Output Voltage Node Phase 1 (master), Must be connect with VOUT2 PGND1 2, 3, 20,21 Power Ground Phase 1 (master) VIN1 4, 24 Supply voltage Phase 1 (master) EN 5 Enable input (High=Enabled, Low = Disabled) PG 6 Power Good (open drain, requires pull-up resistor) VSEL 7 Output Voltage Select (High = VOUT2, Low=VOUT1) , VOUT1 < VOUT2 TG 8 Thermal Good (open drain, requires pull-up resistor) MODE 9 Operating mode selection (Low=Automatic PWM/PSM, High = Forced PWM) VIN2 10, 23 Supply voltage Phase 2 PGND2 11,12, 14, 22 Power Ground Phase 2 VOUT2 13 Output Voltage Node Phase 2, Must be connected with VOUT1 SS/TR 15 Soft-Start / Tracking. An external capacitor connected to this pin sets the output voltage rise time. AGND 16 Analog Ground FB 17 Output voltage feedback for the adjustable version. Connect resistive voltage divider to this pin. RS 18 Resistor Select. Connect resistor that sets the level for the second output voltage here (activated by VSEL= High) VO 19 VOUT detection (connect to VOUT, output discharge is internally connected to this pin)

6 Specifications

6.1 Absolute Maximum Ratings

Pin Voltage Range(1) VIN -0.3 6 V EN, VSEL, MODE, SS/TR, PG, TG -0.3 6 V FB, RS -0.3 3 V Power Good / Thermal Good Sink Current PG, TG 10 mA Operating Junction Temperature Range, TJ -40 150 °C Storage Temperature Range, Tstg -65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500

6.3 Recommended Operating Conditions

Supply Voltage Range, VIN 2.4 5.5 V Output Voltage Range, VOUT 0.6 5.5 V Maximum Output Current, IOUT 6 A Operating junction temperature, TJ –40 125 °C (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) TPSM82480 UNITMOP 24 PINS JEDEC with thermal vias RθJA Junction-to-ambient thermal resistance 32.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 13.6 °C/W RθJB Junction-to-board thermal resistance 11.5 °C/W ψJT Junction-to-top characterization parameter 0.53 °C/W ψJB Junction-to-board characterization parameter 11.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance - °C/W

6.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to 125°C) and VIN = 2.4 V to 5.5 V. Typical values at VIN = 3.6 V and TJ = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input Voltage Range VIN rising 2.6 5.5 V VIN falling 2.4 5.5 IQ Operating Quiescent Current EN = High, VIN ≥ 3 V, IOUT = 0 mA, device not switching, TJ = -40°C to +85°C 23 38 µA 100% Mode operation 3.5 6.5 mA ISD Shutdown Current EN = Low (≤ 0.3 V), TJ = -40°C to +85°C 0.5 18.5 µA VUVLO Undervoltage Lockout Threshold Falling Input Voltage 2.2 2.3 2.4 V Hysteresis 200 mV TSD Thermal Shutdown Temperature PWM Mode, Rising Junction Temperature 160 Thermal Shutdown Hysteresis PWM Mode 10 CONTROL (EN, VSEL, MODE, SS/TR, PG, TG) VH Input Threshold Voltage (EN, VSEL, MODE) to ensure High Level 1.2 V VL Input Threshold Voltage (EN, VSEL, MODE) to ensure Low Level 0.4 ILKG(EN) Input Leakage Current (EN) EN = VIN or GND 10 200 nA ILKG(MODE) Input Leakage Current (MODE, VSEL) 10 200 nA ISS/TR SS/TR pin source current 4.7 5.25 5.8 µA VTH(TG) Thermal Good Threshold Temperature PWM Mode 120 Thermal Good Hysteresis PWM Mode 10 VTH(PG) Power Good Threshold Voltage Rising (%VOUT) 93% 96% 99% Falling (%VOUT) 89% 92% 95% VL(PG) Output Low Threshold (PG, TG) IPG = -2 mA 0.4 V ILKG(PG) Input Leakage Current (PG) 2 700 nA ILKG(TG) Input Leakage Current (TG) 2 100 nA tSS Internal Soft-Start Time SS/TR = VIN or floating 80 µs tDELAY Time from EN rising until start switching 100 200 400 µs POWER SWITCH RDS(ON) High-Side MOSFET ON-Resistance VIN ≥ 3 V Phase1 36 98 mΩ Phase2 Low-Side MOSFET ON-Resistance Phase1 29 72 mΩ Phase2 ILIM High-Side MOSFET Current Limit per phase 4.3 5.0 5.8 A

ADVANCE□INFORMATION TPSM82480 SLVSDT1 –JULY 2017 www.ti.com Product Folder Links: TPSM82480 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) over operating junction temperature range (TJ = –40°C to 125°C) and VIN = 2.4 V to 5.5 V. Typical values at VIN = 3.6 V and TJ = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) The output voltage accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage ripple. (2) For detailed information on output discharge see Active Output Discharge. OUTPUT VREF Internal Reference Voltage 0.6 V ILKG(FB) Input Leakage Current (FB) EN = High VFB = 0.6 V 1 65 nA ILKG(RS) Input Leakage Current (RS) VSEL = Low, VRS = 0.6 V 1 65 nA RRS Internal resistance (RS to GND) VSEL = High, IRS = 1 mA 10 50 Ω VOUT Output Voltage Range VIN ≥ VOUT 0.6 5.5 V VOUT Feedback Voltage Accuracy PWM Mode, VIN ≥ VOUT + 1 V VOUT Feedback Voltage Accuracy Power Save Mode, L = 0.47 µH, Output Discharge Current(2) EN = Low, VOUT = 2.5 V 120 mA Load Regulation VOUT = 1.8 V, PWM mode operation 0.02 %/A Line Regulation 2.6 V ≤ VIN ≤ 5.5 V, VOUT = 1.8 V, IOUT = 6 A, PWM mode operation 0.02 %/V

6.6 Typical Characteristics

Figure 2. Quiescent Current Figure 3. Shutdown Current Figure 4. High-Side Switch Resistance Figure 5. Low-Side Switch Resistance

7 Detailed Description

7.1 Overview

the actual peak inductor current level for every switching cycle. The regulation network is internally compensated. conversion efficiency high over the whole load current range. with high performance and as small as possible solution size.

7.2 Functional Block Diagram

Figure 6. TPSM82480

7.3 Feature Description

7.3.1 Enable / Shutdown (EN)

The device starts operation, when VIN is present and enable (EN) is set High. Since the boundary EN thresholds are specified with 1.2 V for rising and 0.4 V for falling voltages, the typical vales are 0.85 V (rising) and 0.65 V (falling). The device is disabled by pulling EN Low. Leaving the EN pin floating is not recommended.

7.3.2 Soft Start (SS), Pre-biased Output

The internal soft start circuit controls the output voltage slope during startup. This avoids excessive inrush current and provides an adjustable controlled output-voltage rise time. The soft start also prevents unwanted voltage drop from high impedance power sources or batteries. When EN is set to start device operation, the device starts switching after a delay of typically 200 µs and VOUT rises with a slope, controlled by the external capacitor which is connected to the SS/TR pin (soft start). Leaving the SS/TR pin floating or connecting to VIN provides internally set fastest startup with a soft start slope of about 80us. See Application Curves for typical startup operation. The device can start into a pre-biased output. In this case, the device starts switching, only when the internal set point for VOUT increases above the pre-biased voltage level.

7.3.3 Tracking (TR)

The device tracks an external voltage applied to the SS/TR pin. The FB voltage tracks the external voltage as long as it is below about 0.6V. Above 0.6V the device goes to normal operation. If the voltage at the SS/TR pin decreases below about 0.6V, the FB voltage tracks again this voltage. See Tracking for further details.

7.3.4 Output Voltage Select (VSEL)

A resistive divider (VOUT to FB to AGND) sets the output voltage of the TPSM82480. Providing a logic High level at the VSEL pin, another resistor, connected between FB and RS pins is connected in parallel to the lower resistor of the divider. This sets a different higher output voltage and can be used for dynamic voltage scaling (see Setting VOUT2 Using the VSEL Feature). If the VSEL pin is set Low, the device connects an internal pull down resistor to keep the internal logic level Low, even if the pin is floating afterwards. The device disconnects the resistor, if the pin is set to High.

7.3.5 Forced PWM (MODE)

To avoid Power Save Mode (PSM) Operation, the device can be forced to PWM mode operation by pulling the MODE pin High. In this case the device operates continuously with it's nominal switching frequency and the minimum peak current can go as low as -500 mA. If the MODE pin is set Low, the device connects an internal pull down resistor to keep the internal logic level Low, even if the pin is floating afterwards. The device disconnects the resistor, if the pin is set to High.

7.3.6 Power Good (PG)

The TPSM82480 has a built in power good function. The PG pin goes High, when the output voltage has reached its nominal value. Otherwise, including when disabled, in UVLO or thermal shutdown, PG is Low. The PG pin is an open drain output that requires a pull-up resistor and can sink typically 2mA. If not used, the PG pin can be left floating or grounded.

7.3.7 Thermal Good (TG)

As long as the junction temperature of the TPSM82480 is below the thermal good temperature of typically 120°C, the logic level at the TG pin is High. If the junction temperature exceeds that temperature, the TG pin goes Low. This can be used for the system to take action preventing excessive heating or even thermal shutdown. The TG pin is an open drain output that requires a pull-up resistor and can sink typically 2mA. If not used, the TG pin can be left floating or grounded.

ADVANCE□INFORMATION ] Hz [f%100ns70DC SWmin /c215/c215/c61 /c40 /c41 IN PEAK OUTINOUTOUT )PSM( SW VI L VVVI 2f /c215/c215 /c45/c215/c215/c61 TPSM82480 SLVSDT1 –JULY 2017 www.ti.com Product Folder Links: TPSM82480 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Feature Description (continued)

7.3.8 Active Output Discharge

The VO pin, connected to the output voltage, provides an active discharge path when the device is switched off by setting EN Low or UVLO event. In case of being activated, this discharge circuit sinks typically 120mA for output voltages of typically 1 V and above. If VOUT is lower, the active current sink enters linear operation mode and the discharge current decreases.

7.3.9 Undervoltage Lockout (UVLO)

The undervoltage lockout prevents misoperation of the device, if the input voltage drops below the UVLO threshold which is set to typically 2.3 V. The converter starts operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.

7.3.10 Thermal Shutdown

The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C (typical), the device goes in thermal shutdown with a hysteresis of about 10°C. Both the power FETs are turned off and the PG pin goes Low. Once TJ has decreased enough, the device resumes normal operation with Soft Start.

7.4 Device Functional Modes

7.4.1 Pulse Width Modulation (PWM) Operation

The TPSM82480 is based on a predictive OFF-time peak current control topology, operating with PWM in continuous conduction mode for heavier loads. The switching frequency is typically 2.2MHz. Both the master and follower phase regulate to the same VOUT level, each with a separate current loop, using the same peak current set point, cycle by cycle. This provides excellent peak current balancing, independent of inductor dc resistance matching. Since the follower phase operates with an adaptive delay to the master phase, phase shifted operation is always obtained. If the load current decreases, the device runs with the master phase only (see Phase Add/Shed and Current Balancing). PWM only mode can be forced by pulling MODE pin High. If MODE is set Low, the device features an automatic transition into Power Save Mode, entered at light loads, running in discontinuous conduction mode (DCM).

7.4.2 Power Save Mode (PSM) Operation

As the load current decreases to half the ripple current, the converter enters Power Save Mode operation. During PSM, the converter operates with reduced switching frequency maintaining high conversion efficiency. Power Save Mode is based on an adaptive peak current target, to keep output voltage ripple low. Since each pulse shifts VOUT up, a pause time happens until VOUT trips the internal VOUT_Low threshold again and the next pulse takes place. The switching frequency in PSM (one phase operation) calculates as: space (1)

7.4.3 Minimum Duty Cycle and 100% Mode Operation

The minimum on-time, which is typically 70ns, normally determines a limit on the minimum operating duty cycle. The calculation is: space (2) space However, a frequency foldback lowers the switching frequency depending on the duty cycle and ensures proper regulation for every duty cycle.

ADVANCE□INFORMATION /c250 /c251 /c249 /c234 /c235 /c233 /c87/c43/c43/c61 m 5 . 132 RIVV ) ON ( DS OUT(min)OUT(min)IN TPSM82480 www.ti.com SLVSDT1 –JULY 2017 Product Folder Links: TPSM82480 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Device Functional Modes (continued) There is no limit towards maximum duty cycle. When the input voltage becomes close to the output voltage, the device enters automatically 100% duty cycle mode and both high-side FETs switch on as long as VOUT remains below the regulation setpoint. In this case, the voltage drop across the high-side FETs and the inductors determines the output voltage level. An estimate for the minimum input voltage to maintain output voltage regulation is: space (3) space Where the maximum DCR of the inductors is 27mΩ. In 100% duty cycle mode, the low-side FETs are switched off. The typical quiescent current in 100% mode is 3.5 mA.

7.4.4 Phase Shifted Operation

Using an inherent benefit of the two-phase conversion, the two phases of TPSM82480 run out of phase. For every switching cycle, the second phase is not allowed to turn on its high-side FET until the master phase has reached its peak current value. This limits the input RMS current and corresponding switching noise.

7.4.5 Phase Add/Shed and Current Balancing

When the load current is below the internal threshold, only the master phase operates. The second phase activates, if the load current exceeds the threshold of typically 1.7 A. The second phase powers off with a hysteresis of about 0.5 A, when the load current decreases.

7.4.6 Current Limit and Short Circuit Protection

Each phase has a separate integrated peak current limit. The dc values are specified in the Electrical Characteristics. While its minimum value limits the output current of the phase, the maximum number gives the current that must be considered to flow in some operating case. At the peak current limit, the device provides its maximum output current. However, if the current limit situation remains for 512 consecutive switching cycles, the peak current folds back to about 1/3 of the regular limit. This limits the output power for over current and short circuit events. The foldback current limit is released to the normal one only if the load current has decreased as far as needed to undercut the (foldback) peak current limit.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.2 Typical Application

Figure 7. Typical Application using TPSM82480 for a 6A Point-Of-Load Power Supply

8.2.1 Design Requirements

Table 1. List of Components

8.2.2 Detailed Design Procedure

8.2.2.1 Setting the Adjustable Output Voltage

8.2.2.2 Setting VOUT2 Using the VSEL Feature

connecting R3 between FB and RS pins and pulling VSEL High. R3 is calculated using Equation 6. V2 the higher level output voltage.

8.2.2.3 Output Capacitor Selection

certain transient response target (see Table 3).

Table 2. Recommended Output Capacitor Values (nominal) and actual effective capacitance. In such case, stability needs to be checked within the actual environment. Table 3. Recommended Output Capacitor Values (nominal) further advantages like smaller voltage ripple and tighter dc output accuracy in Power Save Mode.

8.2.2.4 Input Capacitor Selection

operation, the effective capacitance at the VIN pins must not fall below 2 x 5 µF. values of input capacitors can be used.

8.2.2.5 Soft Start Capacitor Selection

longer as shown in Figure 8. Figure 8. Soft Start ΔtSS

8.2.2.6 Tracking

doing so, the voltage at the FB pin is directly proportional to the voltage at the SS/TR pin. When choosing the resistive divider proportion according to Equation 8, VOUT tracks VTR simultaneously. Figure 9. Voltage Tracking

ADVANCE□INFORMATION /c87/c61/c87 /c87/c215 /c87/c61/c215/c61 k 8 . 4k120 k240k 4 . 2R RRR /c87/c61/c109/c61 k 4 . 2A250 V 6 . 0R4 TPSM82480 SLVSDT1 –JULY 2017 www.ti.com Product Folder Links: TPSM82480 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Following the example of Setting the Adjustable Output Voltage with VOUT = 1.8 V, R1 = 240 kΩ and R2 = 120 kΩ, Equation 9 and Equation 10 calculate R3 and R4, connected to the SS/TR pin. Different to the resistive divider at the FB pin, a larger current must be chosen, to avoid a tracking offset caused by the 5.25 µA current that flows out of the SS/TR pin. Assuming a 250 µA current, R4 calculates as follows: space (9) space R3 calculates now rearranging Equation 8: space (10) space However, the following limitations can influence the tracking accuracy:

The upper limit of the SS/TR voltage that can be tracked is about 0.6V. Since it is detected internally by a comparator, process variation and ramp speed can cause up to ±30 mV different threshold.
In case that the voltage at SS/TR ramps up immediately when VIN is supplied or EN is set High, the internal startup delay, ΔtDELAY, delays the ramp of VOUT. The internal ramp starts after ΔtDELAY at the voltage level, which is actually present at the SS/TR pin.
The tracking down speed is limited by the RC time constant of the internal output discharge (always connected when tracking down) and the actual load with the output capacitance. Note: The device tracks down with the same behavior for MODE High (Forced PWM) or Low (Auto PSM).

8.2.2.7 Thermal Good

The Thermal Good pin provides an open drain output. The logic level is given by the pull up source which can be VOUT. In this case, TG goes or stays Low, when the device switches off due to EN, UVLO or Thermal Shutdown. When using an independent source for the pull up logic, the logic behavior at shutdown differs, because the TG pin internally goes high impedance. As before, TG goes Low when TG threshold is reached, but goes back High in the event of being switched off (e.g. Thermal Shutdown).

8.2.3 Application Curves

Figure 10. Efficiency vs Output Current Figure 11. Efficiency vs Input Voltage Figure 12. Efficiency vs Output Current Figure 13. Efficiency vs Output Voltage Figure 14. Efficiency vs Output Current Figure 15. Efficiency vs Input Voltage

8.3 System Examples

This section provides typical schematics for commonly used output voltage values. Figure 38. A typical 1.8 V & 2.5 V, 6 A Power Supply Table 4. Resistive Divider Values for different Combinations of VOUT

9 Power Supply Recommendations

10 Layout

10.1 Layout Guidelines

Both VOUT1 and VOUT2 must be connected to build a common VOUT structure.

connection, to avoid interference between the input lines. recommended. Otherwise the connection of COUT to GND must be short for good load regulation. RS pin in case of using R3) pin, avoiding long trace distance. For more detailed information about the actual EVM solution, see SLVUAI6.

10.2 Layout Example

Figure 39. TPSM82480 Board Layout

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

TPSM82480EVM-BSR002 Evaluation Module User's Guide, SLVUB57

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

ADVANCE□INFORMATION TPSM82480 www.ti.com SLVSDT1 –JULY 2017 Product Folder Links: TPSM82480 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. space (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) space (3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. space (5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

12.1 Package Option Addendum

12.1.1 Packaging Information

Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish(3) MSL Peak Temp (4) Op Temp (°C) Device Marking(5)(6) TPSM82480MOPR PREVIEW QFM MOP 24 3000 TBD CU NIPDAU Level-1-260C-UNLIM –40 to 125 TBD TPSM82480MOPT PREVIEW QFM MOP 24 250 TBD CU NIPDAU Level-1-260C-UNLIM –40 to 125 TBD

ADVANCE□INFORMATION Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed TPSM82480 SLVSDT1 –JULY 2017 www.ti.com Product Folder Links: TPSM82480 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

12.1.2 Tape and Reel Information

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPSM82480MOPR QFM MOP 24 3000 TPSM82480MOPT QFM MOP 24 250

ADVANCE□INFORMATION TAPE AND REEL BOX DIMENSIONS Width (mm) W L H TPSM82480 www.ti.com SLVSDT1 –JULY 2017 Product Folder Links: TPSM82480 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPSM82480MOPR QFM MOP 24 3000 TPSM82480MOPT QFM MOP 24 250

www.ti.com PACKAGE OUTLINE C

1.75 MAX

PICK & PLACE NOZZLE AREA 2X 2.0 1.8 6X 3.275 .000 SYMM .000SYMM0 18X 1.475 10X 0.3 0.2 6X 1.35 1.15 4X 1.1 0.9 4X 2.3 2.1 18X 0.65 0.45 4X 0.65 0.45 4X 0.675 4X 1.875

1.55 MAX

4X 1.2754X 14X 0.5 B 3.7 3.5 A 8.0 7.8 (0.05) TYP QFM - 1.55 mm max heightMOP0024A QUAD FLAT MODULE 4223492/B 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PIN 1 ID AREA

0.08 C SEATING

0.1 C A B

0.05 1320 3 11 0.05 0.1 C A B 0.05 0.05 24 23 SCALE 2.300 SCALE 2.300 ADVANCE□INFORMATION TPSM82480 SLVSDT1 –JULY 2017 www.ti.com Product Folder Links: TPSM82480 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MIN

.000 SYMM0 .000 SYMM0 4X ( )1.075 8X ( )1.075 ( )

2 PADS & 2 VIAS

0.675 4X ( ) 2.175 16X ( ) 0.3 4X ( )0.07 18X ( )1.475 ( )3.675( )2.875 4X ( ) 2.175 4X ( ) 1.575 4X ( ) 0.975 4X ( ) 0.375 1.875 6X ( ) 3.275 4X ( ) 1.575 2X ( ) 2.513 4X ( ) 1.275 18X (0.55) 6X (1.25) 2X (1.9) 4X (1)10X (0.25) 4X (0.55) 4X (2.2) ( 0.2) VIA TYP (R0.05) TYP QFM - 1.55 mm max heightMOP0024A QUAD FLAT MODULE 4223492/B 06/2017 NOTES: (continued) 3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. SOLDER MASK OPENING METAL UNDER SOLDER MASK PAD DETAIL TYPICAL EXPOSED METAL LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE:15X 1320 3 11 2324 ADVANCE□INFORMATION TPSM82480 www.ti.com SLVSDT1 –JULY 2017 Product Folder Links: TPSM82480 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.52) (1.17) 2X (1.7) 4X (0.95) PADS 4, 10,14 & 20 8X (0.98) PADS 21-24 10X (0.25) 10X (0.55) 4X (1.865) PADS 21-24 (R0.05) TYP 18X (1.475) (0.675) 4X (0.685) 6X (3.275) 4X (1.875) PADS 4,10,14 & 20 8X (0.5) QFM - 1.55 mm max heightMOP0024A QUAD FLAT MODULE 4223492/B 06/2017 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE PADS 1, 3, 11 & 13: 88% PADS 4, 10, 14 & 20: 90% PADS 2, 12 & 21-24: 84% SCALE:15X SYMM SYMM 1320 3 11 2324 SOLDER MASK EDGE, TYP METAL UNDER SOLDER MASK TYP EXPOSED METAL TYP ADVANCE□INFORMATION TPSM82480 SLVSDT1 –JULY 2017 www.ti.com Product Folder Links: TPSM82480 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

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Summary

5.5-V Input, 6-A, Step-Down Converter with Integrated Inductor

Description