TPS63802 TI1 | Alldatasheet
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ADVANCE□INFORMATION Output Current (A) Efficiency 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 100P 1m 10m 100m 1 2 D002 D001 VIN = 2.5V VIN = 3.0V VIN = 3.7V VIN = 4.3V VIN 1.3V t5.5V EN MODE VIN L2L1 GND VOUT AGND PG FB F F TPS63802 1µH VOUT 3.3V / 2A Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS63802 SLVSEU9 –NOVEMBER 2018 TPS638022-A,High-Efficient,LowIQBuck-BoostConverterwithSmallSolutionSize
1 Features
1• Input Voltage Range: 1.3 V to 5.5 V – >1.8 V for Device Start-up
- Output Voltage Range: 1.8 V to 5 V (adjustable)
- 2-A Output Current for VIN ≥ 2.3 V, VOUT = 3.3 V
- High Efficiency Over the Entire Load Range – 11-μA Operating Quiescent Current – Power Save Mode with Mode Selection
- Peak Current Buck-Boost Mode Architecture – Seamless Transition Between Buck, Buck- Boost and Boost operation modes – Operates With Low and High Output Capacitance values – Forward and Reverse Current Operation – Start-up Into Pre-Biased Outputs
- Safety- and Robust Operation Features – Integrated Soft Start – Over-Temperature- and Over-Voltage- Protection – True Shutdown Function with Load Disconnect – Forward and Backward current limit
- Small Solution Size – 2 mm x 3 mm Package size – Small 1 µH inductor – Works With 22 µF Minimum Output Capacitor
2 Applications
- System Pre-Regulator (Smartphone, Tablet, EFT Terminal, Telematics)
- Point-of-Load Regulation (Wired Sensor, Port/Cable Adapter and Dongle)
- Fingerprint, Face-ID, Camera Sensors (Smartphone, Electronic Smart Lock, IP Network Camera)
- RF Amplifier Supply (Smart Sensors)
- Thermoelectric Device (TEC/TEM) Supply (Datacom, Optical Modules, Cooling/Heating)
3 Description
The TPS63802 is a high efficiency, high output current buck-boost converter. It is used when the input voltage is higher, equal, or lower than the output voltage. Output currents up to 2 A are supported over a wide voltage range. The device limits the peak current at 4.5 A in Boost-Mode and 3.5 A in Buck- Mode. The device is adjusted to the programmed output voltage. It automatically changes from buck to boost operation based on the input voltage. It remains in a 3-cycle buck-boost mode when the input voltage is approximately equal to the output voltage. The transitions happen seamlessly and avoids unwanted toggling within the modes. The TPS63802 comes in a 2 mm x 3 mm package. The device works with tiny passive components to keep the overall solution size small. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS63802 HotRod QFN, 10- Pin (0.5mm pitch) 3.0 mm × 2.0 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application Efficiency vs Output Current (VO = 3.3V)
ADVANCE□INFORMATION TPS63802 SLVSEU9 –NOVEMBER 2018 www.ti.com Product Folder Links: TPS63802 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents
12.2 Receiving Notification of Documentation Updates 25
13 Mechanical, Packaging, and Orderable
4 Revision History
November 2018 * Initial release
ADVANCE□INFORMATION 1EN 2MODE 3AGND 4FB 5PG 6 VOUT 7 L2
8 GND
10 VIN
www.ti.com SLVSEU9 –NOVEMBER 2018 Product Folder Links: TPS63802 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated
5 Device Comparison Table
6 Pin Configuration and Functions
DESCRIPTION
10 VIN Supply voltage input
9 L1 Connection for inductor
1 EN Device Enable input. Set HIGH to enable and LOW to disable. It must not be left floating
8 GND Power ground
2 MODE PFM/PWM mode selection. Set LOW for power safe mode, set HIGH for forced PWM mode. It must not be left floating
3 AGND Analog ground
7 L2 Connection for inductor
6 VOUT Power stage output
4 FB Voltage feedback sensing Pin
5 PG Power good indicator, open drain output
ADVANCE□INFORMATION TPS63802 SLVSEU9 –NOVEMBER 2018 www.ti.com Product Folder Links: TPS63802 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground pin.
7 Specifications
7.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage(2) VIN, L1, L2, EN, PFM/PWM, VOUT, FB –0.3 6 V L1, L2 (AC, less than 10ns) –3 9 V Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) Vo margin for accuracy and load steps is considerd in absolut maximum ratings
7.3 Recommended Operating Conditions
VIN Input voltage 1.3 5.5 V VOUT Output voltage 1.8 5 (1) V CIN Effective capacitance connected to VIN 4 5 μF L Effective inductance 0.7 1 1.2 μH COUT Effective capacitance connected to VOUT 6 10 μF TJ Operating junction temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted) THERMAL METRIC(1) TPS63802 UNITHotRod QFN
10 PINS
RΘJA Junction-to-ambient thermal resistance 81.0 °C/W RΘJC(top) Junction-to-case (top) thermal resistance 36.4 °C/W RΘJB Junction-to-board thermal resistance 23.4 °C/W ΨJT Junction-to-top characterization parameter 0.9 °C/W ΨJB Junction-to-board characterization parameter 23.5 °C/W RΘJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
ADVANCE□INFORMATION TPS63802 www.ti.com SLVSEU9 –NOVEMBER 2018 Product Folder Links: TPS63802 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated
7.5 Electrical Characteristics
VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5 V , TJ= –40°C to +125°C, typical values are at TJ= 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN;LOAD Minimum input voltage for full load, once started IOUT = 2 A, VOUT = 3.3 V, TJ = 25°C 2.3 V IQ;VIN Quiescent current into VIN TJ = 25°C, EN = VIN = 3.6 V, VOUT =
3.3 V, not switching 11 μA
ISD Shutdown current into VIN EN = low, -40°C ≤ TJ ≤ 85°C, VIN =
3.6 V, VOUT = 0 V 10 600 nA
Undervoltage lockout threshold VIN falling, VOUT ≥ 1.8 V, once started 1.2 1.25 1.29 V Undervoltage lockout threshold VIN rising 1.6 1.7 1.79 V TSD Thermal shutdown Temperature rising 150 °C TSD;HYST Thermal shutdown hysteresis 20 °C SOFT-START, POWER GOOD Tramp Soft-start, Current limit ramp time TJ = 25°C, VIN = 3.6 V, VOUT = 3.3 V, IO = 3.5A, from 0A to 3.5A 0.28 ms Tdelay Delay from EN-edge until rising VOUT TJ = 25°C, VIN = 3.6 V 100 μs LOGIC SIGNALS EN, MODE VTHR;EN Threshold Voltage rising for EN-Pin 1.07 1.1 1.13 V VTHF;EN Threshold Voltage falling for EN-Pin 0.97 1 1.03 V VIH High-level input voltage 1.2 V VIL Low-level input voltage 0.4 V VPG;rising Power Good threshold voltage VOUT rising, referenced to VOUT nominal 95% VPG;falling VOUT falling, referenced to VOUT nominal 90% VPG;Low Power Good low-level output voltage ISINK = 1 mA 0.4 V tPG;delay Power Good delay time VFB falling 40 µS Ilkg Input leakage current 0.01 0.2 µA OUTPUT ISD Shutdown current into VOUT EN = low, -40°C ≤ TJ ≤ 85°C, VIN = 0.0 V, VOUT = 3.3 V 10 600 nA VFB Feedback Regulation Voltage 500 mV VFB Feedback Voltage accuracy PWM mode –1% 1% Overvoltage Protection Threshold VOUT rising 5.5 5.66 5.78 V VIN rising 5.5 5.66 5.78 V IPWM/PFM Peak Inductor Current to enter PFM- Mode VIN = 3.6 V; VOUT = 3.3 V 550 700 900 mA IFB Feedback Input Bias Current VFB = 500 mV 10 100 nA IPK Peak Current Limit, Boost Mode VIN ≥ 2.5V 3.5 4.8 5.8 A Peak Current Limit, Buck-Boost Mode 4.8 A Peak Current Limit, Buck Mode 3.5 A IPK;Reverse Peak Current Limit for Reverse Operation VIN = 3.6 V, VOUT = 3.3 V –0.75 –0.5 A Buck RDS;ON High-side FET on-resistance VIN = 3 V, VOUT = 3.3 V 47 mΩ Low-side FET on-resistance VIN = 3 V, VOUT = 3.3 V 30 mΩ Boost RDS;ON High-side FET on-resistance VIN = 3 V, VOUT = 3.3 V 43 mΩ Low-side FET on-resistance VIN = 3 V, VOUT = 3.3 V 18 mΩ
ADVANCE□INFORMATION TPS63802 SLVSEU9 –NOVEMBER 2018 www.ti.com Product Folder Links: TPS63802 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) VIN= 1.8 V to 5.5 V, VOUT = 1.8 V to 5 V , TJ= –40°C to +125°C, typical values are at TJ= 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSW Inductor Switching Frequency, Boost Mode VIN = 2.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C 2.1 MHz Inductor Switching Frequency, Buck- Boost Mode VIN = 3.3V, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C 1.4 MHz Inductor Switching Frequency, Buck Mode VIN = 4.3, VOUT = 3.3V, no Load, MODE = HIGH, TJ = 25°C 2.7 MHz Line regulation VIN = 2.4 V to 5.5 V, VOUT = 3.3V, IOUT = 2 A 0.05 % Load regulation VIN= 3.6 V, VOUT = 3.3V, IOUT = 0 A to 2 A, PWM Mode 0.1 %
7.6 Typical Characteristics
Figure 1. Shutdown Current vs. Temperature Figure 2. Quiescent Current vs Temperature
ADVANCE□INFORMATION EN MODE VIN L2L1 GND VOUT AGND PG FB C IN C OUT L Gate Driver Gate Driver Ref 1.1V Device Control Power Safe Mode Protection Current Limit Buck/Boost Control Off-time calculation Soft-Start ± Ref 500mV VMAX SwitchVIN VOUT Device Control Current Sensor Gate Driver VIN VOUT L1, L2 Power Good Device Control Device Control TPS63802 SLVSEU9 –NOVEMBER 2018 www.ti.com Product Folder Links: TPS63802 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The TPS63802 Buck-Boost converter uses 4 internal switches to maintain synchronous power conversion at all possible operating conditions. This enables the device to keep high efficiency over a wide input voltage and output load range. To regulate the output voltage at all possible input voltage conditions, the device automatically transits between buck, buck-boost and boost operation as required by the configuration. In buck and boost modes, it always uses one active switch, one rectifying switch, one switch on, and one switch held off. Therefore, it operates as a buck converter when the input voltage is higher than the output voltage, and as a boost converter when the input voltage is lower than the output voltage. When the input voltage is close to the output voltage, it operates in a 3-cycle buck-boost operation. In this mode all 4 switches are active (seeBuck-Boost Operation) The RMS current through the switches and the inductor is kept at a minimum, to minimize switching and conduction losses. Controlling the switches this way allows the converter to always keep high efficiency over the complete input voltage range. The device provides a seamless transition between all modes.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Control Loop Description
system current demand (IREF) for the inner Current Loop. Efficiency at light loads. See Power Save Mode Operation for further details. Figure 3. Control Loop Architecture Scheme
8.3.2 Precise Device Enable: Threshold- or delayed Enable
proper operation, the EN pin must be terminated and must not be left floating. Figure 4. Circuit Example how to use the Precise Device Enable feature
8.3.3 Mode Selection (PFM/PWM)
allowing Pulse-Frequency-Modulation for lower output currents. This mode is enabled by applying a low level.
8.3.4 Undervoltage Lockout (UVLO)
Figure 5. Rising and falling Undervoltage Lockout behavior
8.3.5 Softstart
as well as the possibility to start into high loads at start-up. switching cycle request from the output voltage control loop. Figure 6. Device Start-up Scheme
8.3.6 Adjustable Output Voltage
side resistor of less than 100 KΩ. The high-side resistor is chosen accordingly.
8.3.7 Over Temperature Protection - Thermal Shutdown
the over-temperature threshold.
8.3.8 Input Overvoltage - Reverse-Boost Protection (IVP)
and the negative current operation is interrupted. The PG signal goes low to indicate that behavior.
8.3.9 Output Overvoltage Protection (OVP)
8.3.10 Power Good Indicator
the PG pin unconnected when not used. Table 1. Power Good Indicator Truth Table
8.4 Device Functional Modes
8.4.1 Peak Current Mode Architecture
and a function of VI and VO.
Figure 7. Peak Current Architecture Operation
8.4.1.1 Reverse Current Operation, Negative Current
negative value. The maximum average current is even more negative than the peak current. Figure 8. Peak Current Operation, Reverse Current
8.4.1.2 Boost Operation
Figure 9. Peak Current Boost Operation
8.4.1.3 Buck-Boost Operation
- TON: Boost Charge Phase where Boost Low-Side and Buck High-Side are closed and inductor current is built up
- TOFF: Buck Discharge Phase where Boost High-Side and Buck Low-Side are closed and inductor is discharged
- TCOM: VI connected to VO where all High-Side switches are closed and input is connected to output
Figure 10. Peak Current Buck-Boost Operation
8.4.1.4 Buck Operation
Figure 11. Peak Current Buck Operation
8.4.2 Power Save Mode Operation
loop has risen VO by bringing charge to the output, the Voltage loop output IREF (respectively VEA) decreases. When IREF falls below ISKIP-Hysteresis, it automatically goes into pause again.
Figure 12. Power Safe Mode Operation Curves
8.4.2.1 Current Limit Operation
the device in this Mode, it behaves similar to a current source.
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
voltage is higher, lower or equal to the output voltage.
9.2 Typical Application
Figure 13. 3.3VOUT Typical Application
9.2.1 Design Requirements
Table 2 shows the list of components for the Application Characteristic Curves. Table 2. Components for Application Characteristic Curves(1)
9.2.2 Detailed Design Procedure
and capacitor value combinations.
9.2.2.1 Output Capacitor
There is no upper limit for the output capacitance value.
9.2.2.2 Input Capacitor Selection
9.2.2.3 Inductor Selection
transition point into Power Save Mode, and efficiency. See Table 3 for typical inductors. Table 3. List of Recommended Inductors(1) current value for selecting the right inductor.
- D =Duty Cycle in Boost mode
- f = Converter switching frequency (typical 2.5 MHz)
- L = Inductor value
- η = Estimated converter efficiency (use the number from the efficiency curves or 0.90 as an assumption)
than the value calculated using Equation 2. Possible inductors are listed in Table 3.
9.2.2.4 Setting The Output Voltage
not exceed 100 kΩ. The high-side resistor (between FB and VOUT) R1 is calculated by Equation 3. Table 4. Resistor selection for typ. voltages
2.5 V 365 kΩ 91 kΩ
3.3 V 511 kΩ 91 kΩ
3.6 V 562 kΩ 91 kΩ
5 V 806 kΩ 91 kΩ
9.2.3 Application Curves
Figure 14. Typical Output Current Capability vs. Input Figure 15. Efficiency vs. Output Current Figure 16. Efficiency vs. Output Current Figure 17. Efficiency vs. Output Current Figure 18. Efficiency vs. Output Current VI = 2.3V, VO = 3.3V no Load, MODE = HIGH Figure 19. Switching Waveforms, PWM Boost Operation
10 Power Supply Recommendations
11 Layout
11.1 Layout Requirements
The PCB layout is an important step to maintain the high performance of the TPS63802 devices.
- Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Routing wide and direct traces to the input and output capacitor results in low trace resistance and low parasitic inductance.
- Separate AGND and PGND: Do not connect AGND and PGND directly at the IC! See as an example.
- Use a common-power GND but connect AGND & PGND through a via at a different layer.
- Use separate traces for the supply voltage of the power stage; and, the supply voltage of the analog stage.
- The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes.
11.2 Layout Example
Figure 38. TPS6380x Layout
ADVANCE□INFORMATION TPS63802 www.ti.com SLVSEU9 –NOVEMBER 2018 Product Folder Links: TPS63802 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 29-Nov-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS63802DLAR PREVIEW VSON-HR DLA 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 63802 TPS63802DLAT PREVIEW VSON-HR DLA 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 63802 XPS63802DLAT ACTIVE VSON-HR DLA 10 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 29-Nov-2018 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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