TPS62810-Q1_19 TI1 | Alldatasheet
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Technical content
ADVANCE□INFORMATION Output Current (A) Efficiency (%) 100 100P 1m 10m 100m 1 4 D002 VIN = 4.0 V VIN = 5.0 V VIN = 6.0 V L
0.47 H/c109
V 2.75V - 6V IN C IN /c109F C 47 F OUT /c109 TPS62810 EN VOUT GND PG SS/TR COMP/FSET R CF CSS Copyright © 2018, Texas Instruments Incorporated CFF Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 TPS6281x-Q12.75-Vto6-Vadjustable-frequencystep-downconverter
1 Features
1• AEC-Q100 qualified for automotive applications – Device temperature grade 1: –40°C to +125°C TA
- Input voltage range: 2.75 V to 6 V
- Family of 1 A, 2 A, 3 A and 4 A
- Quiescent current 15 µA typical
- Output voltage from 0.6 V to 5.5 V
- Output voltage accuracy ±1% (PWM operation)
- Adjustable soft-start
- Forced PWM or PWM and PFM operation
- Adjustable switching frequency of
1.8 MHz to 4 MHz
- Precise ENABLE input allows – User-defined undervoltage lockout – Exact sequencing
- 100% duty cycle mode
- Active output discharge
- Spread spectrum clocking - optional
- Fold-back overcurrent protection - optional
- Power good output with window comparator
- Package with wettable flanks
2 Applications
- Infotainment head unit
- Hybrid and reconfigurable cluster
- Telematics control Unit
- Surround view ECU
- ADAS sensor fusion
- External amplifier
3 Description
The TPS6281x-Q1 family is a pin-to-pin 1-A, 2-A, 3-A and 4-A synchronous step-down DC/DC converters. All devices offer high efficiency and ease of use. The TPS6281x-Q1 family is based on a peak current mode control topology. TPS6281x-Q1 is designed for automotive applications such as Infotainment and advanced driver assistance systems. Low resistive switches allow up to 4-A continuous output current at high ambient temperature. The switching frequency is externally adjustable from 1.8 MHz to 4 MHz and can also be synchronized to an external clock in the same frequency range. In PWM/PFM mode, The TPS6281x-Q1 automatically enters Power Save Mode at light loads to maintain high efficiency across the whole load range. The TPS6281x-Q1 provides a 1% output voltage accuracy in PWM mode which helps design a power supply with high output voltage accuracy. The SS/TR pin allows setting the start-up time or forming tracking of the output voltage to an external source. This allows external sequencing of different supply rails and limiting the inrush current during start-up. The TPS6281x-Q1 is available as an adjustable version, packaged in a 3-mm x 2-mm VQFN package with wettable flanks. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS62810-Q1 VQFN 3 mm x 2 mm TPS62811-Q1 VQFN 3 mm x 2 mm TPS62812-Q1 VQFN 3 mm x 2 mm TPS62813-Q1 VQFN 3 mm x 2 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Schematic Efficiency vs Output Current; VOUT = 3.3 V; PWM/PFM; fS = 2.25 MHz
ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 www.ti.com Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Table of Contents
13.4 Receiving Notification of Documentation Updates 34
14 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (August 2018) to Revision A Page
ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 www.ti.com SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) Product Preview
5 Device Comparison Table
DEVICE NUMBER FEATURES OUTPUT VOLTAGE TPS62810-Q1
4 A output current
fold-back current limit = OFF spread spectrum clocking = OFF adjustable TPS6281020-Q1(1) 4A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = ON adjustable TPS62811-Q1(1)
1 A output current
fold-back current limit = OFF spread spectrum clocking = OFF adjustable TPS6281120-Q1(1) 1A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = ON adjustable TPS628110A-Q1(1) 1A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = OFF fixed 1.2V TPS628110M-Q1(1) 1A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = OFF fixed 1.8V TPS62812-Q1
2 A output current
fold-back current limit = OFF spread spectrum clocking = OFF adjustable TPS6281220-Q1(1) 2A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = ON adjustable TPS6281206-Q1(1) 2A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = OFF fixed 1.0V TPS6281208-Q1(1) 2A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = OFF fixed 1.1V TPS628120C-Q1(1) 2A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = OFF fixed 1.3V TPS62813-Q1(1)
3 A output current
fold-back current limit = OFF spread spectrum clocking = OFF adjustable TPS6281320-Q1(1) 3A output current Vout discharge fold-back current limit = OFF spread spectrum clocking = ON adjustable
ADVANCE□INFORMATION PG SS/TRVIN SW GND 1 2 3 PG COMP/ FSET SS/TR FB EN VINSWGND 5 4 7 8 123 bottom viewtop view MODE/SYNC FB COMP/ FSET EN MODE/SYNC TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 www.ti.com Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
6 Pin Configuration and Functions
9 Pin (VQFN)
NAME NO. EN 8 I This is the enable pin of the device. Connect to logic low to disable the device. Pull high to enable the device. Do not leave this pin unconnected. FB 5 I Voltage feedback input, connect the resistive output voltage divider to this pin. GND 4 Ground pin MODE/SYNC 1 I The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high, the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can also be used to synchronize the device to an external frequency. See the electrical characteristics for the detailed specification for the digital signal applied to this pin for external synchronization. COMP/FSET 7 I Device compensation and frequency set input. A resistor from this pin to GND defines the compensation of the control loop as well as the switching frequency if not externally synchronized. PG 9 O Open drain power good output. SS/TR 6 I Soft-Start / Tracking pin. An external capacitor connected from this pin to GND defines the rise time for the internal reference voltage. The pin can also be used as an input for tracking and sequencing -see the application section in this data sheet. SW 3 This is the switch pin of the converter and is connected to the internal Power MOSFETs. VIN 2 Power supply input. Make sure the input capacitor is connected as close as possible between pin VIN and PGND.
ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 www.ti.com SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) While switching
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Pin voltage range(1) VIN -0.3 6.5 V SW -0.3 VIN+0.3 V SW (transient for less than 10 ns)(2) -3 10 V FB -0.3 4 V PG, SS/TR, COMP/FSET -0.3 VIN+0.3 V Pin voltage range(1) EN, MODE/SYNC -0.3 6.5 V Storage temperature, Tstg -65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±750 (1) The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the manufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.
7.3 Recommended Operating Conditions
VIN Supply voltage range 2.75 6 V VOUT Output voltage range 0.6 5.5 V L Effective inductance for a switching frequency of 3.5 MHz to 4 MHz 0.25 0.33 0.9 µH COUT Effective output capacitance for 1A and 2A version(1) 15 22 470 µF COUT Effective output capacitance for 3A and 4A version (1) 27 47 470 µF CIN Effective input capacitance(1) 5 10 µF RFSET 4.5 100 kΩ TJ Operating junction temperature -40 +150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) TPS6281x-Q1 UNITRWY
9 PINS
RθJA Junction-to-ambient thermal resistance 71.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 37.2 °C/W RθJB Junction-to-board thermal resistance 16.4 °C/W ψJT Junction-to-top characterization parameter 0.9 °C/W ψJB Junction-to-board characterization parameter 16.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 www.ti.com Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
7.5 Electrical Characteristics
over operating junction temperature (TJ = -40 °C to +150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25 °C. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching, TJ= 125 °C 21 µA IQ Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching 15 30 µA ISD Shutdown Current EN = 0 V, at TJ= 125 °C 18 µA ISD Shutdown Current EN = 0 V, Nominal value at TJ= 25 °C, Max value at TJ= 150 °C 1.5 26 µA VUVLO Undervoltage Lockout Threshold Rising Input Voltage 2.5 2.6 2.75 V Falling Input Voltage 2.3 2.5 2.6 V TSD Thermal Shutdown Temperature Rising Junction Temperature 170 Thermal Shutdown Hysteresis 15 CONTROL (EN, SS/TR, PG, MODE) VIH High Level Input Voltage for MODE Pin 1.1 V VIL Low Level Input Voltage for MODE Pin 0.3 V fSYNC Frequency Range on MODE Pin for Synchronization requires a resistor from COMP/FSET to GND, see application section 1.8 4 MHz duty cycle of synchronization signal at MODE Pin 40% 50% 60% Time to Lock to External Frequency 50 µs VIH Input Threshold Voltage for EN pin; Rising Edge 1.06 1.1 1.15 V VIL Input Threshold Voltage for EN pin; Falling Edge 0.96 1.0 1.05 V ILKG Input Leakage Current for EN, MODE/SYNC VIH = VIN or VIL= GND 150 nA resistance from COMP/FSET to GND for logic low internal frequency setting with f = 2.25 MHz 0 2.5 kΩ voltage on COMP/FSET for logic high internal frequency setting with f = 2.25 MHz VIN V VTH_PG UVP Power Good Threshold Voltage; dc Level Rising (%VOUT) 92% 95% 98% UVP Power Good Threshold Voltage; dc Level Falling (%VOUT) 87% 90% 93% OVP Power Good Threshold; dc Level Rising (%VOUT) 107% 110% 113% OVP Power Good Threshold; dc Level Falling (%VOUT) 104% 107% 111% power good de-glitch time for a high level to low level transition on power good 40 µs VOL_PG Power Good Output Low Voltage IPG = 2 mA 0.07 0.3 V ILKG_PG Input Leakage Current (PG) VPG = 5 V 100 nA ISS/TR SS/TR Pin Source Current 2.1 2.5 2.8 µA Tracking Gain VFB / VSS/TR 1 Tracking Offset feedback voltage with VSS/TR = 0 V 17 mV POWER SWITCH RDS(ON) High-Side MOSFET ON- Resistance VIN ≥ 5 V 37 60 mΩ Low-Side MOSFET ON- Resistance VIN ≥ 5 V 15 35 mΩ High-Side MOSFET leakage current TJ = 85 °C; VIN = 6 V; V(SW) = 0 V 1.5 µA High-Side MOSFET leakage current VIN = 6 V; V(SW) = 0 V 30 µA
ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 www.ti.com SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating junction temperature (TJ = -40 °C to +150 °C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25 °C. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-Side MOSFET leakage current TJ = 85 °C; V(SW) = 6 V 3 µA Low-Side MOSFET leakage current V(SW) = 6 V 55 µA SW leakage V(SW) = 0.6 V; current into SW pin -0.025 30 µA ILIMH High-Side MOSFET Current Limit dc value, for TPS62810; VIN = 3 V to 6 V 4.8 5.6 6.4 A ILIMH High-Side MOSFET Current Limit dc value, for TPS62813; VIN = 3V to 6 V 3.9 4.5 5.1 A ILIMH High-Side MOSFET Current Limit dc value, for TPS62812; VIN = 3V to 6 V 2.9 3.4 3.9 A ILIMH High-Side MOSFET Current Limit dc value, for TPS62811; VIN = 3V to 6 V 2.1 2.6 3.0 A ILIMNEG Negative Valley Current Limit dc value -1.8 A fS PWM Switching Frequency Range see the fset function about setting the switching frequency 1.8 2.25 4 MHz fS PWM Switching Frequency with COMP/FSET tied to VIN or GND 2.025 2.25 2.475 MHz PWM Switching Frequency Tolerance using a resistor from COMP/FSET to GND, fs = 1.8 MHz to < 3 MHz -15% 15% PWM Switching Frequency Tolerance using a resistor from COMP/FSET to GND, fs = 3 MHz to 4 MHz -19% 16% ton,min Minimum on-time of HS FET TJ = -40 °C to 125 °C, VIN = 3.3 V 50 75 ns ton,min Minimum on-time of LS FET VIN = 3.3 V 30 ns OUTPUT VFB Feedback Voltage 0.6 V ILKG_FB Input Leakage Current (FB) VFB = 0.6 V 1 70 nA VFB Feedback Voltage Accuracy VIN ≥ VOUT + 1 V PWM mode -1% 1% VIN ≥ VOUT + 1 V; VOUT ≥ 1.5 V PFM mode; Co,eff ≥ 22 µF, L = 0.47 µH -1% 2% 1 V ≤ VOUT < 1.5 V PFM mode; Co,eff ≥ 47 µF, L = 0.47 µH -1% 2.5% VFB Feedback Voltage Accuracy with Voltage Tracking VIN ≥ VOUT + 1 V; VSS/TR = 0.3 V PWM mode -2% 5% Load Regulation PWM mode operation 0.05 %/A Line Regulation PWM mode operation, IOUT= 1 A, VIN ≥ VOUT + 1 V 0.02 %/V Output Discharge Resistance 50 Ω tdelay Start-up Delay Time IOUT = 0 mA, Time from EN=high to start switching; VIN applied already 135 200 450 µs tdelay Start-up Delay Time IOUT = 0 mA, Time from EN=high to start switching; VIN applied already; VIN ≥ 3.1 V 420 tramp Ramp time; SS/TR Pin Open IOUT = 0 mA, Time from first switching pulse until 95% of nominal output voltage; device not in current limit 100 150 200 µs
7.6 Typical Characteristics
Figure 1. Rds(on) of High Side Switch Figure 2. Rds(on) of Low Side Switch
0.56 H/c109
2.75 V - 6 V
8 Parameter Measurement Information
8.1 Schematic
Figure 3. Measurement Setup for TPS62810 and TPS62813 Table 1. List of Components Figure 4. Measurement Setup for TPS62812 and TPS62811
Table 2. List of Components
ADVANCE□INFORMATION GND FB SWVIN EN Oscillator Gate Drive and Control Device Control PG Thermal Shutdown Bias Regulator gm +Ipeak Izero Bandgap SS/TR COMP/FSET MODE TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 www.ti.com SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
The TPS6281x synchronous switch mode power converters are based on a peak current mode control topology. The control loop is internally compensated. In order to optimize the bandwidth of the control loop to the wide range of output capacitance that can be used with TPS6281x, the internal compensation has 3 settings. See COMP/FSET. One out of the 3 compensation settings is chosen either by a resistor from COMP/FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable operation with small external components and low ESR ceramic output capacitors. The devices can be operated without feed forward capacitor on the output voltage divider, however using a typically 10 pF feed forward capacitor improves transient response. The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN or in a range of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no need for additional passive components. External synchronization can only be used when there is a resistor from COMP/FSET to GND. When COMP/FSET is directly tied to GND or VIN, TPS6281x can not be synchronized externally. An internal PLL allows to change from internal clock to external clock during operation. The synchronization to the external clock is done on a falling edge of the clock applied at MODE to the rising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is used to generate the synchronization signal for a second converter. When the MODE pin is set to a logic low level, the device operates in power save mode (PFM) at low output current and automatically transfers to fixed frequency PWM mode at higher output current. In PFM mode, the switching frequency decreases linearly based on the load to sustain high efficiency down to very low output current.
9.2 Functional Block Diagram
ADVANCE□INFORMATION 60( ) ( ) CF S MHz kR k f MHz /c215 /c87/c87 /c61 18( ) ( ) CF S MHz kR k f MHz /c215 /c87/c87 /c61 TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 www.ti.com Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 Precise Enable
The voltage applied at the Enable pin of the TPS6281x-Q1 is compared to a fixed threshold of 1.1 V for a rising voltage. This allows to drive the pin by a slowly changing voltage and enables the use of an external RC network to achieve a power-up delay. The Precise Enable input allows provides a user programmable undervoltage lockout by adding a resistor divider to the input of the Enable pin. The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The TPS6281x-Q1 starts operation when the rising threshold is exceeded. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown current of typically 1 μA. In this mode, the internal high side and low side MOSFETs are turned off and the entire internal control circuitry is switched off.
9.3.2 COMP/FSET
This pin allows to set two different parameters independently:
- internal compensation settings for the control loop (3 settings available)
- the switching frequency in PWM mode from 1.8 MHz to 4 MHz A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change in compensation allows to adopt the device to different values of output capacitance. The resistor should be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting is sampled at start-up of the converter, so a change in the resistor during operation only has an effect on the switching frequency but not on the compensation. In order to save external components, the pin can also be directly tied to VIN or GND to set a pre-defined switching frequency / compensation. Do not leave the pin floating. The switching frequency has to be selected based on the input voltage and the output voltage to meet the specifications for the minimum on-time and minimum off-time. Example: VIN = 5 V, VOUT = 1 V --> duty cycle (DC) = 1 V / 5 V = 0.2
- with ton = DC * T --> ton,min = 1/fs,max * DC
- --> fs,max = 1/ton,min * DC = 1/0.075 µs * 0.2 = 2.67 MHz The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be increased from the minimum value as given in Table 3 and Table 4, up to the maximum of 470 µF in all of the 3 compensation ranges. If the capacitance of an output changes during operation, e.g. when load switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for the minimum capacitance on the output. With large output capacitance, the compensation should be done based on that large capacitance to get the best load transient response. Compensating for large output capacitance but placing less capacitance on the output may lead to instability. The switching frequency for the different compensation setting is determined by the following equations. For compensation (comp) setting 1: Space (1) For compensation (comp) setting 2: Space (2) Space For compensation (comp) setting 3:
Table 3. Switching Frequency and Compensation for TPS62810 (4 A) and TPS62813 (3 A) Table 4. Switching Frequency and Compensation for TPS62812 (2 A) and TPS62811 (1 A) Refer to Output Capacitor for further details on the output capacitance required depending on the output voltage. A too high resistor value for RCF is decoded as "tied to VIN", a value below the lowest range as "tied to GND". capacitance is distributed, a lower compensation setting may be required.
9.3.3 MODE / SYNC
COMP/FSET to GND but the pin is pulled high or low, external synchronization is not possible.
9.3.4 Spread Spectrum Clocking (SSC); optional
typically between the nominal switching frequency and up to 288kHz above the nominal switching frequency.
9.3.5 Undervoltage Lockout (UVLO)
input voltage trips below the threshold for a falling supply voltage.
9.3.6 Power Good Output (PG)
defined in the electrical characteristics, the output is high impedance. Table 5. PG Status
9.3.7 Thermal Shutdown
delay, the device will not detect a too high junction temperature.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
operate at, taking the minimum on-time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
output current becomes smaller than half of the inductor´s ripple current. In power save mode the switching frequency decreases linearly with the load current maintaining high efficiency.
ADVANCE□INFORMATION ( ) 50 IN OUT peak typ LIMH V VI I ns L /c45/c61 /c43 /c215 ( ) L peak typ LIMH PD VI I t L/c61 /c43 /c215 TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 www.ti.com SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated Device Functional Modes (continued) 9.4.3 100% Duty-Cycle Operation The duty cycle of a buck converter operated in PWM mode is given as D=VOUT/VIN. The duty cycle increases as the input voltage comes close to the output voltage and the off-time gets smaller. When the minimum off-time of typically 30 ns is reached, TPS6281x-Q1 skips switching cycles while it approaches 100% mode. In 100% mode, it keeps the high-side switch on continuously. The high side switch stays turned on as long as the output voltage is below the target. In 100% mode, the low side switch is turned off. The maximum dropout voltage in 100% mode is the product of the on-resistance of the high side switch plus the series resistance of the inductor and the load current.
9.4.4 Current Limit and Short Circuit Protection
The TPS6281x-Q1 is protected against overload and short circuit events. If the inductor current exceeds the current limit ILIMH, the high side switch is turned off and the low side switch is turned on to ramp down the inductor current. The high side switch turns on again only if the current in the low side switch has decreased below the low side current limit. Due to internal propagation delay, the actual current can exceed the static current limit. The dynamic current limit is given as: (4) where: ILIMH is the static current limit as specified in the electrical characteristics L is the effective inductance at the peak current VL is the voltage across the inductor (VIN - VOUT) and tPD is the internal propagation delay of typically 50 ns. The current limit can exceed static values, especially if the input voltage is high and very small inductances are used. The dynamic high side switch peak current can be calculated as follows: (5)
9.4.5 Fold-back Current Limit and Short Circuit Protection
This is valid for devices where fold-back current limit is enabled. When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current limit from its nominal value to typically 1.8 A. Fold-back current limit is left when the current limit indication goes away. For the case that device operation continues in current limit, it would, after 3072 switching cycles try again full current limit for again 1024 switching cycles.
9.4.6 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device is being disabled but also to keep the output voltage close to 0 V when the device is off. The output discharge feature is only active once TPS6281x-Q1 has been enabled at least once since the supply voltage was applied. The discharge function is enabled as soon as the device is disabled, in thermal shutdown or in undervoltage lockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Output discharge is not activated during a current limit or fold-back current limit event.
9.4.7 Soft Start / Tracking (SS/TR)
The internal Soft-Start circuitry controls the output voltage slope during startup. This avoids excessive inrush current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high impedance power sources or batteries. When EN is set high to start operation, the device starts switching after a delay of about 200 μs then the internal reference and hence VOUT rises with a slope controlled by an external capacitor connected to the SS/TR pin. Leaving the SS/TR pin un-connected provides the fastest startup ramp with 150 µs typically. A capacitor connected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start until it reaches the reference voltage of 0.6 V. The capacitance required to set a certain ramp-time (tramp) therefore is:
ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 www.ti.com Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Device Functional Modes (continued) (6) If the device is set to shutdown (EN = GND), undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new startup sequence. A voltage applied at SS/TR can be used to track a master voltage. The output voltage follows this voltage in both directions up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the load current. The SS/TR pin must not be connected to the SS/TR pin of other devices. An external voltage applied on SS/TR is internally clamped to the feedback voltage (0.6 V). It is recommended to set the target for the external voltage on SS/TR slightly above the feedback voltage. Given the tolerances of the resistor divider R5 and R6 on SS/TR, this makes sure the device "switches" to the internal reference voltage when the power-up sequencing is finished. See Figure 62.
(1) Lower of IRMS at 20 °C rise or ISAT at 20% drop. validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Programming the Output Voltage
resistor values are recommended for highest accuracy and most robust design.
10.1.2 External Component Selection
10.1.3 Inductor Selection
The TPS6281x-Q1 is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25 MHz. nominal switching frequency, the inductance should be changed accordingly. current and DC resistance (DCR). Equation 8 calculates the maximum inductor current.
- IL(max) is the maximum inductor current
- ΔIL(max) is the Peak to Peak Inductor Ripple Current
- Lmin is the minimum inductance at the operating point
Table 6. Typical Inductors
Table 6. Typical Inductors (continued) useful to get lower ripple current, but increases the transient response time and size as well.
10.1.4 Capacitor Selection
10.1.4.1 Input Capacitor
10.1.4.2 Output Capacitor
the output. The maximum capacitance is 470 µF in any of the compensation settings. changes with the output voltage. ranges and/or ranges for TPS62811 and TPS62812 are equivalent. See Table 3 and Table 4 for details.
10.2 Typical Application
Figure 5. Typical Application
10.2.1 Design Requirements
10.2.2 Detailed Design Procedure
Table 7. Setting the Output Voltage
10.2.3 Application Curves
Figure 6. Efficiency vs Output Current Figure 7. Efficiency vs Output Current Figure 8. Efficiency vs Output Current Figure 9. Efficiency vs Output Current Figure 10. Efficiency vs Output Current Figure 11. Efficiency vs Output Current
Figure 58. Output Voltage Ripple Figure 59. Output Voltage Ripple Figure 60. Output Voltage Ripple
10.3 System Examples
10.3.1 Fixed Output Voltage Versions (PREVIEW)
Figure 61. Independent of that, the application runs with an internally defined switching frequency of 2.25 MHz by connecting COMP/FSET to GND.
Figure 61. Schematic for Fixed Output Voltage Versions
10.3.2 Voltage Tracking
voltage according to the 0.6 V feedback voltage. output voltage close to 0 V.
Figure 62. Schematic for Output Voltage Tracking Figure 63. Scope Plot for Output Voltage Tracking
10.3.3 Synchronizing to an external Clock
close to each other. This ensures a smooth transition from internal to external frequency and vice versa.
Figure 64. Schematic using External Synchronization Figure 65. Switching from External Syncronization to Figure 66. Switching from External Synchronizaion to
11 Power Supply Recommendations
12 Layout
12.1 Layout Guidelines
stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. ground connections. The input capacitor should be placed as close as possible between the VIN and GND pin. and R2, should be kept close to the IC and connect directly to those pins and the system ground plane.
12.2 Layout Example
Figure 67. Example Layout
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
- TPS62810EVM-015 Evaluation Module, SLVUBG0
13.3 Related Links
resources, tools and software, and quick access to order now. Table 8. Related Links
13.4 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
13.5 Community Resources
solve problems with fellow engineers. contact information for technical support.
13.6 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 www.ti.com SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated
13.8 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C1 MAX
0.1 MIN
0.5 TYP
1.1 0.55
0.1 C A B
0.05 C 9X 0.3 0.2 0.05 C 4X 0.4 0.3 0.675 0.575 0.2 0.05 0.55 0.45 0.675 0.575 0.05 0.00 B 2.1 1.9 A 3.1 2.9 (0.2) TYP (0.05) (0.9) VQFN-HR - 1 mm max heightRWY0009A PLASTIC QUAD FLATPACK - NO LEAD 4224015/B 01/2018 PIN 1 INDEX AREA SEATING PLANE 0.08 C SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 5.000 SCALE 30.000SECTION A-A SECTION A-A TYPICAL ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 www.ti.com Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
(0.65) 0.25 (0.5) (0.55) (0.25) (0.35) (0.5) 3X (0.25) 3X (2.3) (2.65) (R0.05) TYP (0.775) (0.775) VQFN-HR - 1 mm max heightRWY0009A PLASTIC QUAD FLATPACK - NO LEAD 4224015/B 01/2018 NOTES: (continued) 3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE: 25X SYMM SYMM SEE SOLDER MASK DETAIL EXPOSED METAL METAL EDGE SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAIL ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 www.ti.com SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation FeedbackCopyright © 2018–2019, Texas Instruments Incorporated
www.ti.com EXAMPLE STENCIL DESIGN (0.25) (0.775) (0.21) (0.775) (0.31) (2.65) (1.25) (0.65) 6X (0.25) 6X (1.05) (R0.05) TYP (0.5) VQFN-HR - 1 mm max heightRWY0009A PLASTIC QUAD FLATPACK - NO LEAD 4224015/B 01/2018 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL PADS 1, 5, 7 & 8: 90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE: 25X EXPOSED METAL TYP ADVANCE□INFORMATION TPS62810-Q1,TPS62811-Q1 TPS62812-Q1,TPS62813-Q1 SLVSDU1A –AUGUST 2018–REVISED MARCH 2019 www.ti.com Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated
www.ti.com 9-Mar-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples XPS62810QWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 TBD Call TI Call TI -40 to 125 XPS62811QWRWYRQ1 PREVIEW VQFN-HR RWY 9 3000 TBD Call TI Call TI -40 to 125 XPS62812QWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 TBD Call TI Call TI -40 to 125 XPS62813QWRWYRQ1 PREVIEW VQFN-HR RWY 9 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 9-Mar-2019 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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