XPS62088YWCR | DigiCamel IC Datasheet

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TPS62088_19 TI1 | Alldatasheet

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Load (A) Efficiency (%) 100 100P 1m 10m 100m 1 3 D007 VOUT = 0.6V VOUT = 0.9V VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V SW GND FBEN PG VIN 10 µF 100 k 4.7 µF VIN 2.4 V to 5.5 V VPG VOUT 1.8 V 0.24 µH TPS6208818 10 µF Copyright Ú 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS62088 SLVSD94C –NOVEMBER 2017–REVISED MAY 2019 TPS62088,2.4-Vto5.5-VInput,Tiny6-pin3-AStep-DownConverterin1.2-mmx0.8-mm WaferChipScalePackage

1 Features

1• DCS-Control™ topology

Up to 95% efficiency
26-mΩ and 26-mΩ internal power MOSFETs
2.4-V to 5.5-V input voltage range
4-μA operating quiescent current
1% output voltage accuracy
4-MHz switching frequency
Power save mode for light-load efficiency
100% duty cycle for lowest dropout
Active output discharge
Power good output
Thermal shutdown protection
Hiccup short-circuit protection
Available in 6-pin WCSP with 0.4-mm pitch
Supports 12 mm2 solution size
Supports < 0.6 mm height solution
Create a custom design using the TPS62088 with the WEBENCH® Power Designer

2 Applications

Solid-state drives
Wearable products
Smart phones
Camera modules
Optical modules

3 Description

The TPS62088 device is a high-frequency synchronous step-down converter optimized for small solution size and high efficiency. With an input voltage range of 2.4 V to 5.5 V, common battery technologies are supported. At medium to heavy loads, the converter operates in PWM mode and automatically enters Power Save Mode operation at light load to maintain high efficiency over the entire load current range. The 4-MHz switching frequency allows TPS62088 to use small external components. Together with its DCS-control architecture, excellent load transient performance and output voltage regulation accuracy are achieved. Other features like over current protection, thermal shutdown protection, active output discharge and power good are built-in. The device is available in a 6-pin WCSP package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS62088xx YFP (6) 0.8mm x 1.2mm x 0.5mm TPS62088xx YWC (6) 0.8mm x 1.2mm x 0.3mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Spacer Typical Application Schematic Figure 1. 3.3-V Input Voltage Efficiency

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (August 2018) to Revision C Page Changes from Revision A (March 2018) to Revision B Page Changes from Original (November 2017) to Revision A Page

Changed TPS6208812, TPS6208818, and TPS6208833 From: Preview To: Production in the Device Information table ... 1

B A PG C FB EN GND VIN 1 2 C B A Not to scale FB GND PG SW EN VIN SW B C PG A EN FB VIN GND 1 2 A B C Not to scale EN VIN PG SW FB GND TPS62088 www.ti.com SLVSD94C –NOVEMBER 2017–REVISED MAY 2019 Product Folder Links: TPS62088 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated (1) Preview

5 Device Options

PART NUMBER OUTPUT VOLTAGE TPS62088YFP Adjustable TPS62088YWC(1) Adjustable TPS6208812YFP 1.2 V TPS6208818YFP 1.8 V TPS6208833YFP 3.3 V

6 Pin Configuration and Functions

NAME NO. EN A1 I Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables the device. Do not leave floating. PG B1 O Power good open drain output pin. The pull-up resistor can be connected to voltages up to 5.5 V. If unused, leave it floating. FB C1 I Feedback pin. For the fixed output voltage versions, this pin must be connected to the output. GND C2 Ground pin. SW B2 PWR Switch pin of the power stage. VIN A2 PWR Input voltage pin.

SLVSD94C –NOVEMBER 2017–REVISED MAY 2019 www.ti.com Product Folder Links: TPS62088 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) While switching

7 Specifications

7.1 Absolute Maximum Ratings(1)

Voltage at Pins(2) VIN, FB, EN, PG –0.3 6 V SW (DC) –0.3 VIN + 0.3 SW (DC, in current limit) -1.0 VIN + 0.3 SW (AC, less than 10ns)(3) -2.5 10 Temperature Operating Junction, TJ –40 150 °C Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) For YFP package versions, lifetime is reduced when operating continuously at 3-A output current with the junction temperature higher than 85 °C.

7.3 Recommended Operating Conditions

VIN Input voltage range 2.4 5.5 V VOUT Output voltage range 0.6 4 V IOUT Output current range(1) 0 3 A ISINK_PG Sink current at PG pin 1 mA VPG Pull-up resistor voltage 5.5 V TJ Operating junction temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Not applicable to an EVM.

7.4 Thermal Information

THERMAL METRIC(1) TPS62088 UNIT YFP (6-PINS) YWC (6-PINS) EVM-814 RθJA Junction-to-ambient thermal resistance 141.3 130.9 85.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 1.7 1.1 n/a(2) °C/W RθJB Junction-to-board thermal resistance 47.3 27.3 n/a(2) °C/W ψJT Junction-to-top characterization parameter 0.5 0.7 1.9 °C/W ψJB Junction-to-board characterization parameter 47.5 27.2 55.9 °C/W

7.5 ELECTRICAL CHARACTERISTICS

TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V , unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Quiescent current EN = High, no load, device not switching 4 10 µA ISD Shutdown current EN = Low, TJ = -40℃ to 85℃ 0.05 0.5 µA

www.ti.com SLVSD94C –NOVEMBER 2017–REVISED MAY 2019 Product Folder Links: TPS62088 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated ELECTRICAL CHARACTERISTICS (continued) TJ = -40 °C to 125 °C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25 °C and VIN = 5 V , unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VUVLO Under voltage lock out threshold VIN falling 2.1 2.2 2.3 V Under voltage lock out hysteresis VIN rising 160 mV TJSD Thermal shutdown threshold TJ rising 150 °C Thermal shutdown hysteresis TJ falling 20 °C LOGIC INTERFACE EN VIH High-level input threshold voltage 1.0 V VIL Low-level input threshold voltage 0.4 V IEN,LKG Input leakage current into EN pin 0.01 0.1 µA SOFT START, POWER GOOD tSS Soft start time Time from EN high to 95% of VOUT nominal 1.25 ms VPG Power good lower threshold VPG rising, VFB referenced to VFB nominal 94 96 98 % VPG falling, VFB referenced to VFB nominal 90 92 94 % Power good upper threshold VPG rising, VFB referenced to VFB nominal 103 105 107 % VPG falling, VFB referenced to VFB nominal 108 110 112 % VPG,OL Low-level output voltage Isink = 1 mA 0.4 V IPG,LKG Input leakage current into PG pin VPG = 5.0 V 0.01 0.1 µA OUTPUT VOUT Output voltage accuracy TPS6208812, PWM mode 1.188 1.2 1.212 VTPS6208818, PWM mode 1.782 1.8 1.818 TPS6208833, PWM mode 3.267 3.3 3.333 VFB Feedback regulation voltage PWM mode 594 600 606 mV IFB,LKG Feedback input leakage current TPS62088, VFB = 0.6 V 0.01 0.05 µA RFB Internal resistor divider connected to FB pin TPS6208812, TPS6208818, TPS6208833 7.5 MΩ IDIS Output discharge current VSW = 0.4V; EN = LOW 75 400 mA POWER SWITCH RDS(on) High-side FET on-resistance 26 mΩ Low-side FET on-resistance 26 mΩ ILIM High-side FET switch current limit 3.6 4.3 5.0 A fSW PWM switching frequency IOUT = 1 A, VOUT = 1.8 V 4 MHz

7.6 Typical Characteristics

Figure 2. High-Side FET On-Resistance Figure 3. Low-Side FET On-Resistance Figure 4. Quiescent Current Figure 5. Shutdown Current

VPG_H VFB VINPG EA Comparator Direct Control Compensation Peak Current Detect Fixed VOUT VSW VIN VSW VPG_L Discharge TPS62088 www.ti.com SLVSD94C –NOVEMBER 2017–REVISED MAY 2019 Product Folder Links: TPS62088 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TPS62088 synchronous step-down converter adopts a new generation DCS-Control™ (Direct Control with Seamless transition into Power Save Mode) topology without the output voltage sense (VOS) pin. This is an advanced regulation topology that combines the advantages of hysteretic, voltage, and current mode control schemes. The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal switching frequency of 4 MHz, having a controlled frequency variation over the input voltage range. As the load current decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC current consumption to achieve high efficiency over the entire load current range. Because DCS-Control supports both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to Power Save Mode is seamless and without effects on the output voltage. The devices offer both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Power Save Mode

As the load current decreases, the device enters Power Save Mode operation. The power save mode occurs when the inductor current becomes discontinuous. Power Save Mode is based on a fixed on-time architecture, as related in Equation 1. (1)

IN,MIN OUT OUT,MAX DS(on) LV V I (R + R )/c61 /c43 /c180 TPS62088 SLVSD94C –NOVEMBER 2017–REVISED MAY 2019 www.ti.com Product Folder Links: TPS62088 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated Feature Description (continued) In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized by increasing the output capacitor or inductor value. When the device operates close to 100% duty cycle mode, the device can't enter Power Save Mode regardless of the load current if the input voltage decreases to typically 10% above the output voltage. The device maintains output regulation in PWM mode. 8.3.2 100% Duty Cycle Low Dropout Operation The devices offer low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current and output voltage can be calculated as: where

VIN,MIN = Minimum input voltage to maintain an output voltage
IOUT,MAX = Maximum output current
RDS(on) = High-side FET ON-resistance
RL = Inductor ohmic resistance (DCR) (2)

8.3.3 Soft Start

After enabling the device, there is a 250-µs delay before switching starts. Then, an internal soft startup circuitry ramps up the output voltage which reaches nominal output voltage during the startup time of 1 ms. This avoids excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance. The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the output voltage to its nominal value.

8.3.4 Switch Current Limit and HICCUP Short-Circuit Protection

The switch current limit prevents the device from high inductor current and from drawing excessive current from the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET is turned off and the low-side MOSFET remains off, while the inductor current flows through its body diode and quickly ramps down. When this switch current limits is triggered 32 times, the device stops switching. The device then automatically starts a new start-up after a typical delay time of 128 µs has passed. This is named HICCUP short-circuit protection. The device repeats this mode until the high load condition disappears.

8.3.5 Undervoltage Lockout

To avoid mis-operation of the device at low input voltages, under voltage lockout is implemented that shuts down the device at voltages lower than VUVLO.

8.3.6 Thermal Shutdown

The device goes into thermal shutdown and stops the power stage switching when the junction temperature exceeds TJSD. When the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically by switching the power stage again.

8.4 Device Functional Modes

8.4.1 Enable and Disable

pin in shutdown mode. Do not leave the EN pin floating. The typical threshold value of the EN pin is 0.89 V for rising input signal, and 0.62 V for falling input signal.

8.4.2 Power Good

power good output requires a pull-up resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. falling edge has a deglitch delay of 20 µs. Table 1. PG Pin Logic

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

several input and output voltage options by using typical applications as a reference.

9.2 Typical Application

Figure 6. Typical Application of Adjustable Output Figure 7. Typical Application of Fixed Output

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters. Table 2. Design Parameters

12 PC4 =

1 R1VV FBOUT

(1) See Third-party Products disclaimer. Table 3 lists the components used for the example. Table 3. List of Components of Figure 6 (1) See Third-party Products disclaimer. Table 4. List of Components of Figure 7, Smallest Solution

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS62088 device with the WEBENCH® Power Designer.

Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
Compare the generated design with other possible solutions from Texas Instruments.

pricing and component availability.

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Setting The Output Voltage

devices have an internal feed forward capacitor.

(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%. (2) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%. (3) This LC combination is the standard value and recommended for most applications.

9.2.2.3 Output Filter Design

Table 5. Matrix of Output Capacitor and Inductor Combinations (1) See Third-party Products disclaimer.

9.2.2.4 Inductor Selection

inductor. To calculate the maximum inductor current under static load conditions, Equation 5 is given.

IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value (5) It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate inductor. Table 6 lists recommended inductors.

Table 6. List of Recommended Inductors(1)

9.2.2.5 Capacitor Selection

reduces input current ripple. capacitance can vary over a wide range as outline in the output filter selection table. capacitor is not required for the fixed output voltage versions.

9.2.3 Application Curves

VIN = 5.0 V, VOUT = 1.8 V, TA = 25 ºC, BOM = Table 3, unless otherwise noted. Figure 8. Efficiency Figure 9. Load Regulation Figure 10. Efficiency Figure 11. Load Regulation

VIN = 5.0 V, VOUT = 1.8 V, TA = 25 ºC, BOM = Table 3, unless otherwise noted. Figure 24. Load Transient Figure 25. HICCUP Short Circuit Protection Figure 26. HICCUP Short Circuit Protection (Zoom In)

10 Power Supply Recommendations

power supply has a sufficient current rating for the application.

11 Layout

11.1 Layout Guidelines

Figure 27 and Figure 28 for the recommended PCB layout.

The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the power traces short. Routing these power traces direct and wide results in low trace resistance and low parasitic inductance.
The low side of the input and output capacitors must be connected properly to the power GND to avoid a GND potential shift.
The sense traces connected to FB is a signal trace. Special care should be taken to avoid noise being induced. Keep these traces away from SW nodes. The connection of the output voltage trace for the FB resistors should be made at the output capacitor.
Refer to Figure 27 and Figure 28 for an example of component placement, routing and thermal design.

11.2 Layout Example

Figure 27. PCB Layout of Adjustable Output Voltage Figure 28. PCB Layout of Fixed Output Voltage Application

11.3 Thermal Considerations

dissipation limits of a given component.

Improving the power dissipation capability of the PCB design
Introducing airflow in the system For more details on how to use the thermal parameters, see the Thermal Characteristics Application Notes, SZZA017 and SPRA953.

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Development Support

12.2.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS62088 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2.2 Related Documentation

For related documentation, see the following:

Thermal Characteristics Application Note, SZZA017
Thermal Characteristics Application Note, SPRA953

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

DCS-Control, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C0.5 MAX 0.19 0.13 0.8 TYP 0.4 TYP

0.4 TYP

6X 0.25 0.21 0.30 0.25 B E A D 4224455/B 02/2019 D: Max = 1.22 mm, Min = 1.18 mm DSBGA - 0.5 mm max heightYFP0006-C01 DIE SIZE BALL GRID ARRAY E: Max = 0.82 mm, Min = 0.78 mm NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C A B C

0.015 C A B

www.ti.com EXAMPLE BOARD LAYOUT 6X ( 0.23) (0.4) TYP (0.4) TYP ( 0.23) METAL

0.05 MAX

( 0.23) SOLDER MASK OPENING

0.05 MIN

DSBGA - 0.5 mm max heightYFP0006-C01 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). SOLDER MASK DETAILS NOT TO SCALE SYMM SYMM LAND PATTERN EXAMPLE SCALE:50X A B C 1 2 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED TPS62088 www.ti.com SLVSD94C –NOVEMBER 2017–REVISED MAY 2019 Product Folder Links: TPS62088 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN (0.4) TYP (0.4) TYP METAL TYP 4224455/B 02/2019 DSBGA - 0.5 mm max heightYFP0006-C01 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:50X A B C 1 2 TPS62088 SLVSD94C –NOVEMBER 2017–REVISED MAY 2019 www.ti.com Product Folder Links: TPS62088 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

www.ti.com 6-Jun-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS6208812YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS & no Sb/Br) SAC396 Level-1-260C-UNLIM -40 to 125 1B5 TPS6208812YFPT ACTIVE DSBGA YFP 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 1B5 TPS6208818YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 1B6 TPS6208818YFPT ACTIVE DSBGA YFP 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 1B6 TPS6208833YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 1B7 TPS6208833YFPT ACTIVE DSBGA YFP 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 1B7 TPS62088YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 15X TPS62088YFPT ACTIVE DSBGA YFP 6 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 15X XPS62088YWCR ACTIVE PicoCSP YWC 6 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 6-Jun-2019 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 2-May-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS6208812YFPR DSBGA YFP 6 3000 210.0 185.0 35.0 TPS6208812YFPT DSBGA YFP 6 250 210.0 185.0 35.0 TPS6208818YFPR DSBGA YFP 6 3000 210.0 185.0 35.0 TPS6208818YFPT DSBGA YFP 6 250 210.0 185.0 35.0 TPS6208833YFPR DSBGA YFP 6 3000 210.0 185.0 35.0 TPS6208833YFPT DSBGA YFP 6 250 210.0 185.0 35.0 TPS62088YFPR DSBGA YFP 6 3000 210.0 185.0 35.0 TPS62088YFPT DSBGA YFP 6 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 2-May-2019 Pack Materials-Page 2

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Product Information

XPS62088YWCR specifications and overview.

Summary

2.4-V to 5.5-V Input, Tiny 6-pin 3-A Step-Down Converter in 1.2-mm x 0.8-mm Wafer Chip Scale Package

Description

2.4-V to 5.5-V Input, Tiny 6-pin 3-A Step-Down Converter in 1.2-mm x 0.8-mm Wafer Chip Scale Package

Source title XPS62088YWCR Datasheet(PDF) - Texas Instruments

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