XPS546A24ARVFR

TPS546A24A TI1 | Alldatasheet

Document overview

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Technical content

BCX_CLK BCX_DAT PMB_CLK PMB_DATA SYNC SMB_ALRT VSHARE VDD5 PGND SW BOOT GOSNS/SLAVE VOSNS VOUT AGND PGD/RST_B To Loop Slaves To PMBus TPS546B24A ADVANCE□INFORMATION Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS546A24A SLUSE16 –FEBRUARY 2020 TPS546A24A2.95-Vto18-V,10-A,upto4×Stackable,PMBus®BuckConverter

1 Features

1• Split rail support: 2.95-V to 18-V PVIN; 2.95-V to 18-V AVIN (4-VIN VDD5 for switching)

• Integrated 5.5-mΩ/1.8-mΩ MOSFETs
• Average current mode control with selectable internal compensation
• 2×, 3x, 4× stackable with current sharing up to 40 A, supporting a single address per output
• Selectable 0.6-V to 5.5-V output via pin strap or 0.25-V to 6.0-V using PMBus VOUT_COMMAND
• Extensive PMBus command set with telemetry for VOUT, IOUT and internal die temperature
• Differential remote sensing with internal FB divider for < 1% VOUT error –40°C to +150°C TJ
• AVS and margining capabilities through PMBus
• MSEL pins pin programming PMBus defaults
• 12 Selectable switching frequencies from 225 kHz to 1.5 MHz (8 pin-strap options)
• Frequency sync in/sync out
• Supports prebiased output
• Supports strongly coupled inductor
• 7 mm × 5 mm × 1.5 mm, 40-pin QFN, Pitch = 0.5 mm
• Create a Custom Design Using the TPS546A24A With WEBENCH® Power Designer

2 Applications

• Data center switches, rack servers
• Active antenna system, remote radio and baseband unit
• Automated test equipment, CT, PET, and MRI
• ASIC, SoC, FPGA, DSP core, and I/O voltage

3 Description

The TPS546A24A is a highly integrated, non-isolated DC/DC converter capable of high frequency operation and 10-A current output from a 7-mm × 5-mm package. Two, three, and four TPS546A24A devices can be interconnected to provide up to 40 A on a single output. The device has an option to overdrive the internal 5-V LDO with an external 5-V supply via the VDD5 pin to improve efficiency and reduce power dissipation of the converter. The TPS546A24A uses a proprietary fixed-frequency current-mode control with input feedforward and selectable internal compensation components for minimal size and stability over a wide range of output capacitances. The PMBus interface with 1-MHz clock support gives a convenient, standardized digital interface for converter configuration as well as monitoring of key parameters including output voltage, output current, and internal die temperature. Response to fault conditions can be set to restart, latch off, or ignore, depending on system requirements. Back-channel communication between stacked devices enables all TPS546A24Aconverters powering a single output rail to share a single address to simplify system software/firmware design. Key parameters including output voltage, switching frequency, soft-start time, and overcurrent fault limits can also be configured through BOM selection without PMBus communication to support program free power-up. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS546A24A LQFN-CLIP (40) 7.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Table of Contents 9.3 Mounting and Thermal Profile Recommendation.. 147

10.2 Receiving Notification of Documentation

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES February 2020 * Advance Information release

ADVANCE□INFORMATION Thermal Pad 1PGD/RST_B 2PMB_DATA 3PMB_CLK 4BP1V5 5DRTN 6SMB_ALRT 7BOOT 8SW 9SW 10SW 11SW 12SW 13PGND 14PGND 15PGND 16PGND 17PGND 18PGND 19PGND 20PGND

21 PVIN

22 PVIN

23 PVIN

24 PVIN

25 PVIN

26 AVIN

27 EN/UVLO

28 VDD5

29 MSEL2

30 VSEL

31 ADRSEL

32 MSEL133 VOSNS

35 VSHARE

37 AGND

38 SYNC

39 BCX_CLK

40 BCX_DAT

33 GOSNS/SLAVE

www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

5 Pin Configuration and Functions

40-Pin LQFN-CLIP With Exposed Thermal Pad Top View Pin Functions PIN I/O DESCRIPTION NO. NAME

1 PGD/RST_B I/O

Open-drain power good or (21h) VOUT_COMMAND RESET#, As determined by user programmable RESET# bit in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS). The default pin function is an open drain power-good indicator. When configured as RESET#, and internal pull-up can be enabled or disable by the PULLUP# bit in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS) 2 PMB_DATA I/O PMBus DATA pin. See PMBus specification. 3 PMB_CLK I PMBus CLK pin. See PMBus specification.

4 BP1V5 O

Output of the 1.5-V internal regulator. This regulator powers the digital circuitry and should be bypassed with a minimum of 1 µF to DRTN with an X5R or better ceramic capacitor rated for a minimum of 6V. BP1V5 is not designed to power external circuit. 5 DRTN — Digital bypass return for bypass capacitor for BP1V5. Internally connected to AGND. Do not Connect to PGND or AGND. 6 SMB_ALRT O SMBus alert pin. See SMBus specification.

7 BOOT I

Bootstrap pin for the internal flying high side driver. Connect a typical 100 nF X5R or better ceramic capacitor rated for a minimum of 10V from this pin to SW. To reduce the voltage spike at SW, an optional BOOT resistor of up to 8 Ω may be placed in series with the BOOT capacitor to slow down turn- on of the high-side FET.

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NO. NAME SW I/O Switched power output of the device. Connect the output averaging filter and bootstrap to this group of pins. PGND — Power stage ground return. These pins are internally connected to the thermal pad. PVIN I Input power to the power stage. Low-impedance bypassing of these pins to PGND is critical. PVIN to PGND should be bypassed with X5R or better ceramic capacitors rated for at least 1.5x the maximum PVIN voltage. In addition, a minimum of 1 0402 2.2nF - 10nF X7R or better ceramic capacitance rated for at least 1.5x the maximum PVIN voltage should placed as close to the PVIN and PGND pins, or under the PVIN pins to reduce the high-frequency bypass impedance.

26 AVIN I

Input power to the controller. Bypass with a minimum 1-µF X5R or better ceramic capacitor rated for at least 1.5x the maximum AVIN voltage to AGND. If AVIN is connected to the same input as PVIN or VDD5, a minimum 10-µs R-C filter between PVIN or VDD5 and AVIN is recommended to reduce switching noise on AVIN. 27 EN/UVLO I Enable switching as the PMBus CONTROL pin. EN/UVLO can also be connected to a resistor divider to program input voltage UVLO.

28 VDD5 O

Output of the 5-V internal regulator. This regulator powers the driver stage of the controller and should be bypassed with a minimum of 4.7 µF X5R or better ceramic capacitor rated for a minimum of 10V to PGND at the thermal pad. Low impedance bypassing of this pin to PGND is critical.

29 MSEL2 I

Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of soft-start time, overcurrent fault limit, and multi-phase information. See Programming MSEL2 section or Programming MSEL2 for a Slave Device (GOSNS tied to BP1V5)if GOSNS is tied to BP1V5. 30 VSEL I Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of internal voltage feedback divider and default output voltage. See Programming VSEL section.

31 ADRSEL I

Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of PMBus addresses and frequency sync (including determination of SYNC pin as SYNC IN or SYNC OUT function). See Programming ADRSEL section.

32 MSEL1 I

Connect this pin to a 1% tolerance or better resistor divider between BP1V5 and AGND for different options of switching frequency and internal compensation parameters. See Programming MSEL1 section.

33 VOSNS I

The positive input of the remote sense amplifier. For a standalone device or the loop master device in a multi-phase configuration, connect VOSNS pin to the output voltage at the load. For the loop slave device in a multi-phase configuration, the remote sense amplifier is not required for output voltage sensing or regulation and this pin may be left floating. If used to monitor another voltage with the Phased READ_VOUT command, VOSNS should be maintained between 0V and 0.75V with a <1kΩ resistor divider due to the internal resistance to GOSNS, which is connected to BP1V5.

34 GOSNS/SLAVE I

The negative input of the remote sense amplifier for loop master device or should be pulled up high to indicate loop slave. For standalone device or the loop master device in a multi-phase configuration, connect GOSNS pin to the ground at the load. For the loop slave device in a multi-phase configuration, the GOSNS pin must be pulled up to BP1V5 to indicate the device a loop slave. 35 VSHARE I/O Voltage sharing signal for multi-phase operation. For standalone device, the VSHARE pin must be left floating. VSHARE can by bypassed to AGND with upto 50pF of capacitance. 36 NC - Not internally connected. Connect to PGND at the thermal pad. 37 AGND - Analog ground return for controller. Connect the AGND pin directly to the thermal pad on the PCB board.

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NO. NAME

38 SYNC I/O

For frequency synchronization, can be programmed as SYNC IN or SYNC OUT pin by ADRSEL pin or the (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG) PMBus Command. The SYNC pin can be left floating when not used. 39 BCX_CLK I/O Clock for back-channel communications between stacked devices. 40 BCX_DAT I/O Data for back-channel communications between stacked devices. — Thermal pad — Package thermal pad, internally connected to PGND. The thermal pad must have adequate solder coverage for proper operation. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage PVIN –0.3 18 V Input voltage PVIN –0.3 16 V Input voltage PVIN, < 2-ms transient –0.3 19 V Input voltage PVIN – SW (PVIN to SW differential) –0.3 24 V PVIN – SW (PVIN to SW differential, < 10-ns transient because of SW ringing) –5 24 Input voltage AVIN –0.3 20 V BOOT –0.3 35 V BOOT – SW (BOOT to SW differential) –0.3 5.5 V EN/UVLO, VOSNS, SYNC, VSEL, MSEL1, MSEL2, ADRSEL –0.3 5.5 V VSHARE, GOSNS/SLAVE –0.3 1.98 V PMB_CLK, PMB_DATA, BCX_CLK, BCX_DAT –0.3 5.5 V Output voltage SW –1 24 V Output voltage SW < 10-ns transient –5 24 V Output voltage VDD5, SMB_ALRT, PGD/RST_B –0.3 5.5 V BP1V5 –0.3 1.65 V TJ operating junction temperature –40 150 °C Tstg Storage temperature –55 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. . (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VAVIN Controller input voltage 2.95 12 18 V VPVIN Power stage input voltage 2.95 12 18 V VPVIN Power stage input voltage 2.95 12 16 V VSW(peak) Peak Switch Node Voltage with respect to PGND 18 V TJ Junction temperature –40 150 °C

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, spra953. (2) EVM thermal resistance measured on TPS546D24AEVM-2PH. 8-layer, 2-oz Cu per layer evaluation board.

6.4 Thermal Information

THERMAL METRIC(1) TPS546X24A UNITPQFN (RVF)

40 PINS

RθJA Junction-to-ambient thermal resistance JEDEC 28.9 °C/W RθJA Junction-to-ambient thermal resistance EVM(2) 8.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.9 °C/W RθJB Junction-to-board thermal resistance 4.1 °C/W ψJT Junction-to-top characterization parameter 1.3 °C/W ψJB Junction-to-board characterization parameter 4.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.0 °C/W (1) Specified by design. Not production tested.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VAVIN Input supply voltage range 2.95 16 V VPVIN Power stage voltage range 2.95 16 IAVIN Input operating current Converter not switching 12.5 17 mA AVIN UVLO VAVINuvlo Analog input voltage UVLO for power on reset (PMBus communication) enable threshold 2.5 2.7 V Analog input voltage UVLO for disable 2.09 2.3 V Analog input voltage UVLO hysteresis 250 mV tdelay(uvlo_PMBus) Delay from AVIN UVLO to PMBus ready to communicate AVIN = 3 V 8 ms PVIN UVLO VIN_ON Power input turn on voltage Factory default setting 2.75 VProgrammable range 2.75 15.75 Resolution 0.25 Accuracy –5% 5% VIN_OFF Power input turnoff voltage Factory default setting 2.5 VProgrammable range 2.5 15.5 Resolution 0.25 Accuracy –5% 5% ENABLE AND UVLO VENuvlo EN/UVLO Voltage rising threshold 1.05 1.1 V EN/UVLO Voltage falling threshold 0.9 VENhys EN/UVLO Voltage hysteresis No external resistors on EN/UVLO 70 mV IENhys EN/UVLO hysteresis current VEN/UVLO = 1.1 V 4.5 5.5 6.5 uA EN/UVLO hysteresis current VEN/UVLO = 0.9 V -100 -5 nA REMOTE SENSE AMPLIFIER ZRSA Remote sense input impedance VOSNS – GOSNS = 1V VOSNS to GOSNS 85 130 165 kΏ VIRNG(GOSNS) GOSNS input range for regulation accuracy (1) VOSNS – GOSNS = 1V, VOUT_SCALE_LOOP ≤ 0.5 –0.05 0.05 V VIRNG(VOSNS) VOSNS input range for regulation accuracy (1) GOSNS = AGND, VOUT_SCALE_LOOP ≤ 0.5 –0.1 5.5 V

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) The parameter covers 2.95 V to 18 V of AVIN. REFERENCE VOLTAGE AND ERROR AMPLIFIER VREF Reference voltage(1) Default setting 0.4 V Reference voltage range(1) 0.25 0.75 V Reference voltage resolution(1) 2 –12 V VOUT(ACC) Output voltage accuracy VOUT = 1000 mV 0.992 1.008 V VOUT = 500 mV 0.492 0.508 V VOUT = 1500 mV 1.490 1.510 V VOUT = 1000 mV 0.994 1.006 V VOUT = 500 mV 0.494 0.506 V VOUT = 1500 mV 1.492 1.508 V VOUT = 1000 mV 0°C ≤ TJ ≤ 85°C(2) 0.995 1.005 V VOUT = 500 mV 0.495 0.505 V VOUT = 1500 mV 1.493 1.507 V GmEA Progrmmable error amplifier transonductance 25 200 µS Resolution(1) Four settings: 25 uS, 50 uS, 100 uS, 200 uS 25 Unloaded Bandwidth(1) 8 MHz RpEA Programmable parallel resistor range 5 315 kΩ Resolution(1) 5 CintEA Programmable integrator capacitor range 1.25 18.75 pF Resolution(1) 1.25 pF CpEA Programmable parallel capacitor range 6.25 193.75 pF Resolution(1) 6.25 CURRENT GM AMPLIFIER GmBUF Progrmmable current error amplifier transonductance 25 200 µS Resolution(1) Four settings: 25 µS, 50 µS, 100 µS, 200 µS 25 Unloaded bandwidth(1) 17 MHz RpBUF Programmable parallel resistor range 5 315 kΩ Resolution(1) 5 RintBUF Programmable integrator resistor range(1) 800 1600 kΩ Resolution(1) 800 CintBUF Programmable integrator capacitor range 0.3125 4.6875 pF Resolution(1) 0.3125 CpBUF Programmable parallel capacitor range 3.125 96.875 pF Resolution(1) 3.125 OSCILLATOR fSW Adjustment range(2) 225 1500 kHz Switching frequency(2) 500 550 600 SYNCHRONIZATION VIH(sync) High-level input voltage 1.35 V VIL(sync) Low-level input voltage 0.8 tpw(sync) Sync input iminimum pulse width fsw = 225 kHz to 1500 kHz 200 ns

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (3) Not production tested. Guaranteed by correlation. AVIN = PVIN = 12 V, VOUT = 1 V fsw = 325kHz L = 320nH (4) The setting of TON_RISE and TOFF_FALL of 0 ms means the unit to bring its output voltage to the programmed regulation value of down to 0 as quickly as possible, which results in an effective TON_RISE and TOFF_FALL time of 0.5 ms (fastest time supported). ΔfSYNC SYNC pin frequency range from FREQUENCY_SWITCH frequency(1) –20 20 % VOH(sync) Sync output high voltage 100-μA load VDD5 –0.85V VDD5 V VOL(sync) Sync output low voltage 2.4-mA load 0.4 V tPLL PLL lock time Fsw = 550 kHz, SYNC clock frequency 495 kHz - 605 kHz(1) 65 μs PhaseErr Phase interleaving error(3) fsw < 1.1 MHz 9 Degree fsw ≥1.1 MHz 23 ns RESET VIH(reset) High-level input voltage(1) 1.35 V VIL(reset) Low-level input voltage 0.8 tpw(reset) Minimum RESET_B pulse width 200 ns Rpullup(reset) Internal pull-up resistance VRESET = 0.8V RESET# = 1 25 34 55 kΩ Vpullup(reset) Internal Pull-up Voltage IRESET = 10 μA RESET# = 1 VDD5 - 0.5 V VDD5 REGULATOR VVDD5 Regulator output voltage Default, IVDD5 = 10 mA 4.5 4.7 4.9 V Programmable range(1) 3.9 5.3 V Resolution 200 mV VVDD5(do) Regulator dropout voltage VAVIN – VVDD5, VAVIN = 4.5 V, IVDD5 = 25 mA 130 285 mV IVDD5SC Regulator short-circuit current(1) VAVIN = 4.5 V 100 mA VVDD5ON(IF) Enable voltage on VDD5 for pin- strapping 2.62 2.85 V VVDD5OFF(IF) Disable voltage on VDD5 for pin- strapping 2.25 2.48 V VVDD5ON(SW) Switching enable voltage upon VDD5 4.05 V VVDD5OFF(SW) Switching disable voltage upon VDD5 3.10 V VVDD5UV(hyst) Regulator UVLO voltage hysteresis 400 mV BOOTSTRAP VBOOT(drop) Bootstrap voltage drop IBOOT = 20 mA, VDD5 = 4.5 V 225 mV BP1V5 REGULATOR IBP1V5SC 1.5-V regulator short-circuit current(1) 30 mA PWM tON(min) Minimum controllable pulse width(1) 20 ns tOFF(min) PWM Minimum off-time(1) 400 500 ns SOFT START tON_RISE Soft-start time Factory default setting 3 msProgrammable range(1)(4) 0 31.75 Resolution 0.25 Accuracy, TON_RISE = 3 ms –10% 15%

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (5) The setting of TON_MAX_FAULT_LIMIT and TOFF_MAX_WARN_LIMIT of 0 means disabling TON_MAX_FAULT and TOFF_MAX_WARN response and reporting completely. tON_MAX_FLT_LT Upper limit on the time to power up the output Factory default setting(5) 0 msProgrammable range(1)(5) 0 127.5 Resolution 0.5 Accuracy(1) –10% 15% tON_DELAY Turn-on delay Factory default setting 0 msProgrammable range(1) 0 127.5 Resolution 0.5 Accuracy(1) –10% 15% SOFT STOP tOFF_FALL Soft-stop time Factory default setting(4) 0.5 msProgrammable range(1) (4) 0 31.75 Resolution 0.25 Accuracy, TOFF_FALL = 1 ms –10% 15% tOFF_DELAY Turn-off delay Factory default setting 0 msProgrammable range(1) 0 127.5 Resolution 0.5 Accuracy(1) –10% 15% VPVINOVF Power Input overvoltage fault limit Factory default 20 VProgrammable range 6 20 Resolution 1 VPVINUVW Power Input undervoltage warning limit Factory default 2.5 VProgrammable range 2.5 15.75 Resolution 0.25 POWER STAGE RHS High-side power device on- resistance VBOOT - VSW = 4.5V, TJ = 25°C 5.5 mΩ VBOOT - VSW = 3 V, TJ = 25°C TBD mΩ RLS Low-side power device on- resistance VVDD5 = 4.5 V, TJ = 25°C 1.8 mΩ VVDD5 = 3 V, TJ = 25°C TBD mΩ Rswpd SW internal pull-down resistance 3 30 35 kΩ Vwkdr(on) Weak high-side gate drive triggering threshold upon PVIN rising 14.75 V Vwkdr(off) Weak high-side gate drive recovering threshold upon PVIN falling 14.35 V tDEAD(LtoH) Power stage driver dead-time from Low-side off to High-side on VVDD5 = 4.5 V, TJ = 25°C(1) 6 ns tDEAD(HtoL) Power stage driver dead-time from High-side off to Low-side on VVDD5 = 4.5 V, TJ = 25°C(1) 6 ns CURRENT SHARING VVSHARE VSHARE fault trip threshold 0.1 V VSHARE fault release threshold 0.2 LOW-SIDE CURRENT LIMIT PROTECTION tOFF(OC) Off time between restart attempts(1) Factory default setting 7 × tON_RISE ms Range 1 × tON_RISE 7 × tON_RISE

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO_OC_FLT_LM T Output current overcurrent fault threshold Factory default setting 14 A IO_OC_FLT_LM T Output current overcurrent fault threshold Programmable range 4 23 A IO_OC_FLT_LM T Output current overcurrent fault threshold Resolution 1 A INEGOC Negative output current overcurrent protection threshold –10 A IO_OC_WRN_L MT Output current overcurrent warning threshold Factory default setting 10 A Programmable range 4 23 A Resolution 1 A IHSOC Output current overcurrent fault accuracy IOUT = 10 A –1 2 A IOUT = 20 A(3) –2 4

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HIGH-SIDE SHORT CIRCUIT PROTECTION IHSOC Ratio of High-side short-circuit protection fault threshold over Low-side overcurrent limit High-side current sense blanking time 100 ns POWER GOOD (PGOOD) AND OVERVOLTAGE/UNDERVOLTAGE WARNING RPGD PGD pulldown resistance IPGD = 5 mA 30 50 Ω IPGD(OH) Output high open drain leakage current into PGD pin VPGD = 5 V 15 µA VPGD(OL) PGD pin output low level voltage at no supply voltage VAVIN = 0, IPGD = 80 μA 0.8 V VOVW Overvoltage warning threshold (PGD threshold on VOSNS rising) Factory default, at VOUT_COMMAND (VOC) = 1 V 106% 110% 114% VOC Range 103% 116% Resolution 1% VUVW Undervoltage warning threshold (PGD threshold on VOSNS falling) Factory default, at VOUT_COMMAND (VOC) = 1 V 86% 90% 94% Range 84% 97% Resolution 1% VPGD(rise) PGD release threshold on VOSNS rising and undervoltage warning de-assertion threshold Factory default, at VOUT_COMMAND (VOC) = 1 V 95% VPGD(fall) PGD threshold on VOSNS falling and overvoltage warning de- assertion threshold Factory default, at VOUT_COMMAND (VOC) = 1 V 105% OUTPUT OVERVOLTAGE AND UNDERVOLTAGE FAULT PROTECTION VOVF Overvoltage fault threshold Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND (VOC) = 1 V 111% 115% 119% VOC Range Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND (VOC) = 1 V 105% 140% Resolution Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND (VOC) = 1 V 2.5% VUVF Undervoltage fault threshold Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND = 1.00 V 81% 85% 89% Range Factory default, at VOUT_COMMAND = 1.00 V Factory default, at VOUT_COMMAND = 1.00 V 60% 95% Resolution Factory default, at VOUT_COMMAND = 1.00 V Factory default, at VOUT_COMMAND = 1.00 V 2.5% VOVF(fix)OFF Fixed overvoltage fault threshold Factory default, at VOUT_COMMAND (VOC) = 1 V Factory default, at VOUT_COMMAND = 1.00 V 1.15 1.2 1.25 V Recovery threshold(1) Factory default, at VOUT_COMMAND = 1.00 V Factory default, at VOUT_COMMAND = 1.00 V 0.4 OUTPUT VOLTAGE TRIMMING VOUTRES Default Resolution of VOUT_COMMAND, Trim and Margin, VOUT_SCALE_LOOP = 0.5 1.90 1.95 2.00 mV Programmable range(1) 2–12 2 –5 V VOUT_TRAN_R T Output voltage transition rate Factory default setting 1 mV/µs Programmable range(1) 0.063 15.933 Accuracy –10% 10%

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT_SCL_LP Feedback loop scaling factor(1) Factory default setting 0.5 Programmable range, 4 discrete settings 0.125 1 VOUT_CMD Output voltage programmable values Factory default setting 0.8 V Programmable range VOUT_SCALE_LOOP = 1 (3) 0.25 0.75 V VOUT_SCALE_LOOP = 0.5 0.25 1.5 VOUT_SCALE_LOOP = 0.25(3) 0.25 3 VOUT_SCALE_LOOP = 0.125(3) 0.25 6

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) TJ = –40°C to 150°C, VPVIN = VAVIN= 12 V, fSW = 550 kHz; zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE SENSE AND THERMAL SHUTDOWN TSD Bandgap thermal shutdown temperature(1) 150 170 THYST Bandgap thermal shutdown hysteresis(1) 25 OT_FLT_LMT Internal overtemperature fault limit(1) Factory default setting 150 Programmable range 0 160 Resolution 1 OT_WRN_LMT Internal overtemperature warning limit(1) Factory default setting 125 Programmable range 0 160 Resolution 1 TOT(hys) Internal overtemperature fault, warning hysteresis(1) Factory default setting 25 MEASUREMENT SYSTEM MVOUT(rng) Output voltage measurement range(1) 0 6 V MVOUT(acc) Output voltage measurement accuracy 250 mV < VOUT < 6 V –2% 2% MVOUT(lsb) Output voltage measurement bit resolution(1) 244 µV MIOUT(rng) Output current measurement range(1) –5 30 A MIOUT(acc) Output current measurement accuracy(3) IOUT ≤ 5 A, TJ = 25°C –1 0 1 A MIOUT(acc) Output current measurement accuracy(3) IOUT = 10A, -40°C ≤ TJ ≤ 150°C –1.5 0 1.5 A MIOUT(acc) Output current measurement accuracy(3) IOUT = 10A, 0°C ≤ TJ ≤ 85°C –1.3 0 1.3 A MIOUT(lsb) Output current measurement bit resolution(1) 2–6 A MPVIN(rng) Input voltage measurement range(1) 0 20 V MPVIN(acc) Input voltage measurement accuracy 4 V< PVIN < 20 V –3 3 % MPVIN(lsb) Input voltage measurement bit resolution(1) 2–6 V MTSNS(acc) Internal temperature sense accuracy(3) –40°C ≤ TJ ≤ 150°C –3 3 MTSNS(lsb) Internal temperature sense bit resolution(1) 0.25 PMBUS INTERFACE + BCX VIH(PMBUS) High-level input voltage on PMB_CLK, PMB_DATA, BCX_CLK, BCX_DAT 1.35 V VIL(PMBUS) Low-level input voltage on PMB_CLK, PMB_DATA, BCX_CLK, BCX_DAT 0.8 IlH(PMBUS) Input high level current into PMB_CLK, PMB_DATA –10 10 μA IIL(PMBUS) Input low level current into PMB_CLK, PMB_DATA –10 10 μA VOL(PMBUS) Output low level votlage on PMB_DATA, SMB_ALRT, BCX_DAT VAVIN > 4.5 V, input current to PMB_DATA, SMB_ALRT, BCX_DAT = 20 mA 0.4 V IOH(PMBUS) Output high level open drain leakage current into PMB_DATA, SMB_ALRT Voltage on PMB_DATA, SMB_ALRT = 5.5 V 10 μA

6.6 Typical Characteristics

Texas Instruments evaluation module (EVM). Figure 1. TPS546A24A Safe Operating Area Figure 2. TPS546A24A Safe Operating Area Figure 3. TPS546A24A Safe Operating Area Figure 4. TPS546A24A Safe Operating Area Figure 5. TPS546A24A Safe Operating Area Figure 6. TPS546A24A Safe Operating Area Figure 7. TPS546A24A Safe Operating Area Figure 8. TPS546A24A Safe Operating Area Figure 9. TPS546A24AEfficiency vs Output Current Figure 10. TPS546A24AEfficiency vs Output Current Figure 11. TPS546A24AEfficiency vs Output Current Figure 12. TPS546A24AEfficiency vs Output Current

ADVANCE□INFORMATION AVIN SW PGND VDD5 Driver Control Anti-Cross- Conduction Pre-Bias BOOT SYNC BP1V5 VDD5 VSEL VOSNS ADC, PMBus Interface, Back Channel Interface, Memory PMB_CLK PMB_DATA SMB_ALRT BCX_CLK AGND PGD/RST_B Error Amplifier with Internal Compensation PWM ADRSEL Linear Regulators GOSNS/SLAVE DRTN Oscillator PLL EN/UVLO On-Time Generator PVIN Soft-Start DAC MSEL2 VOUT/UV/OV Detection BCX_DAT Output Current Sensing VSHARE MSEL1 Decoder (SS, OC, Phase Count) Decoder (Addr, PH Pos, Det SYNC in/out) Decoder (Vref, Divider Ratio) Die Temp Sensing To Infrastructure To Infrastructure & Selectable Divider Ratio MSEL2/PMBus IMON VMON & OV/UV SYNC_ OUT SYNC _IN Slave Detection RESET Vout Auto-detection/ PMBus Fault Management BP1V8 PVIN UVLO Decoder (Fsw, Comp) TMON TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPS546A24A uses a fixed-frequency, proprietary current-mode control. The switching frequency can be selected from pre-set values through pin-strapping and PMBus programming. The output voltage is sensed through a true differential remote sense amplifier, and internal resistor divider, then compared to an internal voltage reference by an error amplifier. An internal oscillator initiates the turn-on of the high-side power switch. The error amplifier output is buffered and shared via VSHARE among stacked devices. This shared voltage is compared to the sensed switch node current to drive a linear voltage ramp modulator with input voltage, output voltage, and switching frequency feed-forward, to regulate the average switch-node current. As a synchronous buck converter, the device normally works in continuous conduction mode (CCM) under all load conditions. The compensation components are integrated into the TPS546A24A devices, and programmable via the PMBus command (B1h) USER_DATA_01 (COMPENSATION_CONFIG) or with the external pin MSEL1 to select pre-set values based on switching frequency and output LC filters.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Average Current-Mode Control

customers can use the SLUC686 design tool. Figure 23. Average Current Mode Control Block Diagram

7.3.1.1 On-Time Modulator

ADVANCE□INFORMATION MB SW OUT

1 CSAVLOOP GMV RVV fVOUT _ SCALE _LOOP Z 10

u u ·§ ¨ ¸ © ¹ OUT 1VOUT _ SCALE _ LOOP VLOOP Z ¦ 1A¦ CSu u u coi ramp MB PVIN V 1.7ILOOP GMI RVI L V CSA ¦ u u u uSu PVIN ramp V 1ILOOP CSA 1V¦ ¦ / 1.7u u Su uu u TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Feature Description (continued)

7.3.1.2 Current Error Integrator

The current error integrator adjusts the modulator control voltage to match the sensed inductor current, Isns to the current voltage at the VSHARE pin. The integrator is tuned through the GMI, RVI, CZI, CPI, and CZI_MUL parameters in (B1h) USER_DATA_01 (COMPENSATION_CONFIG). Thanks to the natural integration of the 1/f function of the current control gain, the bandwidth of the current control loop can be adjusted with the mid-band gain of the integrator, GMI × RVI. The current loop crossover occurs at the frequency when the full loop gain is equal to 1 according to Equation 3: (3) Solving for the mid-band gain of the current loop, we find Equation 4: (4) While Nyquist Theorem suggests that a bandwidth of ½ fSW is possible, inductor tolerances and phase delays in the current sense, modulator, and H-bridge power FETs make fSW/4 a more practical target, which simplifies the target current loop midband gain to achieve a current loop bandwidth of fSW/4 to Equation 5: (5) An integrator from DC to the low-frequency zero, RVI × CZI, compensates for the valley voltage of the modulator ramp and the nominal offset of the output voltage. A high-frequency filter pole, RVI × CPI between half the switching frequency and the switching frequency reduces high-frequency noise from VSHARE and minimizes pulse-width jitter. In order to avoid loop interactions, the integrating zero frequency should be below the voltage loop cross-over frequency, while the high-frequency pole should be between ½ the switching frequency and the switching frequency to limit high-frequency noise and jitter in the current loop without imposing additional phase loss in the voltage loop. The closed loop average current mode control allows the current sense amplifier, on-time modulator, H-bridge power FETs and inductor to operate as a transconductance amplifier with forward gain of 1/CSA or 81.25 A/V with a bandwidth equal to Fcoi.

7.3.1.3 Voltage Error Integrator

The voltage error integrator regulates the output voltage by adjusting the current control voltage, VSHARE, similar to any current mode control architecture. A transconductance amplifier compares the sense feedback voltage to a programmed reference voltage to set the current control voltage VSHARE to maintain the desired output voltage. While a regulated current source feeding an output capacitance provides a natural, stable, integrator, mid-band gain is often desired to improve the loop bandwidth and transient response. With a transconductance set by the current sense gain, the voltage loop cross-over occurs when the full loop gain equal 1 according to Equation 6 (6) In order to prevent the current integration loop bandwdith from negatively impacting the phase margin of the voltage loop, the voltage loop should have a target bandwidth of Fcoi / 2.5. With a current mode loop of fSW/4, the voltage loop mid-band gain should be Equation 7: (7) An integrator pole is necessary to maintain accurate DC regulation, and the zero-frequency set by RVV × CZV should be set below the lowest cross-over frequency with the largest output capacitor intended to be supported at the output, but not more than 1/2 the target voltage loop crossover frequency fcov.

2.95 V ± 18 V

4.25 V ± 18 V

with a high-frequency pole set by RVV × CPV should be set between fsw/4 and fsw. For PMBus programming of compensation values see (B1h) USER_DATA_01 (COMPENSATION_CONFIG).

7.3.2 Linear Regulators

for details. Poor bypassing can degrade the performance of the regulator. regulators might adversely affect operation of the controller.

7.3.3 AVIN and PVIN Pins

AVIN bypass capacitor between AVIN and PVIN to reduce PVIN switching noise on the AVIN input. Figure 24. TPS546A24A Separate PVIN and AVIN connections

Figure 25. TPS546A24A Separate PVIN and AVIN connections with VDD5 Figure 26. TPS546A24A Separate PVIN, AVIN, and VDD5 connections

7.3.4 Input Undervoltage Lockout (UVLO)

The TPS546A24A provides 4 independent UVLO functions for the broadest range of flexibility in start-up control. TEMPERATURE monitoring, all 4 UVLO functions must be met before switching can be enabled.

7.3.4.1 Fixed AVIN UVLO

power on reset, including pin detection. The off-threshold on AVIN is 2.3 V (typ).

7.3.4.2 Fixed VDD5 UVLO

conversion. The off threshold on VDD5 is 3.5 V.

7.3.4.3 Programmable PVIN UVLO

switches between enabled and disabled while PVIN remains below (36h) VIN_OFF. TON_RISE and (65h) TOFF_FALL in such conditions.

7.3.4.4 EN/UVLO Pin

output is not enabled until PMBus programming has been completed. Figure 27. TPS546A24A UVLO Voltage Divider

7.3.5 Start-Up and Shutdown

Supported PMBus Commands for full details on the implementation.

Figure 28. TPS546A24A Start-up and Shutdown tdelay(uvlo_PMBus), TON_DELAY will start after tdelay(uvlo_PMBus) completes.

7.3.6 Differential Sense Amplifier and Feedback Divider

the selectable feedback divider and precision adjustable reference, output voltages up to 6.0 V can be obtained. Table 1. (29h) VOUT_SCALE_LOOP and (21h)

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Setting (21h) VOUT_COMMAND lower than the recommended range can negatively affect VOUT regulation accuracy while setting (21h) VOUT_COMMAND above the recommended range may limit the actual output voltage achieved. NOTE If the regulation output voltage is limited by the recommended range of the current (29h) VOUT_SCALE_LOOP value, VOUT may be below the intended (43h) VOUT_UV_WARN_LIMIT or (44h) VOUT_UV_FAULT_LIMIT without triggering their respective faults due to the limited range of the reference voltage.

7.3.7 Set Output Voltage and Adaptive Voltage Scaling (AVS)

The initial output voltage can be set by the VSEL pin at AVIN power up. As part of power-on reset (POR), the VSEL pin senses both the resistance from the VSEL pin to AGND and the divider ratio of the VSEL pin between B1V5 and AGND. These values program (29h) VOUT_SCALE_LOOP, (21h) VOUT_COMMAND, (2Bh) VOUT_MIN and (24h) VOUT_MAX and select the appropriate settings for the internal feedback divider and precision adjustable reference voltage. Once the TPS546A24A completes its POR and enables PMBus communication, these initial values can be changed via PMBus communication.

• VOUT_MODE
• (21h) VOUT_COMMAND
• (29h) VOUT_SCALE_LOOP
• (22h) VOUT_TRIM
• (25h) VOUT_MARGIN_HIGH
• (26h) VOUT_MARGIN_LOW
• (01h) OPERATION
• (02h) ON_OFF_CONFIG The output voltage can be programmed through PMBus and its value is related to the following registers:
• (24h) VOUT_MAX
• (2Bh) VOUT_MIN
• (40h) VOUT_OV_FAULT_LIMIT
• (42h) VOUT_OV_WARN_LIMIT
• (43h) VOUT_UV_WARN_LIMIT
• (44h) VOUT_UV_FAULT_LIMIT The TPS546A24A defaults to the relative format for (25h) VOUT_MARGIN_HIGH, (26h) VOUT_MARGIN_LOW, (40h) VOUT_OV_FAULT_LIMIT, (42h) VOUT_OV_WARN_LIMIT, (43h) VOUT_UV_WARN_LIMIT and (44h) VOUT_UV_FAULT_LIMIT, but can be changed to use absolute format via the PMBus command VOUT_MODE. Refer to the detailed description of VOUT_MODE for details.

7.3.7.1 Reset Output Voltage

The (21h) VOUT_COMMAND value and the corresponding output voltage can be reset to the last selected power-on reset value set by VSEL or EEPROM as selected in the (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE) command when the PGD/RST_B pin function is set to RESET# in the (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS) PMBus command. To reset (21h) VOUT_COMMAND to its last Power- On Reset value, when the RESET# optional function is enabled, assert the PGD/RST_B pin low externally. While RESET# is asserted low, (21h) VOUT_COMMAND values received via PMBus is ACKed but no change in (21h) VOUT_COMMAND is made. When RESET# is selected in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS), an internal pull-up on the PGD/RST_B pin can be selected by the PULLUP# bit in the same PMBus command to eliminate the need for an external pull-up with the RESET# function.

Figure 29. TPS546A24A Output Voltage Reset

7.3.7.2 Soft Start

rate defined by the (61h) TON_RISE command. options) and/or PMBus programming. may be seen and the output may show larger ripple voltage than normal operation.

7.3.8 Prebiased Output Start-Up

disabled by EN/UVLO or the PMBus (01h) OPERATION command.

7.3.9 Soft Stop and (65h) TOFF_FALL Command

voltage slew rate is controlled by the discharge from the external load. This feature is disabled for EN/UVLO in (02h) ON_OFF_CONFIG by default.

turnon and turnoff sequencing.

7.3.11 Set Switching Frequency

and/or PMBus programming (16 options), listed in Table 2. Table 2. Oscillator fSW Options

7.3.12 Frequency Synchronization

Table 3. Pin Programmed Phase Positions through ADRSEL Resistor Divider (Single Phase Stand-

SYNC pin sets the device for SYNC_IN while a consistent pulldown on SYNC sets the device for SYNC_OUT. TPS546A24A devices programmed to be loop slaves are always programmed to be SYNC IN. continues to operate at approximately 50% of the nominal frequency.

7.3.13 Loop Slave Detection

configured as a loop master.

7.3.14 Current Sensing and Sharing

FETs to achieve lossless current sense with no external components. phases. The amplifier output voltage is compared with an internal PWM ramp to generate the PWM pulse.

7.3.15 Telemetry

conversion requires less than 500 µs, allowing each telemetry value to be updated within 2 ms.

7.3.16 Overcurrent Protection

Both low-side overcurrent (OC) and high-side short circuit protection are implemented. exceeds the 1.5× the programmed low-side threshold. defined as part of (47h) IOUT_OC_FAULT_RESPONSE. shutdown, restart, or ignore.

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

7.3.17 Overvoltage/Undervoltage Protection

The voltage on VOSNS pin is monitored to provide output voltage overvoltage (OV) and undervoltage (UV) protection. When VOSNS voltage is higher than OV fault threshold, OV fault is declared, and the low-side FET is turned on to discharge the output voltage and eliminate the OV condition. The low-side FET remains on until the VOSNS voltage is discharged to 200-mV divide by the internal feedback divider as programmed by (29h) VOUT_SCALE_LOOP. Once the output voltage is discharged, the output is disabled, and the converter times out and restarts according to the (41h) VOUT_OV_FAULT_RESPONSE PMBus command. When VOSNS voltage is lower than UV fault threshold, UV fault is declared. After an initial delay programmed by the (45h) VOUT_UV_FAULT_RESPONSE PMBus command, the output is disabled, and the converter times out and restarts according to the (45h) VOUT_UV_FAULT_RESPONSE PMBus command. The output UV/OV fault thresholds and fault response are set through PMBUS. The UV/OV fault response can be set to shutdown, restart, or continue operating without interruption.

7.3.18 Overtemperature Management

There are two schemes of over temperature protections in the TPS546A24A device: 1. On-chip die temperature sensor for monitoring and overtemperature protection (OTP); 2. The bandgap based thermal shutdown (TSD) protection. TSD provides OT fail-safe protection in the event of a failure of the temperature telemetry system, but can be disabled via (50h) OT_FAULT_RESPONSE for high temperature testing. The overtemperature protection (OTP) threshold is set through PMBus and compares the READ_TEMPERATURE1 telemetry to the (51h) OT_WARN_LIMIT, (51h) OT_WARN_LIMIT, and (4Fh) OT_FAULT_LIMIT . The overtemperature (OT) fault response can be set to shutdown, restart, or continue operating without interruption.

7.3.19 Fault Management

configured to shutdown and restart, the second fault will shutdown but may fail to restart as programmed. Table 4. Fault Protection Summary

Table 4. Fault Protection Summary (continued)

7.3.20 Back-Channel communication

error among the devices of a stack will result in a POR fault and prevent enabling of conversion. VOUT_COMMAND to the slave devices to ensure correct operation of the STACK. STATUS information for the full stack of devices. INTERLEAVE command programmed during POR. value back from the same slave.

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

7.3.21 Switching Node (SW)

The SW pin connects to the switching node of the power conversion stage. It acts as the return path for the highside gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the output capacitance (COSS) of both power FETs form a resonant circuit that can produce high frequency (> 100 MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the pin. In many cases, a series resistor and capacitor snubber network connected from the switching node to PGND can be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber network components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin exceeds the limit, then include snubber components.

7.3.22 PMBus General Description

Timing and electrical characteristics of the PMBus interface specification can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.3 available at http://pmbus.org. The TPS546A24A device supports both the 100-kHz, 400-kHz, and 1-MHz bus timing requirements. The TPS546A24A does utilize clock stretching during PMBus communication, but only stretches the clock during specific bits of the transaction.

• The TPS546A24A does not stretch the clock during the address byte of any transaction
• The TPS546A24A may stretch the clock between bit 0 of the command byte and its ACK response
• The TPS546A24A stretches the clock after bit 0 of the read address of a read transaction
• The TPS546A24A stretches the clock between bit 0 of the last byte of data and its ACK response
• The TPS546A24A may stretch the clock between bit 1 and bit zero of every fourth byte of data for blocks with more than 4 bytes of data Communication over the PMBus interface can either support the packet error checking (PEC) scheme or not. If the master supplies clock (CLK) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used. If PEC will always be used, consider enabling Require PEC in (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS) to configure the TPS546A24A to reject any write transaction that does not include CLK pulses for a PEC byte. The device supports a subset of the commands in the PMBus 1.3 Power Management Protocol Specification. See Supported PMBus Commands for more information The TPS546A24A also supports the SMB_ALERT response protocol. The SMB_ALERT response protocol is a mechanism by which the TPS546A24A can alert the bus master that it has experienced an alert and has important information for the host. The host should process this event and simultaneously accesses all slaves on the bus that support the protocol through the alert response address. All slaves that are asserting SMB_ALERT should acknowledge this request with their PMBus Address. The host performs a modified receive byte operation to get the slave’s address. At this point, the master can use the PMBus status commands to query the slave that caused the alert. For more information on the SMBus alert response protocol, see the system management bus (SMBus) specification. The TPS546A24A contains non-volatile memory that is used to store configuration settings and scale factors. The settings programmed into the device are not automatically saved into this non-volatile memory. The (15h) STORE_USER_ALL command must be used to commit the current PMBus settings to non-volatile memory as device defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed descriptions. All pin programmable values can be committed to non-volatile memory. The POR default selection between pin programmable values and non-volatile memory can be selected by the manufacturer specific (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE) command.

7.3.23 PMBus Address

The PMBus specification requires that each device connected to the PMBus have a unique address on the bus. The TPS546A24A PMBus address is determined by the value of the resistor connected between ADRSEL and AGND and is programmable over the range from 0x10 – 0x2F, providing 32 unique PMBus addresses.

7.3.24 PMBus Connections

on PMB_CLK, PMB_DATA, and SMB_ALRT.

7.4 Device Functional Modes

7.4.1 Programming Mode

(15h) STORE_USER_ALL command must not be used when VDD5 is less than 3 V. supply without PVIN present.

7.4.2 StandAlone/Master/Slave Mode Pin Connections

the recommended pin connects for each configuration is given in Table 5. Table 5. Stand-Alone/Master/Slave pin connections

7.4.3 Continuous Conduction Mode

7.4.4 Operation With CNTL Signal Control

programmable UVLO, the polarity set by ON_OFF_CONFIG must be positive logic.

7.4.5 Operation with (01h) OPERATION Control

the OPERATION command to enable or disable regulation, regardless of the state of the CNTL signal.

7.4.6 Operation with CNTL and (01h) OPERATION Control

7.5 Programming

7.5.1 Supported PMBus Commands

The commands listed in Table 6 are implemented as described to conform to the PMBus 1.3 specification. Table 6 also lists the default for the bit behavior and register values. Table 6. Supported PMBus Commands and Default Values

Table 6. Supported PMBus Commands and Default Values (continued)

7.5.2 Pin Strapping

commands to be selected by the resistors connected to that pin without requiring PMBus communication. Each pin can be programmed in one of 4 ways.

• Pin shorted to AGND with less than 20Ω
• Pin floating or tied to BP1V5 with more than 1MΩ
• Pin bypassed to AGND through a 1% or better tolerance resistor according to R2G code only (16 Resistor Options)
• Pin bypassed to AGND through a 1% or better tolerance resistor according to R2G code and to BP1V5 according to Divider Code (16 Resistor x 16 Resistor Divider Options) Due to the flexibility of programming options with upto 274 configurations per pin, it is recommended that designers consider using one of the available design tools, such as SLUC686 to assist with proper programming resistor selection.

Table 7. TPS546A24A Pin Programming Summary 1MΩ resistor to BP1V5 for improved reliability and noise immunity. the power on reset function.

• Select MSEL1, MSEL2, VSEL and ADRSEL programming resistors to program the desired PMBus register values
• Power AVIN and VDD5 above their UVLOs to initiate pin detection and enable PMBus communication
• Update any PMBus register values not programmed to their final value by Pin Detection
• Write the value 0000h using the Write Word protocol to(EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
• Send the command code 15h using the Send Byte protocol to initialize a (15h) STORE_USER_ALL function
• Allow a minimum 100ms for the device to complete a burn of NVM User Store. Loss of AVIN or VDD5 power during this 100ms can compromise the integrity of the NVM. Failure to complete the NVM burn can result in a corruption of NVM and a POR fault on subsequent power on resets

7.5.2.1 Programming MSEL1

Table 8. MSEL1 divider code for (33h) FREQUENCY_SWITCH programming

is located at approximately 1/100 the switching frequency. Table 9. MSEL1 resistor to AGND code with no divider COMPENSATION_CONFIG programming

7.5.2.2 Programming MSEL2

Table 10. MSEL2 divider code for (61h) TON_RISE programming

and (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)values using Table 11. Table 11. MSEL2 resistor to AGND code for IOUT_OC_WARN/FAULT_LIMIT and

7.5.2.3 Programming VSEL

divider, (2Bh) VOUT_MIN and (24h) VOUT_MAX levels according to the following tables. Table 12. VSEL resistor divider code for (21h) VOUT_COMMAND programming

Table 12. VSEL resistor divider code for (21h) VOUT_COMMAND VOUT_COMMAND Offset and (21h) VOUT_COMMAND step from Table 13. Table 13. VSEL Resistor to AGND Code for (21h) VOUT_COMMAND Programming voltage and divide by the (21h) VOUT_COMMAND step.

7.5.2.4 Programming ADRSEL

divider also selects the Phase Shift between SYNC and the switch node. Table 14. ADRSEL resistor divider code for (37h) INTERLEAVE and SYNC_IN programming

Table 14. ADRSEL resistor divider code for (37h) INTERLEAVE and SYNC_IN programming (continued) Table 15. ADRSEL resistor to AGND code for (EFh) MFR_SPECIFIC_31

SYNC_IN all devices of the stack will remain disabled until a valid external SYNC signal is provided.

7.5.2.5 Programming MSEL2 for a Slave Device (GOSNS tied to BP1V5)

(46h) IOUT_OC_FAULT_LIMIT with a single resistor to AGND. Note: The master is always device 0. Table 16. Slave MSEL2 resistor to AGND code for (37h) INTERLEAVE and (ECh)

6 Device 1, 2-phase 20/26

7 Device1, 2-phase 8/12

4 Device 1, 3-phase 20/26

5 Device 1, 3-phase 8/12

8 Device 2, 3-phase 20/26

9 Device 2, 3-phase 8/12

2 Device 1, 4-phase 20/26

3 Device 1, 4-phase 8/12

14 Device 2, 4-phase 20/26

15 Device 2, 4-phase 8/12

10 Device 3, 4-phase 20/26

11 Device 3, 4-phase 8/12

ground on all other slave devices.

7.5.2.6 Pin-Strapping Resistor Configuration

tolerance or better resistors should be used. Table 17. Pin-Strapping Resistor (Ω) Table for R2G Codes 0-7 Table 18. Pin-Strapping Resistor (Ω) Table for R2G Codes 8-15

Table 18. Pin-Strapping Resistor (Ω) Table for R2G Codes 8-15 (continued)

7.6 Register Maps

7.6.1 Conventions for Documenting Block Commands

order. The description below shows the convention this document follows for documenting block commands. Byte N and ending with Byte 0.

• Byte 0 (first byte sent) corresponds to bits 7:0
• Byte 1 (second byte sent) corresponds to bits 15:8
• Byte 2 (third byte sent) corresponds to bits 23:16
• … and so on. When Block values are listed as text in hexadecimal, they are listed in byte order, from left to right, starting with Byte 0 and ending with Byte N with a space between each byte of the value. In the block 54 49 54 6A 24 41h the byte order shall be
• Byte 0, bits 7:0, = 54h
• Byte 1, bits 15:8, = 49h
• Byte 2, bits 23:16, = 6Ah
• Byte 3, bits 31:24, = 24h
• Byte 4, bits 39:32, = 41h 47 46 45 44 43 42 41 40 RW RW RW RW RW RW RW RW Byte N 39 38 37 36 35 34 33 32 RW RW RW RW RW RW RW RW Byte … 31 30 29 28 27 26 25 24 RW RW RW RW RW RW RW RW Byte 3 23 22 21 20 19 18 17 16 RW RW RW RW RW RW RW RW Byte 2 15 14 13 12 11 10 9 8 RW RW RW RW RW RW RW RW Byte 1 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW Byte 0 LEGEND: R/W = Read/Write; R = Read only

Figure 30. Block Command Byte Ordering

to the upper or lower MARGIN levels, and select soft-stop. Figure 31. (01h) OPERATION Register Map Table 19. Register Field Descriptions

7 ON_ OFF RW 0b Enable/disable power conversion, when the (02h) ON_OFF_CONFIG command is

by (02h) ON_OFF_CONFIG, etc...).

6 SOFT_ OFF RW 0b This bit controls the turn-off profile when the (02h) ON_OFF_CONFIG is configured

output voltage is ramped down to 0 V at a slew rate according to TOFF_ FALL. Once the output voltage reaches 0 V, power conversions stops. 5:2 MARGIN RW 0000b Sets the margin state. 0101b: Margin Low (Ignore Fault). Output voltage target is VOUT_MARGIN_LOW. OV/UV faults are ignored and do not trigger shut-down or STATUS updates. 0110b: Margin Low (Act on Fault). Output voltage target is VOUT_MARGIN_LOW. OV/UV faults trigger per their respective fault response settings. 1001b: Margin High (Ignore Fault). Output voltage target is VOUT_MARGIN_HIGH. OV/UV trigger are ignored and do not trigger shut-down or STATUS update. VOUT_MARGIN_HIGH. OV/UV trigger per their respective fault response settings. Other: Invalid/Unsupported data.

1 TRANSITIO

R 0b Not used and always set to 0. 0 Reserved R 0b Not used and always set to 0.

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Attempts to write (01h) OPERATION to any value other than those listed above will be considered invalid/unsupported data and cause the TPS546A24A to respond by flagging the appropriate status bits, and

Figure 32. (02h) ON_OFF_CONFIG Register Map Table 20. Register Field Descriptions 7:5 Reserved R 000b Not used and always set to 0.

4 PU RW NVM 0b: Unit starts power conversion any time the input power is present regardless of

3 CMD RW NVM 0b: Ignore OPERATION Command to start/stop power conversion

start/stop power conversion. start/stop power conversion. can not be used when CONTROL has active load polarity.

0 DELAY RW NVM 0b: When power conversion is commanded OFF by the CONTROL pin (must be

a write-only command with no data. sources which only become active post-ARA trigger SMB_ALERT#. Figure 33. (03h) CLEAR_FAULTS Register Map

needs to be established before any phase-dependent command can be successfully executed. Figure 34. (04h) PHASE Register Map Table 21. Register Field Descriptions

commands may have their parameters read, regardless osf the WRITE_PROTECT settings. Figure 35. (10h) WRITE_PROTECT Register Map Table 22. Register Field Descriptions ON_ OFF_ CONFIG, STORE_USER_ALL, and VOUT_ COMMAND commands. Other: Invalid/Unsupported data.

not have matching locations in the User Store are ignored. and waiting 100 ms minimum before continuing, following issuance of NVM store operations. Figure 36. (15h) STORE_USER_ALL Register Map

Figure 37. (16h) RESTORE_USER_ALL Register Map

read-only and has one data byte formatted as below. Figure 38. (19h) CAPABILITY Register Map Table 23. Register Field Descriptions 7 PEC R 1b 1b: Packet Error Checking is supported.

4 ALERT R 1b 1b: The device has an SMB_ALERT# pin and supports the SMBus Alert Response

3 FORMAT R 0b 0b: Numeric format is LINEAR or DIRECT.

2 AVSBUS R 0b 0b: AVSBus is NOT supported

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 7.6.10 (1Bh) SMBALERT_MASK CMD Address 1Bh Write Transaction: Write Word Read Transaction: Block-Write/Block-Read Process Call Format: Write: Unsigned Binary (2 bytes)Read: Unsigned Binary (1 byte) Phased: No, Only PHASE = FFh is supported NVM Back-up: EEPROM Updates: On-the-fly The SMBALERT_MASK command may be used to prevent a warning or fault condition from asserting the SMBALERT# signal. Setting a MASK bit does not prevent the associated bit in the STATUS_CMD from being set, but prevents the associated bit in the STATUS_CMD from asserting SMB_ALERT#. See Reference [3] for more information on the command format. The following register descriptions describe the individual mask bits available. SMBALERT_MASK Write Transaction = Write Word. CMD = 1Bh, Low =STATUS_CMD, High=MASK SMBALERT_MASK Read Transaction = Block-Write/Block-Read Process Call. Write 1 byte block with STATUS_CMD, read 1 byte block

SMBALERT_MASK bits for the STATUS_VOUT command. Figure 39. (1Bh) SMBALERT_MASK_VOUT Register Map Table 24. Register Field Descriptions RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.

SMBALERT_MASK bits for STATUS_IOUT . Figure 40. (1Bh) SMBALERT_MASK_IOUT Register Map Table 25. Register Field Descriptions RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.

6 Not

RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.

4 Not

3 Not

SMBALERT_MASK bits for STATUS_INPUT . Figure 41. (1Bh) SMBALERT_MASK_INPUT Register Map Table 26. Register Field Descriptions

7 Not

5 Not

RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.

2 Not

1 Not

0 Not

Figure 42. (1Bh) SMBALERT_MASK_TEMPERATURE Register Map Table 27. Register Field Descriptions 7 mOTF RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 6 mOTW RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.

Figure 43. (1Bh) SMBALERT_MASK_CML Register Map Table 28. Register Field Descriptions 7 mIVC RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 6 mIVD RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 5 mPEC RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 4 mMEM RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 1 mCOMM RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.

Figure 44. (1Bh) SMBALERT_MASK_OTHER Register Map Table 29. Register Field Descriptions hence this bit is hard-coded to 1b (source is masked).

SMBALERT_MASK bits for STATUS_MFR. Figure 45. (1Bh) SMBALERT_MASK_MFR Register Map Table 30. Register Field Descriptions 7 mPOR RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 6 mSELF RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 3 mRESET RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 2 mBCX RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition. 1 mSYNC RW NVM 0b: SMBALERT may assert due to this condition. 1b: SMBALERT may NOT assert due to this condition.

manufacturer’s VID codes are being used. Figure 46. (20h) VOUT_MODE Register Map Table 31. Register Field Descriptions

7 REL RW NVM 0b: Absolute Data Format

values in the linear mode range from -4 (62.5mV/LSB) to -12 (0.244 mV/LSB). Refer to the text below for more information. interpreted with the current VOUT_MODE value and converted if VOUT_MODE is later changed.

VOUT_COMMAND causes the device to set its output voltage to the commanded value with two data bytes. Figure 47. (21h) VOUT_COMMAND Register Map Table 32. Register Field Descriptions RW NVM Sets the output voltage target via the PMBus interface. the NVM, depending on the VOUT_COMMAND bit in PIN_DETECT_OVERRIDE. derived from pin-detection on the VSEL pin, at Power On Reset or RESTORE_USER_ALL. referred to as “VBOOT”), and is stored in RAM separately from the current value of VOUT_COMMAND . PMBus 1.3.1 Part II specification, section 10.2.

Format: SLINEAR16, Absolute Only per VOUT_MODE. changes due to VOUT_TRIM occur at the rate specified by VOUT_TRANSITION_RATE . Figure 48. (22h) VOUT_TRIM Register Map Table 33. Register Field Descriptions to -128 with an exponent -12 irrespective of VOUT_MODE. Table 34. VOUT_COMMAND/VOUT_MARGIN + VOUT_TRIM data validity (Linear Format)

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated The minimum and maximum valid data values for VOUT_TRIM follow the description in VOUT_COMMAND . Attempts to write (22h) VOUT_TRIM to any value outside those specified as valid, will be considered invalid/unsupported data and cause the TPS546A24A to respond by flagging the appropriate status bits, and Writes to VOUT_TRIM for which the resulting output voltage is greater than the current VOUT_MAX , or less than the current VOUT_MIN , cause the reference DAC to move to the value specified by VOUT_MIN or VOUT_MAX respectively, and cause the VOUT_MAX_MIN_WARNING fault condition, setting the appropriate bits in STATUS_WORD, STATUS_VOUT , and notifying the host per the PMBus 1.3.1 Part II specification, section 10.2.

accidentally setting the output voltage to a possibly destructive level. Figure 49. (24h) VOUT_MAX Register Map Table 35. Register Field Descriptions RW NVM Maximum output voltage. ULINEAR16 absolute per the setting of VOUT_ MODE. Refer to the description below for data validity.

• Set to the output voltage to current value of VOUT_MAX , at the slew rate defined by VOUT_TRANSITION_RATE
• Set the NONE OF THE ABOVE bit in the STATUS_BYTE
• Set the VOUT bit in the STATUS_WORD
• Set the VOUT_MIN_MAX warning bit in STATUS_VOUT
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. Although the scenario is uncommon, note that the same response results if the user attempted to program VOUT_MAX less than the current output voltage target.

the slew rate defined by VOUT_TRANSITION_RATE . the value of VOUT_MARGIN_HIGH + VOUT_TRIM . Figure 50. (25h) VOUT_MARGIN_HIGH Register Map Table 36. Register Field Descriptions VOUT_TRIM , follow the values allowed by the current VOUT_MAX setting.

the slew rate defined by VOUT_TRANSITION_RATE . value of VOUT_MARGIN_LOW + VOUT_TRIM . Figure 51. (26h) VOUT_MARGIN_LOW Register Map Table 37. Register Field Descriptions

turn off. The units are mV/us. Figure 52. (27h) VOUT_TRANSITION_RATE Register Map Table 38. Register Field Descriptions RW 11100b Linear format two’s complement exponent. Exponent = -4, LSB = 0.0625 mV/us. RW NVM Linear format two’s complement mantissa. output voltage slew rate is set to the nearest supported value.

Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked. STORE_USER_ALL and RESTORE_USER_ALL or cycle AVIN below UVLO. Figure 53. (29h) VOUT_SCALE_LOOP Register Map Table 39. Register Field Descriptions 15:11 VOSL_ EXP RW 11001b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa. Table 40. Accepted values

setting the output voltage to a level which will render the load inoperable. Figure 54. (2Bh) VOUT_MIN Register Map Table 41. Register Field Descriptions 15:0 VOUT_ MIN RW NVM Minimum output voltage. ULINEAR16 absolute per the setting of VOUT_ MODE.

• Set to the output voltage to current value of VOUT_MIN , at the slew rate defined by VOUT_TRANSITION_RATE
• Set the NONE OF THE ABOVE in the STATUS_BYTE
• Set the VOUT bit in the STATUS_WORD
• Set the VOUT_MIN_MAX warning bit in STATUS_VOUT
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. Although the scenario is uncommon, note that the same response results if the user attempted to program VOUT_MAX greater than the current output voltage target. Data Validity The minimum and maximum valid data values for VOUT_MIN follow those of VOUT_MAX . Attempts to write (2Bh) VOUT_MIN to any value outside those specified as valid, will be considered invalid/unsupported data and cause the TPS546A24A to respond by flagging the appropriate status bits, and notifying the host according to

Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked. STORE_USER_ALL and RESTORE_USER_ALL or cycle AVIN below UVLO. FREQUENCY_SWITCH sets the switching frequency of the active channel, in kHz. Figure 55. (33h) FREQUENCY_SWITCH Register Map Table 42. Register Field Descriptions 15:11 FSW_ EXP RW NVM Linear format two’s complement exponent. 10:0 FSW_ MAN RW NVM Linear format two’s complement mantissa. Refer to the table below. Table 43. Supported Switching Frequency Settings

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated FREQUENCY_SWITCH values greater than 1100kHz may require higher VDD5 current than can be provided by the internal AVIN to VDD5 linear regulator. Programming FREQUENCY_SWITCH to a value greater than 1100kHz without an external source to VDD5 may result in repeated start-up and shut-down attempt. FRQUENCY_SWITCH values greater than 1100kHz are not recommended for Stacked Multi-phase operation.

VIN_ON command sets the value of the input voltage, in Volts, at which the unit should start power conversion. Figure 56. (35h) VIN_ON Register Map Table 44. Register Field Descriptions 15:11 VON_ EXP RW 11110b Linear format two’s complement exponent, -2. store/restore operations do not reset this masking.

less than VIN_OFF, the output off due to low VIN bit in STATUS_INPUT shall be set. Figure 57. (36h) VIN_OFF Register Map Table 45. Register Field Descriptions 15:11 VOFF_ EXP RW 11110b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa. Refer to the text below. enabling and disabling of conversion and undesirable operation.

INTERLEAVE sets the phase delay between the external SYNC (In or Out) and the internal PMW oscillator. Figure 58. (37h) INTERLEAVE Register Map Table 46. Register Field Descriptions 11:8 GROUPID RW NVM Group ID Number. Set to 0h to Fh. NUM_GROUP. SEt to value 0h to NUM_GROUP - 1. Table 47. Supported INTERLEAVE Settings

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated The INTERLEAVE command is used to arrange multiple devices sharing a common SYNC signal in time. The phase delay added to each device is equal to 360° / Number in Group × Order. To prevent misaligning the phases of a multi-phase stack, INTERLEAVE is read only when the TPS546A24A is configured as part of a multi-phase stack. The Read/Write status of the INTERLEAVE command is set based on the state of the (ECh) MFR_SPECIFIC_28 (STACK_CONFIG) command at power-on and is not updated if (ECh) MFR_SPECIFIC_28 (STACK_CONFIG) is later changed. If INTERLEAVE will be used to program the phase position of a stand-alone device, the TPS546A24A must be configured as a stand-alone device at power-on to ensure write capability of the INTERLEAVE command.

value is a unitless gain factor applied to the internally sensed current measurement It defaults to a value of 1. Figure 59. (38h) IOUT_CAL_GAIN Register Map Table 48. Register Field Descriptions 15:11 IOCG_ EXP RW 11001b Linear format, two’s complement exponent. RW NVM Linear format, two’s complement mantissa.

Figure 60. (39h) IOUT_CAL_OFFSET Register Map Table 49. Register Field Descriptions RW 11100b Linear format, two’s complement exponent. RW NVM Linear format, two’s complement mantissa. a result the value of this command may be programmed with very high resolution using the linear format. PHASE = 00h to 03h: Writes to (39h) IOUT_CAL_OFFSET modify the current sense offset for individual phases. Reads to (39h) IOUT_CAL_OFFSET return the configured current sense offset for individual phases. PHASE =00h times the number of phases.

absolute format, the true overvoltage fault limit remains relative to the current VOUT_COMMAND. Figure 61. (40h) VOUT_OV_FAULT_LIMIT Register Map Table 50. Register Field Descriptions to 140% of VOUT_COMMAND in 10% steps.

• Set the VOUT_OV_FAULT bit in the STATUS_BYTE ,
• Set the VOUT bit in the STATUS_WORD ,
• Set the VOUT_OVF bit in the STATUS_VOUT register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW VO_OV_RESP VO_OV_RETRY VO_ OV_ DELAY LEGEND: R/W = Read/Write; R = Read only

Figure 62. (41h) VOUT_OV_FAULT_RESPONSE Register Map Table 51. Register Field Descriptions RW NVM Output over-voltage response. 00b: Ignore. Continue operating without interruption. RW NVM 0d: Do not attempt to restart (latch off). times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off). until commanded OFF, or a successful startup occurs. 1d - 7d: VO_OV HICCUP period is equal to 1-7 times TON_RISE.

VOUT_COMMAND do not update the value of VOUT_OV_FAULT_LIMIT when the absolute format is used.

• Set the VOUT bit in the STATUS_WORD ,
• Set the VOUT_OVW bit in the STATUS_VOUT register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. 15 14 13 12 11 10 9 8 RW RW RW RW RW RW RW RW VOUT_OVW (High Byte) 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW VOUT_OVW (Low Byte) LEGEND: R/W = Read/Write; R = Read only

Figure 63. (42h) VOUT_OV_WARN_LIMIT Register Map Table 52. Register Field Descriptions

the absolute format is used.

• Set the VOUT bit in the STATUS_WORD ,
• Set the VOUT_UVW bit in the STATUS_VOUT register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. 15 14 13 12 11 10 9 8 RW RW RW RW RW RW RW RW VOUT_UVW (High Byte) 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW VOUT_UVW (Low Byte) LEGEND: R/W = Read/Write; R = Read only

Figure 64. (43h) VOUT_UV_WARN_LIMIT Register Map Table 53. Register Field Descriptions mapped to the hardware percentage.

Figure 65. (44h) VOUT_UV_FAULT_LIMIT Register Map Table 54. Register Field Descriptions mapped to the hardware percentage.

• The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in response to an output under-voltage fault. The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in response to an output undervoltage fault. Upon triggering the over-voltage fault, the TPS546A24A responds according to the data byte below, and the following actions are taken:
• Set the NONE OF THE ABOVE bit in the STATUS_BYTE ,
• Set the VOUT bit in the STATUS_WORD ,
• Set the VOUT_UVF bit in the STATUS_VOUT register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW VO_UV_RESP VO_UV_RETRY VO_UV_DLY LEGEND: R/W = Read/Write; R = Read only

Figure 66. (45h) VOUT_UV_FAULT_RESPONSE Register Map Table 55. Register Field Descriptions RW NVM Output under-voltage response. 00b: Ignore. Continue operating without interruption. RW NVM Output under-voltage retry. 0d: Do not attempt to restart (latch off). times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off). until commanded OFF, or a successful startup occurs.

the lowest IOUT_OC_FAULT_LIMIT setting times the number of phases in the stack. Figure 67. (46h) IOUT_OC_FAULT_LIMIT Register Map Table 56. Register Field Descriptions RW 11110b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa. Refer to the table below. Per Phase OCL: up to 62A (PHASE != FFh).

ADVANCE□INFORMATION TPS546A24A www.ti.com SLUSE16 –FEBRUARY 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Write when PHASE != FFh: Set IOUT_OC_FAUL_LIMIT for the current phase to the written value. Read when PHASE != FFh: Report the IOUT_OC_FAULT_LIMIT value of the current phase

• Set the IOUT_OC bit in the STATUS_BYTE ,
• Set the IOUT bit in the STATUS_WORD ,
• Set the IOUT_OCF bit in the STATUS_IOUT register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. 7 6 5 4 3 2 1 0 RW RW RW RW RW R R R IO_OC_RESP IO_OC_RETRY IO_OC_DELAY LEGEND: R/W = Read/Write; R = Read only

Figure 68. (47h) IOUT_OC_FAULT_RESPONSE Register Map Table 57. Register Field Descriptions RW NVM Output over-current response. 00b: Ignore. Continue operating without interruption. RW NVM Output over-current retry. 0d: Do not attempt to restart (latch off). times. After 1 - 6 failed restart attempts, do not attempt to restart (latch off). until commanded OFF, or a successful startup occurs.

current detector to indicate an over-current warning condition. The units are amperes.

• Set the NONE OF THE ABOVE bit in the STATUS_BYTE ,
• Set the IOUT bit in the STATUS_WORD ,
• Set the IOUT_OCW bit in the STATUS_IOUT register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. 15 14 13 12 11 10 9 8 RW RW RW RW RW RW RW RW IOOCW_EXP IOOCW_MAN 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW IOOCW_MAN LEGEND: R/W = Read/Write; R = Read only

Figure 69. (4Ah) IOUT_OC_WARN_LIMIT Register Map Table 58. Register Field Descriptions RW 11110b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa. Supported values up to 23A times number of phases.

over-temperature fault condition. The converter response to an overtemperature event is described in OT_FAULT_RESPONSE . Figure 70. (4Fh) OT_FAULT_LIMIT Register Map Table 59. Register Field Descriptions 15:11 OTF_ EXP RW 00000b Linear format two’s complement exponent. 10:0 OTF_ MAN RW NVM Linear format two’s complement mantissa. Refer to the text below. Temperature Fault Limit without disabling the on-die Bandgap thermal shutdown.

• Set the TEMP bit in the STATUS_BYTE ,
• Set the OTF bit in the STATUS_TEMPERATURE register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2 Note: the OT Fault hysteresis is set by the (51h) OT_WARN_LIMIT, when (8Dh) READ_TEMPERATURE_1 falls below (51h) OT_WARN_LIMIT, the Over-temperature fault condition will be released and restart will be allowed if selected by OT_FAULT_RESPONSE If (51h) OT_WARN_LIMIT is programmed higher than (4Fh) OT_FAULT_LIMIT , a default hysteresis of 20 degrees C will be used instead. 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW OTF_RESP OT_RETRY OT_DELAY LEGEND: R/W = Read/Write; R = Read only

Figure 71. (50h) OT_FAULT_RESPONSE Register Map Table 60. Register Field Descriptions RW NVM Over-temperature fault response. 00b: Ignore. Continue operating without interruption. is still present, shut down and restart according to OT_RETRY. RW NVM Over Temperature retry. 0d: Do not attempt to restart (latch off). until commanded OFF, or a successful startup occurs.

ADVANCE□INFORMATION TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Attempts to write (50h) OT_FAULT_RESPONSE to any value outside those specified as valid, will be considered invalid/unsupported data and cause the TPS546A24A to respond by flagging the appropriate status bits, and * when (50h) OT_FAULT_RESPONSE OTF_RESP (Bits 7:6) are set to 11b - Shut down until Temperature is below OT_WARN_LIMIT, issuing a Figure 33command while the temperature is between (4Fh) OT_FAULT_LIMIT and (51h) OT_WARN_LIMIT can result in the TPS546A24A remaining in the OT FAULT state until the temperature rises above (4Fh) OT_FAULT_LIMIT or disabled and enabled according to (02h) ON_OFF_CONFIG

an Over-temperature Warning alarm. The units are degrees C.

• Set the TEMP bit in the STATUS_BYTE ,
• Set the OTW bit in the STATUS_TEMPERATURE register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2 15 14 13 12 11 10 9 8 RW RW RW RW RW RW RW RW OTW_EXP OTW_MAN 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW OTW_MAN LEGEND: R/W = Read/Write; R = Read only

Figure 72. (51h) OT_WARN_LIMIT Register Map Table 61. Register Field Descriptions 15:11 OTW_ EXP RW 00000b Linear format two’s complement exponent. 10:0 OTW_ MAN RW NVM Linear format two’s complement mantissa. Refer to the text below. of 20 degrees C will be used instead.

Figure 73. (55h) VIN_OV_FAULT_LIMIT Register Map Table 62. Register Field Descriptions RW 11110b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa. restored to the nearest supported value.

• Set the NONE OF THE ABOVE bit in the STATUS_BYTE register
• Set the INPUT bit in the upper byte of the STATUS_WORD register
• Set the VIN_OV bit in the STATUS_INPUT register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW VINOVF_RESP VINOVF_RETRY VIN_OVF_DLY LEGEND: R/W = Read/Write; R = Read only

Figure 74. (56h) VIN_OV_FAULT_RESPONSE Register Map Table 63. Register Field Descriptions RW NVM PVIN Over-voltage fault response. 00b: Ignore. Continue operating without interruption. RW NVM PVIN Over-voltage retry. 0d: Do not attempt to restart (latch off). until commanded OFF, or a successful startup occurs.

voltage detector to indicate an input under voltage warning. report input under voltage warnings.

• Set the NONE OF THE ABOVE bit in the STATUS_BYTE ,
• Set the INPUT bit in the STATUS_WORD ,
• Set the VIN_UVW bit in the STATUS_INPUT register
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2. 15 14 13 12 11 10 9 8 RW RW RW RW RW RW RW RW VINUVW_EXP VINUVW_MAN 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW VINUVW_MAN LEGEND: R/W = Read/Write; R = Read only

Figure 75. (58h) VIN_UV_WARN_LIMIT Register Map Table 64. Register Field Descriptions RW 11110b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa.

programmed by the ON_OFF_CONFIG command) until the output voltage starts to rise. Figure 76. (60h) TON_DELAY Register Map Table 65. Register Field Descriptions RW 11111b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa. TON_DELAY during which the device initializes itself at every power-on. TON_DELAY , TON_RISE , TOFF_FALL and TOFF_DELAY times.

entered the regulation band. This effectively sets the slew rate of the reference DAC during the soft-start period. settings or different TON_RISE times for the same TON_RISE setting and different VOUT_COMMAND voltages. Figure 77. (61h) TON_RISE Register Map Table 66. Register Field Descriptions RW 11110b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa.

power up the output without reaching the target voltage. (e.g. output voltage did not rise quickly enough), UV faults / associated response will always precede TON_MAX. The converter response to a TON_MAX fault event is described in TON_MAX_FAULT_RESPONSE . Figure 78. (62h) TON_MAX_FAULT_LIMIT Register Map Table 67. Register Field Descriptions RW 11111b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa. *Note: programming TON_MAX_FAULT to 0ms disables the TON_MAX functionality.

The TON_MAX_FAULT_RESPONSE instructs the device on what action to take in response to TON_MAX fault.

• Set the NONE OF THE ABOVE bit in the STATUS_BYTE
• Set the VOUT bit in the STATUS_WORD
• Set the TON_MAX bit in STATUS_VOUT
• Notify the host per PMBus 1.3.1 Part II specification, section 10.2 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW TONMAX_RESP TONMAX_RETRY TONMAX_DELAY LEGEND: R/W = Read/Write; R = Read only

Figure 79. (63h) TON_MAX_FAULT_RESPONSE Register Map Table 68. Register Field Descriptions RW NVM TON_ MAX Fault Response. 00b: Ignore. Continue operating without interruption. 0d: Do not attempt to restart (latch off). until commanded OFF, or a successful startup occurs.

programmed by the ON_OFF_CONFIG command) until the unit stops transferring energy to the output. Figure 80. (64h) TOFF_DELAY Register Map Table 69. Register Field Descriptions RW 11111b Linear format two’s complement exponent. RW NVM Linear format two’s complement mantissa.

Figure 81. (65h) TOFF_FALL Register Map Table 70. Register Field Descriptions RW NVM Linear format two’s complement mantissa.

Figure 82. (78h) STATUS_BYTE Register Map Table 71. Register Field Descriptions

7 BUSY RW 0b 0b: A fault was NOT declared because the device was busy and unable to

1b. A fault was declared because the device was busy and unable to respond. 6 OFF R 0b LIVE (unlatched) status bit. 0b. The unit is enabled and converting power.

5 VOUT_ OV R 0b 0b: An output over-voltage fault has NOT occurred

4 IOUT_ OC R 0b 0b: An output over-current fault has NOT occurred

3 VIN_ UV R 0b 0b: An input under-voltage fault has NOT occurred

2 TEMP R 0b 0b: A temperature fault/warning has NOT occurred. TEMPERATURE for more information. 1 CML R 0b 0b: A communication, memory, logic fault has NOT occurred.

0 NONE OF

STATUS_ WORD for more information.

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as the STATUS_BYTE . The supported STATUS_WORD message content is described in the following table. The conditions in the STATUS_BYTE are summary information only. Figure 83. (79h) STATUS_WORD Register Map Table 72. Register Field Descriptions 15 VOUT R 0b 0b: An output voltage related fault has NOT occurred. 14 IOUT R 0b 0b: An output current related fault has NOT occurred. 13 INPUT R 0b 0b: An input related fault has NOT occurred. 12 MFR R 0b 0b: A Manufacturer-defined fault has NOT occurred. PGOOD/RESET_B pin is asserted. 0b: The output voltage is within the regulation window. PGOOD pin is de-asserted.

10 Not

9 OTHER R 0b 0b: An OTHER fault has not occurred

8 Not

Table 72. Register Field Descriptions (continued) RW 00h Always equal to the STATUS_ BYTE value. All bits which may trigger SMBALERT have a corresponding bit in SMBALERT_MASK .

Figure 84. (7Ah) STATUS_VOUT Register Map Table 73. Register Field Descriptions

7 VOUT_

OVP. These can be individually controlled in SMBALERT_ MASK_ EXTENDED.

6 VOUT_

5 VOUT_

4 VOUT_

3 VOUT_

2 TON_ MAX RW 0b 0b: Latched flag indicating a TON_ MAX has NOT occurred

All bits which may trigger SMBALERT have a corresponding bit in SMBALERT_MASK .

Figure 85. (7Bh) STATUS_IOUT Register Map Table 74. Register Field Descriptions

7 IOUT_ OCF RW 0b 0b: Latched flag indicating IOUT OC fault has NOT occurred

5 IOUT_

All bits which may trigger SMBALERT have a corresponding bit in SMBALERT_MASK .

Figure 86. (7Ch) STATUS_INPUT Register Map Table 75. Register Field Descriptions

7 VIN_OVF R 0b 0b: Latched flag indicating PVIN OV fault has NOT occurred

5 VIN_UVW 0b 0b: Latched flag indicating PVIN UV warn occurred

All bits which may trigger SMBALERT have a corresponding bit in SMBALERT_MASK . enable conversion. LOW_VIN asserts initially at reset but does not assert SMBALERT. voltage issue. VIN_UVW IS masked until the first time the sensed input voltage exceeds the VIN_ON threshold.

Figure 87. (7Dh) STATUS_TEMPERATURE Register Map Table 76. Register Field Descriptions

7 OTF RW 0b 0b: Latched flag indicating OT fault has NOT occurred

6 OTW RW 0b 0b: Latched flag indicating OT warn has NOT occurred

All bits which may trigger SMBALERT have a corresponding bit in SMBALERT_MASK .

Figure 88. (7Eh) STATUS_CML Register Map Table 77. Register Field Descriptions

7 IVC RW 0b 0b: latched flag indicating invalid or unsupported command was NOT received

6 IVD RW 0b 0b: latched flag indicating invalid or unsupported data was NOT received

5 PEC RW 0b 0b: latched flag indicating NO packet error check has failed

4 MEM RW 0b 0b: latched flag indicating NO memory error was detected

3 PROC_FLT RW 0b 0b: latched flag indicating NO logic core error was detected

1 COMM RW 0b 0b: latched flag indicating NO communication error detected

All bits which may trigger SMBALERT have a corresponding bit in SMBALERT_MASK . Slaves will report a Back-Channel communications issue as a CML fault on their phase.

The STATUS_OTHER command returns one data byte with information not specified in the other STATUS bytes. Figure 89. (7Fh) STATUS_OTHER Register Map Table 78. Register Field Descriptions

0 FIRST_

RW 0b 0b: latched flag indicating that this device was NOT the first to assert SMBALERT. 1b: latched flag indicating that this device was the first to assert SMBALERT.

Figure 90. (80h) STATUS_MFR_SPECIFIC Register Map Table 79. Register Field Descriptions

7 POR RW 0b 0: No Power On Reset Fault has been detected

3 RESET RW 0b: 0b: A RESET_ VOUT event has NOT occurred

2 BCX RW 0b 0b: A BCX fault event has NOT occurred

1 SYNC RW 0b 0b: No SYNC fault has been detected

trigger SMBALERT have a corresponding bit in SMBALERT_MASK .

The READ_VIN command returns the output current in amperes. Figure 91. (88h) READ_VIN Register Map Table 80. Register Field Descriptions Linear format two’s complement exponent. Linear format two’s complement mantissa.

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML PHASE behavior When PHASE = FFh. READ_VIN returns the PVIN voltage of the master device. When PHASE != FFh, READ_VIN returns the PVIN voltage of the device assigned to the current PHASE

Format: ULINEAR16 per VOUT_MODE . The READ_VOUT command returns the actual, measured output voltage. Figure 92. (8Bh) READ_VOUT Register Map Table 81. Register Field Descriptions Output voltage reading, per VOUT_ MODE. scaled to maintain a voltage between 0V and 0.75V for proper reporting of the VOSNS voltage.

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML

The READ_IOUT command returns the output current in amperes. Figure 93. (8Ch) READ_IOUT Register Map Table 82. Register Field Descriptions Linear format two’s complement exponent. Linear format two’s complement mantissa.

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML PHASE behavior When PHASE = FFh. READ_IOUT returns the total current for the stack of devices supporting a single ouptut When PHASE != FFh, READ_IOUT returns the measured current of the device assigned to the current PHASE

The READ_TEMPERATURE_1 command returns the maximum power stage temperature in degrees Celsius. Figure 94. (8Dh) READ_TEMPERATURE_1 Register Map Table 83. Register Field Descriptions Linear format two’s complement mantissa.

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML PHASE behavior When PHASE = FFh. READ_TEMPERATURE_1 returns the temperature of the hottest of device in the stack of devices supporting a single output When PHASE != FFh, READ_TEMPERATURE_1 returns the measured temperature of the device assigned to the current PHASE

The PMBUS_REVISION command reads the revision of the PMBus to which the device is compliant. Figure 95. (98h) PMBUS_REVISION Register Map Table 84. Register Field Descriptions

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML

once at the time of manufacture. Figure 96. (99h) MFR_ID Register Map Table 85. Register Field Descriptions 23:0 MFR_ ID RW NVM 3 bytes of arbitrarily writable user-store NVM for manufactuer ID information.

done once at the time of manufacture. Figure 97. (9Ah) MFR_MODEL Register Map Table 86. Register Field Descriptions

revision number. This is typically done once at the time of manufacture. Figure 98. (9Bh) MFR_REVISION Register Map Table 87. Register Field Descriptions

number. This is typically done once at the time of manufacture. Figure 99. (9Eh) MFR_SERIAL Register Map Table 88. Register Field Descriptions

PMBus that is used for the PMBus interface. Figure 100. (ADh) IC_DEVICE_ID Register Map Table 89. Register Field Descriptions R See text. See the table below. Table 90. IC_DEVICE_ID Values

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3

The IC_DEVICE_REV command is used to either set or read the revision of the IC. Figure 101. (AEh) IC_DEVICE_REV Register Field Descriptions

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3

Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked. STORE_USER_ALL and RESTORE_USER_ALL or cycle AVIN below UVLO. Configure the control loop compensation. Figure 102. (B1h) USER_DATA_01 (COMPENSATION_CONFIG) Register Map Table 91. Register Field Descriptions RW NVM Selects the value of current loop integrating capacitor. RW NVM Selects the value of current loop filter capacitor.

32 SEL_CZI_M

RW NVM Selects the value of current loop mid-band gain resistor. RW NVM Selects the value of voltage loop integrating capacitor. RW NVM Selects the value of voltage loop filter capacitor.

16 Reserved RW NVM Reserved, set to 0b

Table 91. Register Field Descriptions (continued) RW NVM Selects the value of voltage loop mid-band gain resistor. RW NVM Selects the value of voltage error transconductance. RW NVM Selects the value of current error transconductance.

• Disable conversion, then write to (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
• Write to (B1h) USER_DATA_01 (COMPENSATION_CONFIG) while conversion is enabled, store PMBus values to NVM using (15h) STORE_USER_ALL clear the (B1h) USER_DATA_01 (COMPENSATION_CONFIG) bit in (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE) and then cycle AVIN or use the (16h) RESTORE_USER_ALL command. Due to the complexity of translating the 5-byte HEX value of (B1h) USER_DATA_01 (COMPENSATION_CONFIG) into analog compensation values, users are recommended to use of of the tools available at TPS546A24A product foldersuch as the SLUC686 design tool

POWER_STAGE_CONFIG allows the user to adjust the VDD5 regulator voltage. Figure 103. (B5h) USER_DATA_05 (POWER_STAGE_CONFIG) Register Map Table 92. Register Field Descriptions

Configure the priority and averaging for each channel of the internal telemetry system. taken. With each pass through all priority B measurements, one priority C measurement will be taken. Figure 104. (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG) Register Map Table 93. Register Field Descriptions

Table 93. Register Field Descriptions (continued)

ADVANCE□INFORMATION 130 TPS546A24A SLUSE16 –FEBRUARY 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 7.6.77 (DAh) MFR_SPECIFIC_10 (READ_ALL) CMD Address DAh Write Transaction: NA Read Transaction: Read Block Format: Unsigned Binary (14 bytes) Phased: No NVM Back-up: No READ_ALL provides for a 14-byte BLOCK read of STATUS_WORD and Telemetry values to improve bus utilization for poling by combining multiple READ functions into a single command, eliminating the need for multiple address and command code bytes. 111 110 109 108 107 106 105 104 R R R R R R R R Not Supported = 00h 103 102 101 100 99 98 97 96 R R R R R R R R Not Supported = 00h 95 94 93 92 91 90 89 88 R R R R R R R R Not Supported = 00h 87 86 85 84 83 82 81 80 R R R R R R R R Not Supported = 00h 79 78 77 76 75 74 73 72 R R R R R R R R READ_VIN (MSB) 71 70 69 68 67 66 65 64 R R R R R R R R READ_VIN (LSB) 63 62 61 60 59 58 57 56 R R R R R R R R READ_TEMPERATURE1 (MSB) 55 54 53 52 51 50 49 48 R R R R R R R R READ_TEMPERATURE1 (LSB) 47 46 45 44 43 42 41 40 R R R R R R R R READ_IOUT (MSB) 39 38 37 36 35 34 33 32 R R R R R R R R READ_IOUT (LSB) 31 30 29 28 27 26 25 24 R R R R R R R R READ_VOUT (MSB) 23 22 21 20 19 18 17 16 R R R R R R R R READ_VOUT (LSB) 15 14 13 12 11 10 9 8

Figure 105. (DAh) MFR_SPECIFIC_10 (READ_ALL) Register Map Table 94. Register Field Descriptions

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3

Figure 106. (DBh) MFR_SPECIFIC_11 (STATUS_ALL) Register Map Table 95. Register Field Descriptions

Table 95. Register Field Descriptions (continued)

• Set the CML bit in STATUS_BYTE
• Set the CML_IVC (bit 7) bit in STATUS_CML
• Notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3 Writes to STATUS_ALL do not clear asserted status bits.

unused (unassigned or disabled) phase numbers are always equal to 0b. Figure 107. (DCh) MFR_SPECIFIC_12 (STATUS_PHASE) Table 96. Register Field Descriptions PHASE =3d, and read STATUS_WORD or STATUS_ALL for more information. PHASE =2d, and read STATUS_WORD or STATUS_ALL for more information. PHASE =1d, and read STATUS_WORD or STATUS_ALL for more information. PHASE =0d, and read STATUS_WORD or STATUS_ALL for more information.

Figure 108. (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG) Register Map Table 97. Register Field Descriptions

5 SYNC_EDG

less than 0.8V and not switching, SYNC_OUT will be selected. prevented due to a SYNC_FAULT will result in the internal oscillator operating at 70% of its nominal frequency.

Figure 109. (ECh) MFR_SPECIFIC_28 (STACK_CONFIG) Register Map Table 98. Register Field Descriptions

MFR_SPECIFIC_29 is used to configure miscellaneous settings. Figure 110. (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS) Register Map Table 99. Register Field Descriptions

14 RESET_CN

13 RESET_FL

12 RESET# RW NVM Sets the function of the PGD/RESET_B pin

3 PULLUP# RW NVM Sets the pull-up of the PGD/RESET_B pin when RESET# = 1b

2 FLT_CNT RW NVM 0b: Fault Counter counts down 1 cycle on PWM cycle without fault

Updates: on-the-fly (pin detection occurs on POR only). Figure 111. (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE) Register Map Table 100. Register Field Descriptions 15:13 Reserved RW NVM Not used and set to 000b.

12 STACK_CO

11 SYNC_CO

10 Reserved RW NVM Not used and set to 0b or 1b.

9 COMP_CO

8 ADDRESS RW NVM 0b: At power-up or RESTORE, SLAVE_ADDRESS will be reset to NVM value

5 INTERLEA

4 Reserved RW NVM Not used and set to 0b or 1b.

3 TON_RISE RW NVM 0b: At power-up or RESTORE, TON_RISE will be reset to NVM value

2 IOUT_OC RW NVM 0b: At power-up or RESTORE, IOUT_OC_FAULT_LIMIT and

Table 100. Register Field Descriptions (continued)

1 FREQ RW NVM 0b: At power-up or RESTORE, FREQUENCY_SWITCH will be reset to NVM value

0 VOUT RW NVM 0b: At power-up or RESTORE, VOUT_COMMAND, VOUT_SCALE_LOOP,

for various PMBus commands during Power On Reset and RESTORE_USER_ALL.

0 ADDR_PMBUS

Figure 112. (EFh) MFR_SPECIFIC_31 (SLAVE_ADDRESS) Register Map Table 101. Register Field Descriptions

7 Not support R 0b Not support, set to b'0

• 0x0C
• 0x28
• 0x37
• 0x61

Updates: At boot-up, and following NVM Store/Restore operations. NVM_CHECKSUM reports the CRC-16 (polynomial 0x8005) checksum for the current NVM settings. Figure 113. (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM) Register Map Table 102. Register Field Descriptions

detection circuit for that controls it. Multiple faults and or may be simulated at once. Figure 114. (F1h) MFR_SPECIFIC_F1 (SIMULATE_FAULT) Register Map Table 103. Register Field Descriptions

15 FAULT_PE

14 SIM_TEMP

13 Reserved W/R 0b 0b: No Change, 1b: Not Used

12 SIM_IOUT_

11 SIM_VIN_O

10 SIM_VIN_O

9 SIM_VOUT

8 SIM_VOUT

7 WARN_PE

6 Reserved W/R Default

5 Reserved W/R Default

4 SIM_IOUT_

3 SIM_VIN_U

Table 103. Register Field Descriptions (continued)

2 Reserved W/R Default

1 SIM_VOUT

0 SIM_VOUT

Designer for identifying a TI device. set as a result of the receipt of a write attempt to this command. Figure 115. (FCh) MFR_SPECIFIC_44 (FUSION_ID0) Register Map Table 104. Register Field Descriptions

Designer for identifying a TI device. set as a result of the receipt of a write attempt to this command. Figure 116. (FDh) MFR_SPECIFIC_45 (FUSION_ID1) Register Map Table 105. Register Field Descriptions

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8 Power Supply Recommendations

The TPS546A24A devices are designed to operate from split input voltage supplies. AVIN is designed to operate from 2.95 V to 18 V. AVIN must be powered to enable POR, PMBus communication or output conversion. For AVIN voltages less than 4 V, VDD5 must be supplied with an input voltage greater than 4 V to enable switching. PVIN is designed to operate from 2.95 V to 16 V. PVIN must be powered to enable switching, but not for POR or PMBus communication. The TPS546A24A can be operated from a single 4-V or higher supply voltage by connecting AVIN to PVIN. TI recommends a 10-Ω resistor between AVIN and PVIN to reduce switching noise on AVIN. See the recommendations in the Layout section.

9 Layout

9.1 Layout Guidelines

Layout is critical for good power-supply design. Figure 117 shows the recommended PCB-layout configuration. A list of PCB layout considerations using these devices is listed as follows:

• As with any switching regulator, several power or signal paths exist that conduct fast switching voltages or currents. Minimize the loop area formed by these paths and their bypass connections.
• Bypass the PVIN pins to PGND with a low-impedance path. Place the input bypass capacitors of the power- stage as close as physically possible to the PVIN and PGND pins. Additionally, a high-frequency bypass capacitor in a 0402 package on the PVIN pins can help reduce switching spikes. This capacitor can be placed on the other side of the PCB directly underneath the device to keep a minimum loop.
• The VDD5 bypass capacitor carries a large switching current for the gate driver. Bypassing the VDD5 pin to PGND at the thermal pad with a low-impedance path is very critical to the stable operation of the TPS546A24A devices. Place the VDD5 high-frequency bypass capacitors as close as possible to the device pins, with a minimum return loop back to the Thermal Pad.
• The AVIN bypass capacitor should be placed close to the AVIN pin and provide a low-impedance path to PGND at the thermal pad. If AVIN is powered from PVIN for single supply operation, AVIN and PVIN should be seperated with a 10-µs R-C filter to reduce PVIN switching noise on AVIN.
• The BP1V5 bypass capacitor should be placed close to the BP1V5 pin and provide a low-impedance path to DRTN. DRTN should not be connected to any other pin or node. DRTN is internally connected to AGND and by external connection to System Ground. Connecting DRTN to PGND or AGND could introduce a ground loop and errant operation.
• Keep signal components local to the device, and place them as close as possible to the pins to which they are connected. These components include the VOSNS and GOSNS series resistors and differential filter capacitor as well as MSEL1, MSEL2, VSEL, and ADRSEL resistors. Those components can be terminated to AGND with a minimum return loop or bypassed to the copper area of a separate low-impedance analog ground (AGND) that is isolated from fast switching voltages and current paths and has single connection to PGND on the thermal pad through the AGND pin. For placement recommendations, see Figure 117.
• The PGND pin (pin 26) must be directly connected to the thermal pad of the device on the PCB, with a low- noise, low-impedance path.
• Minimize the SW copper area for best noise performance. Route sensitive traces away from the SW and BOOT pins as these nets contain fast switching voltages and lend easily to capacitive coupling.
• Snubber component placement is critical for effective ringing reduction. These components must be on the same layer as the TPS546A24A devices, and be kept as close as possible to the SW and PGND copper areas.
• Route the VOSNS and GOSNS lines from the output capacitor bank at the load back to the device pins as a tightly coupled differential pair. These traces must be kept away from switching or noisy areas which can add differential-mode noise.
• Use caution when routing of the SYNC, VSHARE, BCX_CLK and BCX_DATA traces for stackable configurations. The SYNC trace carries a rail-to-rail signal and should be routed away from sensitive analog signals, including the VSHARE, VOSNS, and GOSNS signals. The VSHARE traces must also be kept away from fast switching voltages or currents formed by the PVIN, AVIN, SW, BOOT, and VDD5 pins.

Bypass for internal regulators, AVIN.

9.2 Layout Example

Figure 117. PCB Layout Recommendation

9.3 Mounting and Thermal Profile Recommendation

(SLUA271) for more information. Figure 118. Recommended Reflow-Oven Thermal Profile

Table 106. Recommended Thermal Profile Parameters

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10 Device and Documentation Support

10.1 Device Support

10.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.1.2 Development Support

10.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS546D24A device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.1.2.2 Texas Instruments Fusion Digital Power Designer

The TPS546A24ATPS546x24x devices are supported by Texas Instruments Digital Power Designer. Fusion Digital Power Designer is a graphical user interface (GUI) which can be used to configure and monitor the devices via PMBus using a Texas Instruments USB-to-GPIO adapter. Click this link to download the Texas Instruments Fusion Digital Power Designer software package.

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. PMBus is a registered trademark of System Management Interface Forum, Inc.. All other trademarks are the property of their respective owners.

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10.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

10.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. These data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 22-Feb-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS546A24ARVFR PREVIEW LQFN-CLIP RVF 40 2500 TBD Call TI Call TI -40 to 150 TPS546A24A XPS546A24ARVFR ACTIVE LQFN-CLIP RVF 40 2500 TBD Call TI Call TI -40 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C 40X 0.3 0.2 3.3 0.1 40X 0.5 0.3 1.52 1.32 (0.2) TYP 0.05 0.00 36X 0.5 5.5 2X 3.5 5.3 0.1 B 5.1 4.9 A 7.1 6.9 LQFN-CLIP - 1.52 mm max heightRVF0040A PLASTIC QUAD FLATPACK - NO LEAD 4222989/B 10/2017 PIN 1 INDEX AREA 0.08 C SEATING PLANE 12 21 13 20 40 33 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 EXPOSED THERMAL PAD SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Reference JEDEC registration MO-220. SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

40X (0.25) 40X (0.6) ( 0.2) TYP VIA 36X (0.5) (6.8) (4.8) (1.28) (3.3) (R0.05) TYP (5.3) 6X (1.4) (1.12) LQFN-CLIP - 1.52 mm max heightRVF0040A PLASTIC QUAD FLATPACK - NO LEAD 4222989/B 10/2017 SYMM 13 20 3340 SYMM LAND PATTERN EXAMPLE SCALE:12X NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 40X (0.6) 40X (0.25) 36X (0.5) (4.8) (6.8) 8X (1.43) (1.28) TYP (0.815) TYP (R0.05) TYP (0.64) TYP (1.08) LQFN-CLIP - 1.52 mm max heightRVF0040A PLASTIC QUAD FLATPACK - NO LEAD 4222989/B 10/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 71% PRINTED SOLDER COVERAGE BY AREA SCALE:18X SYMM 13 20 3340

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