XPL735I RENESAS | Alldatasheet

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Technical content

Datasheet sections

Features

▪ Output types: LVDS, LVPECL, CML

  • Frequency range: 15MHz to 2100MHz ▪ Output type: HCSL
  • Frequency range: 15MHz to 725MHz ▪ Supply voltage options: 1.8V, 2.5V, or 3.3V ▪ Phase jitter (12kHz to 20MHz): 120fs typical ▪ Package options: ▪ Operating temperatures and frequency stability:
  • -40°C to +85°C, ±25ppm
  • -40°C to +105°C, ±50ppm Pin Assignments

Table 1. Pin Descriptions 1 Pins 7 and 8 are no connect for non-I2C applications. See Revision History for more details.

1 OE Output Enable (0 = output disabled, pulled high internally)

2 NC No connect

3 GND Connect to ground

4 OUT0 Output

5 OUT0b Complementary output

6 VDD Supply voltage

7 SDA 1 Serial data

8 SCL 1 Serial clock

2©2022 Renesas Electronics Corporation R31DS0067EU0401 February 10, 2022 XP Datasheet

Ordering Information

L Output Type Package Voltage Precision 125.000000 Frequency I Temperature Range I: Industrial range: ‐40 to +85°C, ±25ppm K: Extended industrial range: ‐40 to +105°C, ±50ppm

125.000000 Listed in MHz as example

3 digits before decimal and 6 digits past decimal 015.000000 to 099.999999 15MHz to 99.999999MHz 100.000000 to 999.999999 100MHz to 999.999999MHz A00.000000 to A99.999999 1000MHz to 1099.999999MHz B00.000000 to B99.999999 1100MHz to 1199.999999MHz C00.000000 to C99.999999 1200MHz to 1299.999999MHz D00.000000 to D99.999999 1300MHz to 1399.999999MHz E00.000000 to E99.999999 1400MHz to 1499.999999MHz F00.000000 to F99.999999 1500MHz to 1599.999999MHz G00.000000 to G99.999999 1600MHz to 1699.999999MHz H00.000000 to H99.999999 1700MHz to 1799.999999MHz I00.000000 to I99.999999 1800MHz to 1899.999999MHz J00.000000 to J99.999999 1900MHz to 1999.999999MHz K00.000000 to K99.999999 2000MHz to 2099.999999MHz L00.000000 2100MHz 5: ±50ppm (K only) 6: ±25ppm (I only) 1: 1.8 VDC ±5% 2: 2.5 VDC ±5% 3: 3.3 VDC ±5% 7: 7.0 x 5.0 mm 5: 5.0 x 3.2 mm 3: 3.2 x 2.5 mm C: CML Enable/Disable Pin 1 L: LVDS Enable/Disable Pin 1 P: LVPECL Enable/Disable Pin 1 N: HCSL Enable/Disable Pin 1 XP: 150fs jitter

1 Thermal characteristics are based on simulation in standard condition. Table 2. Absolute Maximum Ratings Table 3. ESD Compliance Table 4. Mechanical Testing * Mechanical Shock Half-sine wave with 0.3ms 3000G. X, Y, Z each direction 1 time. Frequency: 10 to 55MHz amplitude: 1.5mm. Frequency: 55–2000Hz peak value: 20G. Duration time: 4H for each X,Y,Z axis; total 12hours. High Temp Operating Life (HTOL) 1000 hours at 125°C (under power). Hermetic Seal Gross leak (air leak test). Fine leak (Helium leak test) He-pressure: 6kgf/cm² 2 hours.

Note for all DC Electrical Characteristics tables: A pull-up resistor from V DD to OE enables output when pin 1 is left open. Table 5. 3.3V IDD DC Electrical Characteristics Table 6. 2.5V IDD DC Electrical Characteristics Table 7. 1.8V IDD DC Electrical Characteristics

Table 8. LVCMOS DC Electrical Characteristics Table 9. LVDS DC Electrical Characteristics Table 10. LVPECL DC Electrical Characteristics Table 11. HCSL DC Electrical Characteristics

Table 12. CML DC Electrical Characteristics Table 13. DC Electrical Characteristics – Leakage Current

  1. A pull-up resistor from V DD to OE enables output when pin 1 is left open.
  2. Installation should include a 0.01 μF bypass capacitor placed between V DD and GND to minimize power supply line noise.

Table 14. 3.3V AC Electrical Characteristics

Table 15. 2.5V AC Electrical Characteristics

Table 16. 1.8V AC Electrical Characteristics Table 17. Phase Jitter Characteristics

18©2022 Renesas Electronics Corporation R31DS0067EU0401 February 10, 2022 XP Datasheet

Revision History

Revision Date Description of Change February 10, 2022 Updated Output Clock Duty Cycle minimum and maximum specifications for LVDS, LVPECL, HCSL, and CML in Table 14, Table 15, and Table 16. July 13, 2021 ▪ Updated Ordering Information “Precision” option. ▪ Updated Package Outline Drawings section. September 21, 2020 Updated ordering code to have I2C (was precision field, which is redundant with temperature field). July 22, 2019 Updated LVDS Differential Output Voltage minimum from 0.28 to 0.30V. April 1, 2019 Initial release.

© Integrated Device Technology, Inc.

© Integrated Device Technology, Inc. Rev 01March 6, 2019Update Drawing and DimensionsAug. 9, 2018Rev 00Initial ReleasePackage Revision HistoryRev No.Date CreatedDescription

© Integrated Device Technology, Inc.

© Integrated Device Technology, Inc. Package Revision HistoryRev No.Date CreatedDescriptionJuly 13, 2018Rev 00Initial ReleaseMarch 6, 2019Rev 01Update Drawing and Dimensions

© Integrated Device Technology, Inc.

© Integrated Device Technology, Inc. Rev 01.April 10, 2019DescriptionAug. 8, 2018Rev 00Initial ReleasePackage Revision HistoryRev No.Date CreatedUpdate Drawing, Thickness and Tolerance

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