XPL2010-1102ML

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Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs Data Sheet ADP5040 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

FEATURES

Input voltage range: 2.3 V to 5.5 V One 1.2 A buck regulator Two 300 mA LDOs 20-lead, 4 mm × 4 mm LFCSP package Overcurrent and thermal protection Soft start Undervoltage lockout Buck key specifications Output voltage range: 0.8 V to 3.8 V Current mode topology for excellent transient response

3 MHz operating frequency

Peak efficiency up to 96% Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PWM/PSM modes 100% duty cycle low dropout mode LDOs key specifications Output voltage range: 0.8 V to 5.2 V Low VIN from 1.7 V to 5.5 V Stable with 2.2 µF ceramic output capacitors High PSRR Low output noise Low dropout voltage −40°C to +125°C junction temperature range GENERAL DESCRIPTION The ADP5040 combines one high performance buck regulator and two low dropout regulators (LDO) in a small 20-lead LFCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulator enables the use of tiny multilayer external components and minimizes board space. When the MODE pin is set to logic high, the buck regulator operates in forced pulse width modulation (PWM) mode. When the MODE pin is set to logic low, the buck regulator operates in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold the regulator operates in power save mode (PSM) improving the light-load efficiency. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5040 LDOs extend the battery life of portable devices. The ADP5040 LDOs maintain a power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator in the ADP5040 is activated by a high level on the respective enable pin. The output voltages of the regulators are programmed though external resistor dividers to address a variety of applications. FUNCTIONAL BLOCK DIAGRAM SW 1µF 09665-001 FB2 R2 R1 FB3 R3 R7 2.2µF 2.2µF VOUT2 VOUT1 FB1 VIN1 = 2.3V TO 5.5V VIN1 EN1 VIN2 EN2 EN3 VIN3VIN3 = 1.7V TO 5.5V EN_LDO2 LDO2 (ANALOG) BUCK PGND MODE VOUT3 LDO1 (DIGITAL) EN_LDO1 AVIN AVINRFILT = 30Ω 4.7µF VIN2 = 1.7V TO 5.5V VOUT1 AT 1.2A VOUT2 AT 300mA VOUT3 AT 300mA 10µF 1µH 1µF ON OFF ON OFF ON OFF AGND EN_BK PSM/PWM FPWM Figure 1.

Rev. 0 | Page 2 of 40 TABLE OF CONTENTS Input and Output Capacitor, Recommended Specifications .. 5

REVISION HISTORY

12/11—Revision 0: Initial Version

Rev. 0 | Page 3 of 40 SPECIFICATIONS GENERAL SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 ≥VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter Symbol Description Min Typ Max Unit AVIN UNDERVOLTAGE LOCKOUT UVLOAVIN Input Voltage Rising UVLOAVINRISE Option 0 2.275 V Option 1 3.9 V Input Voltage Falling UVLOAVINFALL Option 0 1.95 V Option 1 3.1 V SHUTDOWN CURRENT IGND-SD ENx = GND 0.1 2 µA Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 20 °C START-UP TIME1 BUCK tSTART1 250 µs LDO1, LDO2 tSTART2 VOUT2, VOUT3 = 3.3 V 85 µs Enx, MODE, INPUTS Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V Input Leakage Current VI-LEAKAGE ENx = AVIN or GND 0.05 1 µA 1 Start-up time is defined as the time from the moment EN1 = EN2 = EN3 transfers from 0 V to VAVIN to the moment VOUT1, VOUT2, and VOUT3 reache 90% of their nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information. BUCK SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; VOUT1 = 1.8 V; L = 1 µH; CIN = 10 µF; COUT = 10 µF; TJ= −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1 Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Input Voltage Range VIN1 2.3 5.5 V OUTPUT CHARACTERISTICS Output Voltage Accuracy VOUT1 PWM mode, ILOAD = 0 mA to 1200 mA −3 +3 % Line Regulation (ΔVOUT1/VOUT1)/ΔVIN1 PWM mode −0.05 %/V Load Regulation (ΔVOUT1/VOUT1)/ΔIOUT1 ILOAD = mA to 1200 mA, PWM mode −0.1 %/A VOLTAGE FEEDBACK VFB1 0.485 0.5 0.515 V PWM TO POWER SAVE MODE CURRENT THRESHOLD IPSM_L 100 mA INPUT CURRENT CHARACTERISTICS MODE = ground DC Operating Current INOLOAD ILOAD = 0 mA, device not switching, all other channels disabled 21 35 μA Shutdown Current ISHTD EN1 = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 μA

Rev. 0 | Page 4 of 40 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SW CHARACTERISTICS SW On Resistance RPFET PFET, AVIN = VIN1 = 3.6 V 180 240 mΩ PFET, AVIN = VIN1 = 5 V 140 190 mΩ R NFET NFET, AVIN = VIN1 = 3.6 V 170 235 mΩ NFET, AVIN = VIN1 = 5 V 150 210 mΩ Current Limit ILIMIT PFET switch peak current limit 1600 1950 2300 mA ACTIVE PULL-DOWN EN1 = 0 V 85 Ω OSCILLATOR FREQUENCY FOSC 2.5 3.0 3.5 MHz 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO1, LDO2 SPECIFICATIONS VIN2, VIN3 = (VOUT2,VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5V; AVIN, VIN1 ≥ VIN2, VIN3; CIN = 1 μF , COUT = 2.2 μF; TJ= −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1 Table 3. Parameter Symbol Conditions Min Typ Max Unit INPUT VOLTAGE RANGE V IN2, VIN3 T J = −40°C to +125°C 1.7 5.5 V OPERATING SUPPLY CURRENT Bias Current per LDO2 I VIN2BIAS /IVIN3BIAS I OUT3 = IOUT4 = 0 μA 10 30 μA I OUT2 = IOUT3 = 10 mA 60 100 μA I OUT2 = IOUT3 = 300 mA 165 245 μA Total System Input Current I IN Includes all current into AVIN, VIN1, VIN2 and VIN3 LDO1 or LDO2 Only IOUT2 = IOUT3 = 0 μA, all other channels disabled 53 μA LDO1 and LDO2 Only IOUT2 = IOUT3 = 0 μA, buck disabled 74 μA OUTPUT VOLTAGE ACCURACY V OUT2, VOUT3 100 μA < IOUT2 < 300 mA, 100 μA < IOUT3 < 300 mA VIN2 = (VOUT2 + 0.5 V) to 5.5 V, VIN3 = (VOUT3 + 0.5 V) to 5.5 V −3 +3 % REFERENCE VOLTAGE V FB2, VFB3 0.485 0.500 0.515 V REGULATION Line Regulation (ΔVOUT2/VOUT2)/ΔVIN2 (ΔVOUT3/VOUT3)/ΔVIN3 VIN2 = (VOUT2 + 0.5 V) to 5.5 V VIN3 = (VOUT3 + 0.5 V) to 5.5 V −0.03 +0.03 %/ V I OUT2 = IOUT3 = 1 mA Load Regulation3 (ΔV OUT2/VOUT2)/ΔIOUT2 (ΔVOUT3/VOUT3)/ΔIOUT3 IOUT2 = IOUT3 = 1 mA to 300 mA 0.002 0.0075 %/mA DROPOUT VOLTAGE4 V DROPOUT V OUT2 = VOUT3 = 5.0 V, IOUT2 = IOUT3 = 300 mA 72 mV V OUT2 = VOUT3 = 3.3 V, IOUT2 = IOUT3 = 300 mA 86 140 mV V OUT2 = VOUT3 = 2.5 V, IOUT2 = IOUT3 = 300 mA 107 mV V OUT2 = VOUT3 = 1.8 V, IOUT2 = IOUT3 = 300 mA 180 mV ACTIVE PULL-DOWN RPDLDO EN2/EN3 = 0 V 600 Ω CURRENT-LIMIT THRESHOLD5 I LIMIT T J = −40°C to +125°C 335 470 mA OUTPUT NOISE OUTLDO2NOISE 10 Hz to 100 kHz, V IN3 = 5 V, VOUT3 = 3.3 V 123 μV rms 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 110 μV rms 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V 59 μV rms OUT LDO1NOISE 10 Hz to 100 kHz, V IN2 = 5 V, VOUT2 = 3.3 V 140 μV rms 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V 129 μV rms 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V 66 μV rms

Rev. 0 | Page 5 of 40 Parameter Symbol Conditions Min Typ Max Unit POWER SUPPLY REJECTION RATIO PSRR 1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 66 dB 100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 57 dB 1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 60 dB 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 This is the input current into VIN2 and VIN3, which is not delivered to the output load. 3 Based on an end-point calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 4. Parameter Symbol Conditions Min Typ Max Unit INPUT CAPACITANCE (BUCK)1 CMIN1 TJ = −40°C to +125°C 4.7 40 µF OUTPUT CAPACITANCE (BUCK)2 CMIN2 TJ = −40°C to +125°C 7 40 µF INPUT AND OUTPUT CAPACITANCE3 (LDO1, LDO2) CMIN34 TJ = −40°C to +125°C 0.70 µF CAPACITOR ESR RESR TJ = −40°C to +125°C 0.001 1 Ω 1 The minimum input capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with the buck. 2 The minimum output capacitance should be greater than 7 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with the buck. 3 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with LDOs.

soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance

15 FB2

11 VOUT1

1. EXPOSED PAD MUST BE CONNECTED TO

Figure 2. Pin Configuration—View from Top of the Die Table 7. Preliminary Pin Function Descriptions 2 VOUT3 LDO2 Output Voltage. 3 VIN3 LDO2 Input Supply (1.7 V to 5.5 V). 4 EN3 Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2. 6 AVIN Housekeeping Input Supply (2.3 V to 5.5 V). 7 VIN1 Buck Input Supply (2.3 V to 5.5 V). 9 PGND Dedicated Power Ground for Buck Regulator. 10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck. 11 VOUT1 Buck Output Sensing Node. 13 VIN2 LDO1 Input Supply (1.7 V to 5.5 V). 14 VOUT2 LDO1 Output Voltage. 16 EN2 Enable LDO1. EN2 = high: turn on LDO1; EN2 = low: turn off LDO1. power save mode (PSM) at light load and in constant PWM at higher load. 5, 18, 19, 20 NC Not Connected. 0 EPAD Exposed Pad. ( AGND = Analog Ground). The exposed pad must be connected to the system ground plane.

Figure 101. Functional Block Diagram MODE pin controls the buck switching operation. current due to the discharged output capacitors. level, the switching regulator operates in auto PWM/PSM mode. when the load current is above the power saving current threshold. function of the current load and the output capacitor value.

the thermal shutdown circuit turns off the buck and the LDOs. operation, poor circuit board design, or high ambient temperature. regulators start with soft start control. input supply drops to 3.65 V typical. The ADP5040 has individual control pins for each regulator. whereas a logic level low turns off a regulator. down resistor is 600 Ω for the LDOs and 85 Ω for the buck. voltage can be set from 0.8 V to 3.8 V. Figure 102. Buck External Output Voltage Setting scheme at light loads to lower the regulation power losses. output voltage by adjusting the peak inductor current threshold. PWM regulation level, which makes the output voltage rise. the load current is below the PSM current threshold.

sets the buck to operate in auto PSM/PWM. efficiency over all load currents. connected to the input of the converter. current from reversing direction and flowing out of the load. allowing overshoot on the output voltage. battery-operated portable equipment. The LDOs operate with an input voltage range of 1.7 V to 5.5 V . provided from the buck regulator. output voltage can be set from 0.8 V to 5.2 V. Figure 103. LDOs External Output Voltage Setting with small 1 µF ceramic input and output capacitors. used in applications where noise performance is not critical.

Figure 104. ADP5040 State Flow

Table 9. Suggested 10 μF Capacitors large load variation when working in PSM mode (see Figure 106). Figure 106. Processor System Power Management with PSM/PWM Control capacitor, a low ESR capacitor is recommended. Table 10. Suggested 4.7 μF Capacitors recommended to ensure stability of the LDO. Table 11. Suggested 2.2 μF Capacitors required, increase the input capacitor to match it.

Rev. 0 | Page 32 of 40 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the LDOs to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDOs provided by Equation 12. Buck Regulator Power Dissipation The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (3) where: PDBUCK is the power dissipation on the ADP5040 buck regulator. PL is the inductor power losses. The inductor losses are external to the device and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by LRMSOUT1L DCRIP ×≅ 2 )( (4) where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator. /12+1)( rII OUT1RMSOUT1 ×= (5) where r is the normalized inductor ripple current. R ≈ VOUT1 × (1 − D)/(IOUT1 × L × fSW) (6) where: L is inductance. FSW is switching frequency. D is duty cycle. D = VOUT1/VIN1 (7) The ADP5040 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 shows the calculation made to estimate the power dissipation in the buck regulator. P DBUCK = PCOND + PSW + PTRAN (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the PMOSFET and the NMOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by: PCOND = [RDSON-P × D + RDSON-N × (1 – D)] × IOUT12 (9) For the ADP5040, at 125°C junction temperature and VIN1 = 3.6 V, RDSON-P is approximately 0.2 Ω, and RDSON-N is approximately respectively, and at VIN1 = 5.5 V , the values are 0.16 Ω and 0.14 Ω, respectively. Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by: PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) where: CGATE-P is the PMOSFET gate capacitance. CGATE-N is the NMOSFET gate capacitance. For the ADP5040, the total of (CGATE-P + CGATE-N) is approximately 150 pF. The transition losses occur because the PMOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near VOUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by: PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW . For the ADP5040, the rise and fall times of SW are in the order of 5 ns. If the preceding equations and parameters are used for estimating the converter efficiency, note that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, a sufficient safety margin should be included in the estimate. LDO Regulator Power Dissipation The power loss of a LDO regulator is given by: PDLDO = [(VIN – VOUT) × ILOAD] + (VIN × IGND) (12) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small and it can be ignored. The total power dissipation in the ADP5040 simplifies to: PD = {[PDBUCK + PDLDO1 + PDLDO2]} (13)

vias as shown in Figure 109. θJC is the junction-to-case thermal resistance provided in Table 6. junction temperature, TJ, can be estimated using Equation 14. temperature of the ADP5040 (Equation 14) is less than 125°C. at http://www.analog.com/reliability_handbook. Figure 108. Application Diagram

• Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas.
• Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference.
• Maximize the size of ground metal on the component side to help with thermal dissipation.
• Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. SUGGESTED LAYOUT See Figure 109 for an example layout. GPL NC NC NCAGND NC GPL GPL GPL GPL VOUT3 VOUT1 VOUT2 PPL PPL PPL Pin1 GPL GPL GPL GPL GPL GPL PPL PPL TOP LAYER 09665-102 VIAS LEGEND: PPL = POWER PLANE (+4V) GPL = GROUND PLANE 2ND LAYER MODE EN L1 – 1µH 0603 C5 – 4.7µF 10V/XR5 0603 C6 – 10µF 6.3V/XR5 0603 1.0 1.0 2.0 2.0 3.0 3.0 mm mm 4.0 4.0 5.0 5.0 6.0 6.0 6.5 6.5 7.0 0.5 0.5 1.5 1.5 2.5 2.5 3.5 3.5 4.5 4.5 5.5 5.5 RFILT 30Ω 0402 C3 – 1µF 10V/XR5 0402 C4– 2.2µF 6.3V/XR5 0402 EN3 VIN3 VOUT3 FB3 VOUT1 FB1 VIN2 VOUT2 FB2 C2 – 1µF 10V/XR5 0402 C5 – 2.2µF 6.3V/XR5 0402 AVIN VIN SW PGND EN1 ADP5040

Figure 109. Evaluation Board Layout

Rev. 0 | Page 35 of 40 BILL OF MATERIALS Table 13. Reference Value Part Number Vendor Package C1 4.7 µF, X5R, 6.3 V JMK107BJ475 Taiyo-Yuden 0603 C2, C3 1 µF, X5R, 6.3 V LMK105BJ105MV-F Taiyo-Yuden 0402 C4 10 µF, X5R, 6.3 V JMK107BJ106MA-T Taiyo-Yuden 0603 C5, C6 2.2 µF, X5R, 6.3 V JMK105BJ225MV-F Taiyo-Yuden 0402 L1 1 µH, 85 mΩ, 1400 mA LQM2MPN1R0NG0B Murata 2.0 × 1.6 × 0.9 (mm) 1 µH, 85 mΩ, 1350 mA MDT2520-CN Toko 2.5 × 2.0 × 1.2 (mm) 1 µH, 89 mΩ, 1800 mA XPL2010-1102ML Coilcraft 1.9 × 2.0 × 1.0 (mm) IC1 3-regulator micro PMU ADP5040 Analog Devices 20-Lead LFCSP

Table 14. Regulator Output Discharge Resistor Options

0 All discharge resistors disabled

1 All discharge resistors enabled

Table 15. Under Voltage Lockout options

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

0.02 NOM

0.20 REF

0.25 MIN

Figure 110. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Rev. 0 | Page 38 of 40 NOTES

Rev. 0 | Page 39 of 40 NOTES

Rev. 0 | Page 40 of 40 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D096665-0-12/11(0)