XPGA848RGTR

PGA848 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 22

Technical content

PGA848 Low-Noise, Wide-Bandwidth, Scope Gain, Single-Ended Output, Programmable Gain Instrumentation Amplifier

1 Features

• Differential to single-ended conversion
• Eight pin-programmable decade (scope) gains
• Low gain error drift: ±2ppm/°C (maximum)
• Faster signal processing: – Wide bandwidth: 6.2MHz (G < 10), 2.4MHz (G = 50, 100) – Input stage noise: 8.5nV/√Hz at G > 10V/V – Filter option to achieve better SNR
• Input overvoltage protection to ±40V beyond supplies
• Input-stage supply range: – Single supply: 9V to 36V – Dual supply: ±4.5V to ±18V
• Independent output power-supply pins
• Output-stage supply range: – Single supply: 4.5V to 36V – Dual supply: ±2.25V to ±18V
• Specified temperature range: –40°C to +125°C
• Small package: 3mm × 3mm VQFN

2 Applications

• Factory automation and controls
• Analog input modules
• Data acquisition (DAQ)
• Test and measurement
• Parametric measurement units (PMU)

3 Description

The PGA848 is a wide-bandwidth, low-noise programmable gain instrumentation amplifier for differential-to-single-ended conversion. The PGA848 is equipped with eight decade (scope) gain settings, from an attenuating gain of 0.5V/V to a maximum of 100V/V. Gain is set using three digital gain selection pins. The PGA848 architecture is optimized to drive inputs of high-resolution, precision analog-to-digital converters (ADCs) with sampling rates up to 1MSPS without additional ADC drivers. The output-stage power supplies are decoupled from the input stage to protect the ADC or downstream devices against overdrive damage. The super-beta input transistors offer an impressively low input bias current, which in turn provides a very low input current noise density of 0.3pA/ √Hz. This capability makes the PGA848 a versatile choice for virtually any sensor type. The low-noise current- feedback front-end architecture offers exceptional gain flatness even at high frequencies, making the PGA848 an excellent high-impedance sensor readout device. Integrated protection circuitry on the input pins handles overvoltages of up to ±40V beyond the power-supply voltages.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) PGA848 RGT (VQFN, 16) 3mm × 3mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. IN+ IN PGA848 Gain Network OVP OVP VS- VS+ VLVDD VLVSS R R R R REF OUT DAIN DAIN+ ADCIN VDD VSS VIN+ VIN VIN VS+ VS- VDGND DGND A<2:0> LVSS LVDD VOUT VREF VOUT = G × VIN + VREF PGA848 Simplified Application Frequency (Hz) Gain (dB) -80 -60 -40 -20 10 100 1k 10k 100k 1M 10M G = 0.5 G = 1 G = 2 G = 5 G = 10 G = 20 G = 50 G = 100 Gain vs Frequency ADVANCE INFORMATION PGA848 SBOSAN4 – AUGUST 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

11 Mechanical, Packaging, and Orderable

4 Device Comparison Table

DEVICE OUTPUT TYPE GAIN (V/V) BANDWIDTH (MHz) SLEW RATE (V/μs) NOISE (nV/√Hz) PGA849 Single-ended ⅛, ¼, ½, 1, 2, 4, 8, 16 10 35 8.6 INA849 Single-ended G = 1 + 6kΩ / RG 28 35 1 PGA848 Single-ended ½, 1, 2, 5, 10, 20, 50, 100 6.2 35 8.5 PGA854 Differential ½, 1, 2, 5, 10, 20, 50, 100 6.2 35 8.5 PGA855 Differential ⅛, ¼, ½, 1, 2, 4, 8, 16 10 35 7.8 INA851 Differential G = 1 + 6kΩ / RG 22 37 3.2 INA821 Single-ended G = 1 + 49.4kΩ / RG 4.7 2 7 INA819 Single-ended G = 1 + 50kΩ / RG 2 0.9 8 PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

2 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

5 Pin Configuration and Functions

1A2 12 DA_IN– 15VS– 6 VS+ 2IN+ 11 OUT 14LVSS 7 LVDD 3IN– 10 REF 13NC 8 NC 4A0 9 DA_IN+ Not to scale Thermal Pad Figure 5-1. RGT Package, 16-Pin VQFN (Top View) Table 5-1. Pin Functions PIN TYPE DESCRIPTION NAME NO. A0 4 Input Gain-setting pin 0 A1 5 Input Gain-setting pin 1 A2 1 Input Gain-setting pin 2 DA_IN+ 9 Input Connection to output difference amplifier summing node DA_IN– 12 Input Connection to output difference amplifier summing node DGND 16 Power Ground reference for digital-logic and gain-setting pins IN– 3 Input Negative (inverting) input IN+ 2 Input Positive (noninverting) input LVDD 7 Power Output-driver positive supply LVSS 14 Power Output-driver negative supply NC 8, 13 — Do not connect OUT 11 Output Output REF 10 Input Reference input. Drive this pin with a low-impedance source VS– 15 Power Input-stage negative supply VS+ 6 Power Input-stage positive supply Thermal Pad Thermal pad — Solder the thermal pad to the printed-circuit board (PCB). Connect the thermal pad to a plane or large copper pour that is either floating or electrically connected to VS–. Make this connection even for applications that have low power dissipation. www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: PGA848 ADVANCE INFORMATION

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VS Supply voltage on VS+, VS– pins; VS = (VS+) – (VS–) 0 40 V VSOUT Supply voltage on LVDD, LVSS pins; VSOUT = VLVDD – VLVSS 0 40 V Voltage on power pins LVDD, LVSS (VS–) – 0.5 (VS+) + 0.5 V Voltage on signal-input pins IN+, IN– (VS–) – 40 (VS+) + 40 V DGND, DA_IN+, DA_IN– pin voltage (VS–) – 0.5 (VS+) + 0.5 V Voltage on gain-select pins A2, A1, A0 VDGND – 0.5 (VS+) + 0.5 V VOUT Voltage on output pin OUT VLVSS – 0.5 VLVDD + 0.5 V VREF Reference input voltage on REF pin VLVSS – 0.5 VLVDD + 0.5 V IO Output pin OUT current –100 100 mA ISC Output short-circuit current(2) Continuous TA Operating temperature –50 150 °C TJ Junction temperature 175 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Short-circuit to VSOUT / 2.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000 (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VS Input stage supply voltage Single supply 9 36 V Dual supply ±4.5 ±18 VSOUT Output stage supply voltage Single supply 4.5 36 V Dual supply ±2.25 ±18 TA Specified temperature –40 125 °C PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

4 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

6.4 Thermal Information

THERMAL METRIC(1) PGA848 UNITRGT (VQFN)

16 PINS

RθJA Junction-to-ambient thermal resistance 47.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 53.6 °C/W RθJB Junction-to-board thermal resistance 22.0 °C/W ψJT Junction-to-top characterization parameter 1.4 °C/W ψJB Junction-to-board characterization parameter 22.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.8 °C/W (1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

6.5 Electrical Characteristics

at TA = 25 °C, VS = VSOUT = ±15V, VICM = 0V, VREF = 0V, RL = 10kΩ connected to ground, and G = 1V/V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VOS Offset voltage (RTI) G = 5 to 100 ±50 ±300 µV Offset voltage drift RTI) TA = –40°C to +125°C G > 1 ±0.1 ±1.0 µV/°C PSRR Power-supply rejection ratio ±4V ≤ VS ≤ ±18V, RTI G = 0.5 108 124 dB G = 1 114 128 G = 2 118 130 G ≥ 5 120 134 zid Differential input impedance 100 || 1 GΩ || pF TA = –40°C to +125°C 10 || 1 zic Common-mode input impedance 100 || 7 VICM Common-mode input voltage VS = ±4.5V to ±18V, TA = –40°C to +125°C (VS–) + 3 (VS+) – 3 V VIN Differential input voltage(1) –20 +20 V CMRR Common-mode rejection ratio At dc to 60Hz, VICM = ±10V, TA = –40°C to +125°C, RTI G = 0.5 69 82 dB G = 1 75 88 G = 2 81 94 G = 5 88 100 G = 10 96 106 G = 20 102 112 G = 50 108 116 G = 100 116 124 BIAS CURRENT IB Input bias current ±0.5 ±2 nA Input bias current drift TA = –40°C to +125°C ±5 pA/°C IOS Input offset current ±0.5 ±1 nA Input offset current drift TA = –40°C to +125°C ±5 pA/°C GAIN Gain 0.5 100 V/V GE Gain error G = 100 ±0.025 ±0.05 www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: PGA848 ADVANCE INFORMATION

6.5 Electrical Characteristics (continued)

at TA = 25 °C, VS = VSOUT = ±15V, VICM = 0V, VREF = 0V, RL = 10kΩ connected to ground, and G = 1V/V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Gain drift TA = –40°C to +125°C G = 2 ±0.05 ±1 ppm/°C G ≠ 2 ±0.2 ±2 Gain nonlinearity G = 0.5 to 20, VOUT = 10V ±2 ±5 ppm G = 50, 100, VOUT = 10V TBD TBD TA = –40°C to +125°C, VOUT = 10V G ≤ 20 TBD G = 50, 100 TBD OUTPUT VOUT Output voltage(2) No load, VSOUT = ±2.25V VLVSS + 0.1 VLVDD – 0.1 V RL = 10kΩ VSOUT = ±2.25V VLVSS + 0.2 VLVDD – 0.2 VSOUT = ±18V VLVSS + 0.4 VLVDD – 0.4 CL Load capacitance Stable operation for capacitive load 100 pF ISC Short-circuit current Continuous to VSOUT / 2 ±45 mA TA = –40°C to +125°C ±20 ±60 FREQUENCY RESPONSE BW Bandwidth, –3dB G < 10 6.2 MHzG = 10, 20 4.2 G = 50, 100 2.4 SR Slew rate G = 0.5 to 100, VOUT > 5V TBD V/µs Gain switching time TBD µs REFERENCE INPUT Reference input voltage VLVSS VLVDD V Reference input impedance 10 kΩ Reference input current VIN = 0V 140 µA Reference gain to output 1 V/V Reference gain error VOUT = ±10V, within the linear operating range 0.01 0.05 % INPUT STAGE POWER SUPPLY IQ_input Input stage quiescent current VS+, VS– VIN = 0V, VICM = 0V 3 3.7 mA TA = –40°C to +125°C 4.6 OUTPUT STAGE POWER SUPPLY IQ_output Output stage quiescent current LVDD, LVSS VIN = 0V, VREF = 0V 1.3 1.8 mA TA = –40°C to +125°C 2.2 DIGITAL LOGIC VIL Digital input logic low A0, A1, A2 pins, referred to DGND VDGND VDGND + 0.8 V VIH Digital input logic high A0, A1, A2 pins, referred to DGND VDGND + 1.8 VS+ V Digital input pin current A0, A1, A2 pins 1.5 3 µA VDGND DGND voltage VS– (VS+) – 4 V DGND reference current 4 10 µA (1) Differential Input voltage of the PGA848 amplifier (VIN = VIN+ – VIN-). The valid input range depends on input common-mode voltage VICM, gain G, and reference voltage VREF. See Section 8.1.1 (2) Output voltage VOUT = G × VIN + VREF if VIN, VICM, and VREF are in valid linear operating range. See Section 8.1.1 PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

6 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

6.6 Typical Characteristics

at TA = 25°C, VS = VSOUT = ±15V, VICM = VREF = 0V, RL = 10kΩ connected to ground, and G =1V/V (unless otherwise noted) Input Referred Offset Voltage (V) Amplifiers (%) -1400 -900 -600 -300 0 300 600 900 1400 N = 700 Mean = 1.45µV Std. dev. = 253.2µV G = 0.5V/V Figure 6-1. Distribution of Offset Voltage (RTI) Input Referred Offset Voltage (V) Amplifiers (%) -350 -250 -150 -50 0 50 150 250 350 N = 700 Mean = –3.23µV Std. dev. = 67.1µV G = 2V/V Figure 6-2. Distribution of Offset Voltage (RTI) Input Referred Offset Voltage (V) Amplifiers (%) -300 -200 -100 0 100 200 300 N = 700 Mean = 17.29µV Std. dev. = 38.32µV G = 100V/V Figure 6-3. Distribution of Offset Voltage (RTI) Input Referred Offset Voltage Drift (V/C) Amplifiers (%) N = 30 Mean = –0.253μV/°C Std. dev. = 0.606μV/°C G = 0.5V/V Figure 6-4. Distribution of Offset Voltage Drift (RTI) Input Referred Offset Voltage Drift (V/C) Amplifiers (%) N = 30 Mean = –0.091μV/°C Std. dev. = 0.030μV/°C G = 2V/V Figure 6-5. Distribution of Offset Voltage Drift (RTI) Input Referred Offset Voltage Drift (V/C) Amplifiers (%) N = 30 Mean = –0.03μV/°C Std. dev. = 0.105μV/°C G = 100V/V Figure 6-6. Distribution of Offset Voltage Drift (RTI) www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: PGA848 ADVANCE INFORMATION

6.6 Typical Characteristics (continued)

at TA = 25°C, VS = VSOUT = ±15V, VICM = VREF = 0V, RL = 10kΩ connected to ground, and G =1V/V (unless otherwise noted) Gain Error (%) Amplifiers (%) N = 700 Mean = –0.005% Std. dev. = 0.0058% G = 0.5V/V Figure 6-7. Distribution of Gain Error Gain Error (%) Amplifiers (%) N = 700 Mean = –0.0019% Std. dev. = 0.0037% G = 2V/V Figure 6-8. Distribution of Gain Error Gain Error (%) Amplifiers (%) N = 700 Mean = –0.0125% Std. dev. = 0.0056% G = 100V/V Figure 6-9. Distribution of Gain Error Frequency (Hz) Gain (dB) -80 -60 -40 -20 10 100 1k 10k 100k 1M 10M G = 0.5 G = 1 G = 2 G = 5 G = 10 G = 20 G = 50 G = 100 Figure 6-10. Gain vs Frequency PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

8 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

7 Detailed Description

7.1 Overview

The PGA848 is a monolithic, high-voltage, precision programmable-gain instrumentation amplifier. The PGA848 combines a high-speed current-feedback input stage with an internally matched gain resistor network, followed by a four-resistor, difference amplifier output stage. Eight preprogrammed decade gains are selectable using A functional block diagram for the PGA848 is shown in the next section. The differential input voltage is fed into a pair of matched, high-impedance input, current-feedback amplifiers. An integrated precision-matched gain resistor network amplifies the differential input voltage. An output difference amplifier, A 3, rejects the input common-mode component and refers the output signal to the voltage level set by the REF pin. The PGA848 output amplifier bandwidth is optimized to drive high-performance analog-to-digital converters (ADCs) with sampling rates up to 1MSPS, without additional ADC drivers. The output amplifier uses a separate power supply that is independent of the input-stage power supply. When driving an ADC, use a low-impedance connection from LVDD and LVSS to the ADC power supplies. This configuration protects the ADC inputs from damage resulting from inadvertent overvoltage conditions.

7.2 Functional Block Diagram

6.67k Gain Network 3.33k 3.33k 6.67k A<2:0> DGND IN– IN+ DGNDVS+ A3 OUT LVSSLVDD LVSSLVDD REF DA_IN– DA_IN+ VS+ VS− LVDD LVSS VS+ VS− VS+ VS− VS+ VS− VS+ VS− VS+ VS− VS+ VS− www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: PGA848 ADVANCE INFORMATION

7.3 Feature Description

7.3.1 Gain Control

The PGA848 uses three pins to set the amplifier gain. These gain-select pins are set with respect to DGND. This configuration simplifies the design when compared to programmable-gain amplifiers requiring a SPI or other digital interface options for gain changes. Figure 7-1 shows the gain-setting block diagram. Table 7-1 lists the gain options. Any gain-select pin not driven by an external source is automatically biased at DGND using internal pulldown options. Gain Decoder DGND Gain Resistor Network Figure 7-1. PGA848 Gain Setting Block Diagram Table 7-1. Gain Options A2:A0 GAIN 000 0.5 001 1 010 2 011 5 100 10 101 20 110 50 111 100 PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

10 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

7.3.2 Input Protection

The inputs of the PGA848 are individually protected for voltages up to ±40V beyond either supply. For example, an input common-mode voltage anywhere between –55V and +55V does not cause damage when powered from ±15V supplies. Internal circuitry on each input provides low series impedance under normal signal conditions, thus maintaining high performance under normal operating conditions. If the input is overloaded, the protection circuitry limits the input current to a value of approximately 4.8mA. Figure 7-2 shows the input protection functionality during an overvoltage condition on IN+ or IN- inputs. Figure 7-2. Input Current vs Input Overvoltage Figure 7-3 shows that during an input overvoltage condition, current flows through the input protection diodes into the power supplies. In applications where the power supplies are unable to sink current, place Zener diode clamps (ZD1 and ZD2) on the power supplies. These Zener diodes provide a current pathway to ground. VS+ VS– Overvoltage Protection INx Input Transistor VS+ VS– Input Voltage Source ZD1 ZD2 RIN Figure 7-3. Input Current Path During an Overvoltage Condition www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: PGA848 ADVANCE INFORMATION

7.3.3 Using the Output Difference Amplifier to Shape Noise

The functional block diagram in Section 7.2 shows that the PGA848 output-stage difference amplifier uses a 6.67kΩ feedback resistor between the output and the inverting input. External direct access to the inverting and noninverting inputs of the difference amplifier is provided through the DA_IN– and DA_IN+ pins, respectively. This option allows circuit designers to add external capacitors in parallel with the internal resistors to implement noise-filtering or noise-shaping techniques. These pins are also used to implement customized attenuating gains for the output stage. Consider the following important factors when designing parallel circuits with the internal resistors:

• The accuracy of the internal resistor network is 0.01% or better. This accuracy results in a common-mode rejection (CMRR) of 80dB or better. Mismatched leakage currents on these pins potentially cause CMRR degradation.
• The internal resistors have ±15% absolute resistance variation. Consider this variation when implementing custom attenuating gains or noise filters. CAUTION Do not treat these pins as outputs, nor use the pins to source or sink current. Excessive currents through the feedback resistors potentially cause permanent damage to internal circuitry.

7.4 Device Functional Modes

The PGA848 has a single functional mode. The device operates when the input-stage power supply is greater PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

12 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The PGA848 is a monolithic, high-voltage, high-bandwidth, precision programmable gain instrumentation amplifier with a single-ended output. The PGA848 combines a high-speed current-feedback input stage with an internally matched gain resistor network, followed by a four-resistor, differential amplifier output stage. The PGA848 is equipped with eight binary-gain settings, from 0.5V/V to 100V/V, using three digital gain-selection pins: A0, A1, and A2. The PGA848 is designed for applications such as factory automation and control, analog input modules, data acquisition, test and measurement, and semiconductor test.

8.1.1 Linear Operating Input Range

The linear operating input voltage range of the PGA848 input circuitry extends within 3V (maximum) of either power supply. The device maintains excellent common-mode rejection throughout this range at all temperatures. The linear operating input common-mode range is a function of the input common-mode voltage, input differential voltage, gain, and reference input voltage. The valid common-mode range to enable valid output voltage at no load condition are shown in Figure 8-4 to Figure 8-3. Output Voltage (V) Max/Min Input Common-Mode Voltage (V) -15 -12 -9 -6 -3 0 3 6 9 12 15 -15 -12 VS = VSOUT = 15V VS = 15V, VSOUT = 5V VS = VSOUT = ±15V VS = ±15V, VSOUT = ±5V VREF = 0V G = 0.5V/V Figure 8-1. Input Common-Mode Voltage vs Output Voltage Output Voltage (V) Max/Min Input Common-Mode Voltage (V) -20 -16 -12 -8 -4 0 4 8 12 16 20 -15 -12 VS = VSOUT = 15V VS = VSOUT = 5V VS = VSOUT = ±15V VS = VSOUT = ±5V VREF = 0V G = 1V/V Figure 8-2. Input Common-Mode Voltage vs Output Voltage www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: PGA848 ADVANCE INFORMATION

Output Voltage (V) Max/Min Input Common-Mode Voltage (V) -20 -16 -12 -8 -4 0 4 8 12 16 20 -15 -12 VS = VSOUT = 15V VS = VSOUT = 5V VS = VSOUT = ±15V VS = VSOUT = ±5V VREF = 0V G = 2V/V Figure 8-3. Input Common-Mode Voltage vs Output Voltage Output Voltage (V) Max/Min Input Common-Mode Voltage (V) -20 -16 -12 -8 -4 0 4 8 12 16 20 -15 -12 VS = VSOUT = 15V VS = VSOUT = 5V VS = VSOUT = ±15V VS = VSOUT = ±5V VREF = 0V G = 100V/V Figure 8-4. Input Common-Mode Voltage vs Output Voltage

8.2 Typical Applications

8.2.1 Driving a Single-Ended Input SAR ADC

Figure 8-5 shows the schematic for a 16-bit, precision, 1MSPS, successive approximation register (SAR), analog-to-digital converter (ADC). This circuit shows the driving capability of the PGA848 with the ADS8860 single-ended input ADC. ADS8860 Single-Ended SAR ADC INP INN 5.3V AVSS REF6250 5.0V Reference RDIV1 ±0.05% 10k REF6050 5.0V Reference OPA192+ RISO RF 5.3V 10pF 10pF 15V 100nF –15V 100nF DA_IN– OUT IN+ IN– DA_IN+ PGA848 Gain Network A0A1A2 A0A1A2 Overvoltage Protection Overvoltage Protection VS+ DGND REF LVDD VS– LVSS 5.3V 1µF REFIN PGA848 REF Voltage 2.5V 100pF 100nF CFB 75pF CFB 75pF 22µF 0.22 CCM 120pF RFIL CDIFF 1.2nF RFIL CCM 120pF 22nF 10nFRDIV2 ±0.05% 10k CF 2200pF100nF 100 100 3.33k 3.33k 6.67k 6.67k VIN+ VIN VOUT = G × VIN +VREF VIN = VIN+ VIN VOUT VREF Figure 8-5. Driving the ADS8860 SAR ADC PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

14 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

The circuit accepts single-ended or differential input signals. The PGA848 operates with independent input and output power supplies. In this example, ±15V power supplies power the input stage, and a unipolar 5.3V supply powers the output stage. The PGA848 output stage supply is powered by the same 5.3V ADC supply. The 5.3V output supply operation prevents overloading the ADC inputs during PGA overdrive conditions. The REF6250 is selected as the ADC voltage reference. The REF6250 is a low-noise, low-drift, precision, 5V reference connected to the ADS8860 reference input ADC REFIN pin. The PGA848 output voltage is developed with respect to the REF pin. The REF pin is set to the SAR ADC midscale voltage by dividing the REF6250 ADC reference with a precision resistive voltage divider. The OPA192 buffer drives the PGA848 REF pin. The OPA192 is a precision amplifier with low offset, low drift, and 10MHz bandwidth.

8.2.1.1 Design Requirements

Table 8-1 lists the design requirements for the application driving the ADS8860 ADC. Table 8-1. Design Parameters PARAMETER VALUE Supply voltages VS± = ±15V, VLVDD = 5.3V, VLVSS = GND, ADC REFIN = 5V PGA848 reference pin VREF = 2.5V Full-scale range of the ADC FSR = 5V Sampling rate of the ADC fSAMPLE = 1MSPS Signal frequency 1kHz RC kickback filter RFIL = 15Ω, CDIFF = 1.2nF, CCM = 120pF

8.2.1.2 Detailed Design Procedure

The first filter located at the input of the PGA (see Figure 8-5 ) helps reduce electromagnetic interference (EMI) and radio frequency interference (RFI), high-frequency, extrinsic noise. Customize this filter as per the application bandwidth and antialiasing requirements. The second filter is provided by C FB in parallel with the PGA 6.67k Ω feedback resistors. The PGA resistors are ±15% absolute tolerance, as such, consider the effect of the tolerance on the filter cutoff frequency. C FB = 75pF results in a filter cutoff frequency of 318kHz. On the high side of the resistor tolerance, the filter frequency changes to 277kHz. The device allows for flexibility to modify the C FB capacitor value to adjust bandwidth, with a trade-off on the broadband noise of the circuit. The third filter placed at the ADS8860 inputs works as a charge reservoir filter to drive the SAR ADC. The charge kickback filter reduces the instantaneous charge demand of the amplifier, maintaining low distortion that otherwise potentially degrades because of incomplete ADC sample-and-hold settling. The RC filter combination (RFIL, CDIFF) is tuned for ADC sample-and-hold settling and total harmonic distortion (THD) performance, while maintaining stability of the PGA. High-grade C0G capacitors are used everywhere in the signal path for the low distortion properties. The PGA848 front end, accounting for all three filters, provides a nominal f –3dB bandwidth of 318kHz. On the high side of the internal 6.67k Ω feedback resistor tolerance, the PGA848 f–3dB bandwidth changes to 277kHz. However, the circuit maintains –0.1dB flatness to 41kHz. The ADS8860 requires a full-scale input in the range of 0V to the 5V ADC reference. The PGA848 REF pin is set to a nominal voltage of 2.5V to shift the signal to the ADC midscale voltage. Generate the PGA848 REF voltage by feeding the REF6250 5V reference through a 10k Ω-to-10kΩ precision voltage divider implemented with ±0.05% tolerance, low-drift ±5ppm/°C resistors. Drive the PGA848 REF pin with a low-impedance source. Use an op amp such as the OPA192 as a buffer to drive the REF pin. The OPA192 buffer is configured in a dual-feedback configuration to provide stability while driving the REF pin and 22nF bypass capacitor. R ISO is a 20 Ω isolation resistor that provides separation of two feedback paths for optimized stability. The first feedback path through the feedback resistor, R F = 2k Ω, connected directly to the www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: PGA848 ADVANCE INFORMATION

REF pin. The second feedback path is through the feedback capacitor, C F = 2nF, connected to the output of the op amp. The circuit provides a loop gain phase margin of 86°. The noninverting input of the OPA192 buffer has a low-pass filter with R = 1k Ω, C = 10nF to reduce the resistive divider thermal noise. Using any other load capacitance requires recalculation of the stability components: R F, CF, and R ISO. If modifying the REF bypass capacitance, verify the circuit is stable with simulation using the OPA192 TINA-TI model (or PSpice ®-for-TI model). Confirm the circuit provides more than 60° of phase margin.

8.3 Power Supply Recommendations

The nominal performance of the PGA848 is specified with input-stage supply and output-stage supply voltages of ±15V, and V ICM and V REF at mid-supply. Within the specified limits, custom input common-mode and output common-mode voltages are usable without compromising performance; see also Section 6.3. To prevent damage to internal circuitry, the output-stage power supplies are clamped to stay within the input-stage supply voltage levels; see also Section 7.2. CAUTION Supply voltages higher than 40V (±20V) permanently damage the device.

8.4 Layout

8.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use good PCB layout practices, including:

• To avoid converting common-mode signals into differential signals and thermal electromotive forces (EMFs), verify both input paths are symmetrical and well-matched for source impedance and capacitance.
• Noise potentially propagates into analog circuitry through the power pins of the device and of the circuit as a whole. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in parallel with the noisy trace.
• Leakage on the DA_IN+ and DA_IN– pins potentially causes dc offset errors in the output voltages. Additionally, excessive parasitic capacitance at these pins potentially results in decreased phase margin and affects the stability of the output stage. If these pins are not used to implement deliberate capacitive feedback, follow best practices to minimize leakage and parasitic capacitance.
• Follow best practices to minimize leakage and parasitic capacitance, which includes implementing keep-out areas in any ground planes located immediately below the input pins.
• Minimize the number of thermal junctions. If possible, route the signal path using a single layer without vias.
• Keep sufficient distance from major thermal energy sources (circuits with high power dissipation). If not possible, place the device so that the thermal energy source effects on both sides of the differential signal path are evenly matched.
• Keep the traces as short as possible. PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

16 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

8.4.2 Layout Example

IN– IN+ VS+ LVDD 8 NC DA_IN– OUT REF 9DA_IN+ DGND VS LVSS 13NC PAD GND IN+ GND ADC_IN Use ground pours for shielding the input signal pairs Place bypass capacitors as close to IC as possible Consider using thermal vias for heatsinking Cutouts on ground planes underneath input pins can reduce stray capacitance, for better phase margin GND VS+ VS+VS– PGA848 ADC IN REF OUT Connect feedback capacitors between OUT and DA_IN– (optional) A<2:0> DGND IN– GND LVSS VS VS+ LVDD Optional noise filtering capacitors VS LVSS LVDD DA_IN+ DA_IN– C6 Connect feedback capacitors between REF and DA_IN+ (optional) ADC_REF / 2 GND ADC_REF / 2 VIN+ VIN IN+IN– VLVDD VLVSS Figure 8-6. Example Schematic and Associated PCB Layout www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: PGA848 ADVANCE INFORMATION

9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

9.1.1.1 PSpice® for TI

PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create subsystem and prototype designs before committing to layout and fabrication, thus reducing development cost and time to market.

9.1.1.2 TINA-TI™ Simulation Software (Free Download)

TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded with a library of macromodels, including a range of passive and active models. TINA-TI simulation software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Design and simulation tools web page, TINA-TI simulation software offers extensive post-processing capability. This capability allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Note These files require that either the TINA software or TINA-TI software be installed. Download the free TINA-TI simulation software from the TINA-TI™ software folder.

9.2 Documentation Support

9.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Comprehensive Error Calculation for Instrumentation Amplifiers application note
• Texas Instruments, Importance of Input Bias Current Return Paths in Instrumentation Amplifier Applications application note
• Texas Instruments, ADS8860 16-Bit, 1MSPS, Serial Interface, Micropower, Miniature, Single-Ended Input, SAR Analog-to-Digital Converter data sheet
• Texas Instruments, REF62xx High-Precision Voltage Reference With Integrated ADC Drive Buffer data sheet
• Texas Instruments, OPAx192 36V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp With e-Trim™ data sheet

9.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

TINA-TI™ and TI E2E™ are trademarks of Texas Instruments. TINA™ is a trademark of DesignSoft, Inc. PSpice® is a registered trademark of Cadence Design Systems, Inc. All trademarks are the property of their respective owners. PGA848 SBOSAN4 – AUGUST 2025 www.ti.com

18 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: PGA848 ADVANCE INFORMATION

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES August 2025 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com PGA848 SBOSAN4 – AUGUST 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: PGA848 ADVANCE INFORMATION

www.ti.com 29-Aug-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) XPGA848RGTR Active Preproduction VQFN (RGT) | 16 5000 | LARGE T&R - Call TI Call TI -40 to 125 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated