MPC850EC MOTOROLA | Alldatasheet
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This document contains detailed information on power considerations, AC/DC electrical characteristics, and AC timing specifications for revision A,B, and C of the MPC850. This document contains the following topics: Topic Page Part I, “Overview” 1 Part II, “Features” 3 Part III, “Electrical and Thermal Characteristics” 7 Part IV , “Thermal Characteristics” 8 Part V , “Power Considerations” 9 Part VI, “Bus Signal Timing” 10 Part VII, “IEEE 1149.1 Electrical Specifications” 37 Part VIII, “CPM Electrical Characteristics” 39 Part IX, “Mechanical Data and Ordering Information” 61 Part X, “Document Revision History” 67 Part I Overview The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. The MPC850, which includes support for Ethernet, is specifically designed for cost-sensitive, remote-access, and telecommunications applications. It is provides functions similar to the MPC860, with system enhancements such as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM. In addition to a high-performance embedded MPC8xx core, the MPC850 integrates system functions, such as a versatile memory controller and a communications processor module (CPM) that incorporates a specialized, independent RISC communications processor (referred to as the CP). This separate processor off-loads peripheral tasks from the embedded MPC8xx core. The CPM of the MPC850 supports up to seven serial channels, as follows:
- One or two serial communications controllers (SCCs). The SCCs support Ethernet, ATM (MPC850SAR), HDLC and a number of other protocols, along with a transparent mode of operation. Advance Information MPC850EC/D Rev. 0.2, 04/2002 MPC850 (Rev. A/B/C) Comm unications Controller Hardware Specifications
- One USB channel
- Two serial management controllers (SMCs)
- One I C port
- One serial peripheral interface (SPI). Table 1 shows the functionality supported by the members of the MPC850 family. Additional documentation may be provided for parts listed in Table 1.
Table 1. MPC850 Functionality Matrix
Figure 1. MPC850 Microprocessor Block Diagram
- Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with thirty-two 32-bit general-purpose registers (GPRs) — Performs branch folding and branch prediction with conditional prefetch, but without conditional execution System Interface Unit Memory Controller Bus Interface Unit System Functions Real-Time Clock PCMCIA InterfaceBus Embedded 2-Kbyte I-Cache MMU 1-Kbyte D-Cache Data MMU Load/Store Instruction Bus Parallel I/O Baud Rate Generators Dual-Port RAM Interrupt Controller Four Timers 20 Virtual
2 Virtual
MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA — 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture) – Caches are two-way, set-associative – Physically addressed – Cache blocks can be updated with a 4-word line burst – Least-recently used (LRU) replacement algorithm – Lockable one-line granularity — Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and fully-associative instruction and data TLBs — MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
8 Mbytes; 16 virtual address spaces and eight protection groups
- Advanced on-chip emulation debug mode
- Data bus dynamic bus sizing for 8, 16, and 32-bit buses — Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian memory systems — Twenty-six external address lines
- Completely static design (0–80 MHz operation)
- System integration unit (SIU) — Hardware bus monitor — Spurious interrupt monitor — Software watchdog — Periodic interrupt timer — Low-power stop mode — Clock synthesizer — Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture — Reset controller — IEEE 1149.1 test access port (JTAG)
- Memory controller (eight banks) — Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM (SDRAM), static random-access memory (SRAM), electrically programmable read-only memory (EPROM), flash EPROM, etc. — Memory controller programmable to support most size and speed memory interfaces — Boot chip-select available at reset (options for 8, 16, or 32-bit memory) — Variable block sizes, 32 Kbytes to 256 Mbytes — Selectable write protection — On-chip bus arbiter supports one external bus master — Special features for burst mode support
- General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting
MPC850 (Rev. A/B/C) Hardware Specifications — Interrupt can be masked on reference match and event capture
- Interrupts — Eight external interrupt request (IRQ) lines — Twelve port pins with interrupt capability — Fifteen internal interrupt sources — Programmable priority among SCCs and USB — Programmable highest-priority request
- Single socket PCMCIA-ATA interface — Master (socket) interface, release 2.1 compliant — Single PCMCIA socket — Supports eight memory or I/O windows
- Communications processor module (CPM) — 32-bit, Harvard architecture, scalar RISC communications processor (CP) — Protocol-specific command sets (for example, GRACEFUL STOP TRANSMIT stops transmission after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD closes the receive buffer descriptor) — Supports continuous mode transmission and reception on all serial channels — Up to 8 Kbytes of dual-port RAM — Twenty serial DMA (SDMA) channels for the serial controllers, including eight for the four USB endpoints — Three parallel I/O registers with open-drain capability
- Four independent baud-rate generators (BRGs) — Can be connected to any SCC, SMC, or USB — Allow changes during operation — Autobaud support option
- Two SCCs (serial communications controllers) — Ethernet/IEEE 802.3, supporting full 10-Mbps operation — HDLC/SDLC™ (all channels supported at 2 Mbps) — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk — Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC))
- QUICC multichannel controller (QMC) microcode features — Up to 64 independent communication channels on a single SCC — Arbitrary mapping of 0–31 channels to any of 0–31 TDM time slots
MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA — Supports either transparent or HDLC protocols for each channel — Independent TxBDs/Rx and event/interrupt reporting for each channel
- One universal serial bus controller (USB) — Supports host controller and slave modes at 1.5 Mbps and 12 Mbps
- Two serial management controllers (SMCs) — UART — Transparent — General circuit interface (GCI) controller — Can be connected to the time-division-multiplexed (TDM) channel
- One serial peripheral interface (SPI) — Supports master and slave modes — Supports multimaster operation on the same bus
- One I C (interprocessor-integrated circuit) port — Supports master and slave modes — Supports multimaster environment
- Time slot assigner — Allows SCCs and SMCs to run in multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined — 1- or 8-bit resolution — Allows independent transmit and receive routing, frame syncs, clocking — Allows dynamic changes — Can be internally connected to four serial channels (two SCCs and two SMCs)
- Low-power support — Full high: all units fully powered at high clock frequency — Full low: all units fully powered at low clock frequency — Doze: core functional units disabled except time base, decrementer, PLL, memory controller, real-time clock, and CPM in low-power standby — Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for fast wake-up — Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt timer — Low-power stop: to provide lower power dissipation — Separate power supply input to operate internal logic at 2.2 V when operating at or below
25 MHz
— Can be dynamically shifted between high frequency (3.3 V internal) and low frequency (2.2 V internal) operation
- Debug interface — Eight comparators: four operate on instruction address, two operate on data address, and two operate on data
- 3.3-V operation with 5-V TTL compatibility on all general purpose I/O pins. Part III Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC850. Table 2 provides the maximum ratings. This device contains circuitry protecting against damage due to high-static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V CC ). Table 3 provides the package thermal characteristics for the MPC850.
Table 2. Maximum Ratings affect device reliability or cause permanent damage to the device.
Table 3 shows the thermal characteristics for the MPC850. Table 4 provides power dissipation information. Table 5 provides the DC electrical characteristics for the MPC850. Table 3. Thermal Characteristics Assumes natural convection and a single layer board (no thermal vias). Table 4. Power Dissipation (P
33 TBD 515 mW
40 TBD 590 mW
50 TBD 725 mW
Table 5. DC Electrical Specifications
2 BDIP/GPL_B5 , BR, BG, FRZ/IRQ6, CS[0:5], CS6/CE1_B, CS7/CE2_B, WE0/BS_AB0 /IORD, WE1/BS_AB1 /IOWR ,
Table 5. DC Electrical Specifications (continued)
10 MPC850 (Rev. A/B/C) Hardware Specifications MOTOROLA Layout Practices For most applications PI/O < 0.3 • PINT and can be neglected. If PI/O is neglected, an approximate relationship between PD and TJ is: Solving equations (1) and (2) for K gives: K = PD • (TA + 273°C) + θJA • PD (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA . Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA .
5.1 Layout Practices
Each VCC pin on the MPC850 should be provided with a low-impedance path to the board’s supply. Each GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip. The V CC power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip V CC and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MPC850 have fast rise and fall times. Printed circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the V CC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. Part VI Bus Signal Timing Table 6 provides the bus operation timing for the MPC850 at 50 MHz, 66 MHz, and 80 MHz. Timing information for other bus speeds can be interpolated by equation using the MPC850 Electrical Specifications Spreadsheet found at http://www.mot.com/netcomm. The maximum bus speed supported by the MPC850 is 50 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC850 used at 66 MHz must be configured for a 33 MHz bus). The timing for the MPC850 bus shown assumes a 50-pF load. This timing can be derated by 1 ns per 10 pF. Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet.
Table 6. Bus Operation Timing 1
50 MHz 66 MHz 80 MHz
15 MHz and MF <= 2)
Table 6. Bus Operation Timing 1 (continued)
calculated and can be taken directly from the frequency column corresponding to the frequency marked on the part. The following equations should be used in these calculations. CAP LOAD is the capacitance load on the signal in question. FFACTOR is the one defined for each of the parameters in the table. 2 Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value. the maximum allowed jitter on EXTAL can be up to 2%. output is relevant when the MPC850 is selected to work with internal bus arbiter. when the memory controller or the PCMCIA interface drives them). timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter.
Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, ACS = 11)
Figure 14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 21 provides the timing for the asynchronous external master control signals negation. Figure 21. Asynchronous External Master—Control Signals Negation Timing Table 7 provides interrupt timing for the MPC850. Table 7. Interrupt Timing
50 MHz 66MHz 80 MHz
Table 9 shows the PCMCIA port timing for the MPC850. Figure 27 provides the PCMCIA output port timing for the MPC850. Figure 27. PCMCIA Output Port Timing Figure 28 provides the PCMCIA output port timing for the MPC850. Figure 28. PCMCIA Input Port Timing Table 9. PCMCIA Port Timing
Table 10 shows the debug port timing for the MPC850. Figure 29 provides the input timing for the debug port clock. Figure 29. Debug Port Clock Input Timing Figure 30 provides the timing for the debug port. Figure 30. Debug Port Timings Table 10. Debug Port Timing
Table 11 shows the reset timing for the MPC850. Figure 31 shows the reset timing for the data bus configuration. Figure 31. Reset Timing—Configuration from Data Bus Table 11. Reset Timing
Figure 32 provides the reset timing for the data bus weak drive during configuration. Figure 32. Reset Timing—Data Bus Weak Drive during Configuration Figure 33 provides the reset timing for the debug port configuration. Figure 33. Reset Timing—Debug Port Configuration Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37. Table 12. JTAG Timing
Figure 34. JTAG Test Clock Input Timing Figure 35. JTAG Test Access Port Timing Diagram Table 12. JTAG Timing (continued)
Figure 36. JTAG TRST Timing Diagram Figure 37. Boundary Scan (JTAG) Timing Diagram
8.1 PIO AC Electrical Specifications
Table 13 provides the parallel I/O timings for the MPC850 as shown in Figure 38. Table 13. Parallel I/O Timing
29 Data-in setup time to clock high 15 — ns
31 Clock low to data-out valid (CPU writes data, control, or direction) — 25 ns
Figure 38. Parallel I/O Data-In/Data-Out Timing Diagram
8.2 IDMA Controller AC Electrical Specifications
Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42. Figure 39. IDMA External Requests Timing Diagram Table 14. IDMA Controller Timing
Figure 42. SDACK Timing Diagram—Peripheral Read
8.3 Baud Rate Generator AC Electrical Specifications
Table 15 provides the baud rate generator timings as shown in Figure 43. Figure 43. Baud Rate Generator Timing Diagram Table 15. Baud Rate Generator Timing
8.4 Timer AC Electrical Specifications
Table 16 provides the baud rate generator timings as shown in Figure 44. Figure 44. CPM General-Purpose Timers Timing Diagram
8.5 Serial Interface AC Electrical Specifications
Table 17 provides the serial interface timings as shown in Figure 45 to Figure 49. Table 16. Timer Timing Table 17. SI Timing 70 L1RCLK, L1TCLK frequency (DSC = 0) 1, 2 — SYNCCLK/2.
71 L1RCLK, L1TCLK width low (DSC = 0) 2 P + 10 — ns
73 L1RSYNC, L1TSYNC valid to L1xCLK edge Edge
74 L1xCLK edge to L1RSYNC, L1TSYNC, invalid
78 L1xCLK edge to L1ST n valid
83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns
3 P + 10 — ns
85 L1RQ
88 L1xCLK edge to L1SYNC valid (FSD = 00) CNT =
1 The ratio SyncCLK/L1RCLK must be greater than 2.5/1. 2 These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC,
Table 17. SI Timing (continued)
Figure 45. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
Figure 46. SI Receive Timing with Double-Speed Clocking (DSC = 1)
Figure 47. SI Transmit Timing Diagram
Figure 48. SI Transmit Timing with Double Speed Clocking (DSC = 1)
Figure 49. IDL Timing
8.6 SCC in NMSI Mode Electrical Specifications
Table 18 provides the NMSI external clock timing. Table 19 provides the NMSI internal clock timing. Table 18. NMSI External Clock Timing
100 RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this
1 The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater than or equal to 2.25/1.
101 RCLKx and TCLKx width low 1/SYNCCLK +5 — ns
107 RXDx hold time from RCLKx rising edge
2 Also applies to CD and CTS hold time when they are used as an external sync signal. Table 19. NMSI Internal Clock Timing
100 RCLKx and TCLKx frequency 1 (x = 2, 3 for all specs in this table)
1 The ratios SyncCLK/RCLKx and SyncCLK/TCLK1x must be greater or equal to 3/1.
0.00 SYNCCLK/3 MHz
102 RCLKx and TCLKx rise/fall time — — ns
2 Also applies to CD and CTS hold time when they are used as an external sync signals.
Figure 52. HDLC Bus Timing Diagram
8.7 Ethernet Electrical Specifications
Table 20 provides the Ethernet timings as shown in Figure 53 to Figure 55. Table 20. Ethernet Timing
123 RCLKx clock period
130 TCLKx clock period
Figure 53. Ethernet Collision Timing Diagram Figure 54. Ethernet Receive Timing Diagram
138 CLKOUT low to SD
1 The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1. 2 SD ACK is asserted whenever the SDMA writes the incoming frame destination address into memory. Table 20. Ethernet Timing (continued)
Figure 55. Ethernet Transmit Timing Diagram
8.8 SMC Transparent AC Electrical Specifications
Figure 21 provides the SMC transparent timings as shown in Figure 56. Table 21. Serial Management Controller Timing
150 SMCLKx clock period 1
1 The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.
154 SMRXDx/ SMSYNx
Transmit clock invert (TCI) bit in GSMR is set. CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 56. SMC Transparent Timing Diagram
8.9 SPI Master AC Electrical Specifications
Table 22 provides the SPI master timings as shown in Figure 57 and Figure 58. Table 22. SPI Master Timing
160 MASTER cycle time 4 1024 t cyc
161 MASTER clock (SCK) high or low time 2 512 t cyc
This delay is equal to an integer number of character-length clocks.1.
8.10 SPI Slave AC Electrical Specifications
Table 23 provides the SPI slave timings as shown in Figure 59 and Figure 60. Table 23. SPI Slave Timing
170 Slave cycle time 2 — t cyc
173 Slave clock (SPICLK) high or low time 1 — t
174 Slave sequential transfer delay (does not require deselect) 1 — t cyc
Figure 59. SPI Slave (CP = 0) Timing Diagram
Figure 60. SPI Slave (CP = 1) Timing Diagram
8.11 I2C AC Electrical Specifications
Table 24 provides the I2C (SCL < 100 KHz) timings. Table 24. I2C Timing (SCL < 100 KHZ)
Table 25 provides the I2C (SCL > 100 KHz) timings. 1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1. Table 25. I2C Timing (SCL > 100 KHZ)
200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz
200 SCL clock frequency (master) 1
1 SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
207 Data hold time 0 — s
208 Data setup time 1/(40 * fSCL) — s
209 SDL/SCL rise time — 1/(10 * fSCL) s
210 SDL/SCL fall time — 1/(33 * fSCL) s
Table 24. I2C Timing (SCL < 100 KHZ) (CONTINUED )
Figure 61 shows the I2C bus timing. Figure 61. I2C Bus Timing Diagram Table 26 provides information on the MPC850 derivative devices. Table 26. MPC850 Derivatives
1 Serial Communication Controller (SCC)
Table 27 identifies the packages and operating frequencies available for the MPC850.
9.1 Pin Assignments and Mechanical Dimensions of
non-JEDEC, are presented in this document. Table 27. MPC850 Package/Frequency/Availability
66 XPC850CZT66B
80 XPC850CZT80B
Figure 64 shows the non-JEDEC package dimensions of the PBGA. Figure 64. Package Dimensions for the Plastic Ball Grid Array (PBGA)—non-JEDEC Standard
0.30 C AB
- DIMENSIONING AND TOLERANCING PER ASME
- DIMENSIONS IN MILLIMETERS.
- DIMENSION b IS MEASURED AT THE MAXIMUM
- PRIMARY DATUM C AND THE SEATING PLANE ARE
Figure 65 shows the JEDEC package dimensions of the PBGA. Figure 65. Package Dimensions for the Plastic Ball Grid Array (PBGA)—JEDEC Standard
- DIMENSIONING AND TOLERANCING PER ASME
- DIMENSIONS IN MILLIMETERS.
- DIMENSION b IS MEASURED AT THE MAXIMUM
- PRIMARY DATUM C AND THE SEATING PLANE ARE
Table 28 lists significant changes between revisions of this document. Table 28. Document Revision History 0.1 11/2001 Removed reference to 5 Volt tolerance capability on peripheral interface pins. template, added this revision table.
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