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© 2010 Freescale Semiconductor, Inc. All rights reserved. Freescale Semiconductor Technical Data This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the .29 μm (HiP3) devices of the PowerQUICC II family of communications processors: the MPC8260 and the MPC8255. Throughout this document, the MPC8260 and the MPC8255 are collectively referred to as the MPC8260. Document Number: MPC8260EC Rev. 2, 05/2010
Contents
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
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Features
Figure 1 shows the block diagram for the MPC8260. Figure 1. MPC8260 Block Diagram
1 Features
- Dual-issue integer core — A core version of the EC603e microprocessor — System core microprocessor supporting fr equencies of 133–200 MHz (150–200 MHz for the MPC8255) — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm — PowerPC architecture-compliant memory management unit (MMU)
16 Kbytes
24 Kbytes
2 Virtual
3 MII 2 UTOPIA
8 TDM Ports2 Non-Multiplexed
1 Not on MPC8255
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 3 — Common on-chip processor (COP) test interface — High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency — Floating-point unit (FPU) Separate power supply for internal logic and for I/O Separate PLLs for G2 core and for the CPM — G2 core and CPM can run at different frequencies for power/performance optimization — Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios — Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus — Bus supports multiple master designs — Supports single- and four-beat burst transfers — 64-, 32-, 16-, and 8-bit port sizes c ontrolled by on-chip memory controller — Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus — Single-master bus, supports external slaves — Eight-beat burst transfers — 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller System interface unit (SIU) — Clock synthesizer — Reset controller — Real-time clock (RTC) register — Periodic interrupt timer — Hardware bus monitor and software watchdog timer — IEEE Std 1149.1™ JTAG test access port Twelve-bank memory controller — Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user- definable peripherals — Byte write enables and selectable parity generation — 32-bit address decodes with programmable bank size — Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine — Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) — Dedicated interface logic for SDRAM CPU core can be disabled and the device can be used in slave mode to an external core Communications processor module (CPM)
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2
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— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols — Interfaces to G2 core through on-chip 24-Kbyte dual-port RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capability — Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers — Three fast communications controllers (two on the MPC8255) supporting the following protocols: – 10/100-Mbit Ethernet/IEEE Std 802.3™ CDMA /CS interface through media independent interface (MII) – A TM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections – Transparent – HDLC—Up to T3 rates (clear channel) — Two multichannel controllers (MCCs) (only MCC2 on the MPC8255) – Each MCC handles 128 serial, full-duplex, 64-Kbps data channels. Each MCC can be split into four subgroups of 32 channels each. – Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC — Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: – Ethernet/IEEE 802.3 CDMA/CS – HDLC/SDLC and HDLC bus – Universal asynchronous receiver transmitter (UART) – Synchronous UART – Binary synchronous (BISYNC) communications – Transparent — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general circuit interface (GCI) controllers in time- division-multiplexed (TDM) channels – Transparent – UART (low-speed operation) — One serial peripheral interface identical to the MPC860 SPI — One inter-integrated circuit (I 2C) controller (identical to the MPC860 I2C controller) – Microwire compatible – Multiple-master, single-master, and slave modes
2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8260.
2.1 DC Electrical Characteristics
Table 1. Absolute Maximum Ratings 1 guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage. 2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. not exceed VDD/VCCSYN by more than 2.0 V during normal operation. 4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
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Table 2 lists recommended operational voltage conditions. negative direction (–5% and –0.1 Vdc). inputs are tied to an appropriate logic voltage level (either GND or VCC). MPC8280. Note that in PCI mode the I/O interface is different. Figure 2. Overshoot/Undershoot Voltage Table 2. Recommended Operating Conditions 1 conditions is not guaranteed. 2 Parts labeled with an “-HVA” suffix are 2.6-V devices.
Table 3 shows DC electrical characteristics. Table 3. DC Electrical Characteristics 1
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Table 3. DC Electrical Characteristics 1 (continued)
it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 2 The leakage current is measured for nominal VDD, VCCSYN, and VDD.
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2.2 Thermal Characteristics
Table 4 describes thermal characteristics.
2.3 Power Considerations
solving equations (1) and (2) iteratively for any value of TA. Table 4. Thermal Characteristics
1 Assumes a single layer board with no thermal vias
2 Natural convection
3 Assumes a four layer board
2.3.1 Layout Practices
fast output switching times. This recommendation particularly applies to the address and data buses. inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. the I/O power should be included when determining whether to use a heat sink. Table 5. Estimated Power Dissipation for Various Configurations 1
1 T est temperature = room temperature (25° C)
2 PINT = IDD x VDD Watts
3 2.8 Vddl does not apply to HiP3 Rev C silicon.
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2.4 AC Electrical Characteristics
buffer impedances are shown in Table 6. Table 7 lists CPM output characteristics. Table 8 lists CPM input characteristics. transitions from 90% to 10% of VCC. Table 6. Output Buffer Impedances 1 may vary by ±25% with process and temperature. Table 7. AC Characteristics for CPM Outputs 1
timing diagrams also apply when the falling edge is the active edge. Table 8. AC Characteristics for CPM Inputs 1
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Figure 3 shows the FCC external clock. Figure 3. FCC External Clock Diagram Figure 4 shows the FCC internal clock. Figure 4. FCC Internal Clock Diagram
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Figure 7 shows PIO, timer, and DMA signals. Figure 7. PIO, Timer, and DMA Signal Diagram Table 9 lists SIU input characteristics. Table 9. AC Characteristics for SIU Inputs 1 Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
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Figure 9 shows the interaction of several bus signals. Figure 9. Bus Signals Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity). Figure 10. Parity Mode Diagram
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3 Clock Configuration Modes
Clock configurations change only after POR is asserted.
3.1 Local Bus Mode
Table 12 describes default clock modes for the MPC8260. Table 13 describes all possible clock configurations when using the hard reset configuration sequence. Note also that basic modes are shown in boldface type. Table 12. Clock Default Modes Table 13. Clock Configuration Modes 1
Table 13. Clock Configuration Modes 1 (continued)
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MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 23 Pinout
4 Pinout
This section provides the pin assignments and pinout list for the MPC8260. 1 Because of speed dependencies, not all of the possible configurations in Ta ble 1 3 are applicable. 2 The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU ranges between 133–200 and the CPM ranges between 50–166 MHz. 3 Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that the resulting configuration does not exceed the frequency rating of the user’s part. 4 60x and local bus frequency. Identical to CLKIN.
5 CPM multiplication factor = CPM clock/bus clock
6 CPU multiplication factor = Core PLL multiplication factor
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4.1 Pin Assignments
Figure 13 shows the pinout of the MPC8260 480 TBGA package as viewed from the top surface. Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface
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Table 14. Pinout List (continued)
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Symbols used in Table 14 are described in Table 15. it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 3 Must be pulled down or left floating. Table 15. Symbol Legend
5 Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC8260.
5.1 Package Parameters
Package parameters are provided in Table 16. The package type is a 37.5 × 37.5 mm, 480-lead TBGA. Table 16. Package Parameters Table 15. Symbol Legend (continued)
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5.2 Mechanical Dimensions
Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature
- Dimensions and Tolerancing per
- Dimensions in millimeters.
- Dimension b is measured at the
MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 39
Ordering Information
6 Ordering Information
Figure 16 provides an example of the Freescale part numbering nomenclature for the MPC8260. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact your local Freescale sales office. Figure 16. Freescale Part Number Key
7 Document Revision History
Table 17 lists significant changes in each revision of this document. Table 17. Document Revision History 1.3 9/2005 Document template update. “Document Revision History” Table. II™ Family Reference Manual but had previously been omitted from Table 14. Addition of “Note” at bottom of page 5.
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1.0 3/2002 Table 14: modified notes to pins AE11 and AF25. Table 14: added note to pins AA1 and AG4 (Therm0 and Therm1). 83 MHz. 83 MHz is not supported on the MPC8260. Table 14: notes added to pins at AE11, AF25, U5, and V4. Table 17. Document Revision History (continued)
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