XP88C61140

XR88C681J-F EXAR | Alldatasheet

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Technical content

UART (DUART) Rev. 2.11 E2006 June 2006

FEATURES

D Two Full Duplex, Independent Channels D Asynchronous Receiver and Transmitter D Quadruple-Buffered Receivers and Dual Buffered Transmitters D Programmable Stop Bits in 1/16 Bit Increments D Internal Bit Rate Generators with More than 23 Bit Rates D Independent Bit Rate Selection for Each Transmitter and Receiver D External Clock Capability D Maximum Bit Rate: 1X Clock - 1Mb/s, 16X Clock - 125kb/s D Normal, AUTOECHO, Local LOOPBACK and Remote LOOPBACK Modes D Multi-function 16 Bit Counter/Timer D Interrupt Output with Eight Maskable Interrupt Conditions D Interrupt Vector Output on Acknowledge (40 Pin DIP and 44 Pin PLCC Packages Only) D Programmable Interrupt Daisy Chain D 8 General Purpose Outputs (40 Pin DIP and 44 Pin PLCC Packages Only) D 7 General Purpose Inputs with Change of States Detectors on Inputs (40 Pin DIP and 44 Pin PLCC Packages Only) D Multi-Drop Mode Compatible with 8051 Nine Bit Mode D On-Chip Oscillator for Crystal D Standby Mode to Reduce Operating Power D Compatible with the Motorola MC2681 and Signetics SCC2692 devices D Advanced CMOS Low Power Technology

APPLICATIONS

D Serial to Parallel/Parallel to Serial Converter D DTE for Modem Communication Systems GENERAL DESCRIPTION The EXAR Dual Universal Asynchronous Receiver and Transmitter (DUART) is a data communications device that provides two fully independent full duplex asynchronous communication channels in a single package. The DUART is designed for use in microprocessor based systems and may be used in a polled or interrupt driven environment. The XR88C681 device offers a single IC solution for the 8080/85, 8086/88, Z80, Z8000, 68xx and 65xx microprocessor families. The DUART is fabricated using advanced two layer metal, with a high performance density EPI/CMOS 1.8process to provide high performance and low power consumption, and is packaged in a 40 pin PDIP, a 28 pin PDIP, and a 44 pin PLCC.

ORDERING INFORMATION

Part No. Pin Package Operating Temperature Range XR88C681CJ 44 PLCC 0°C to 70°C XR88C681CN/40 40 CDIP 0°C to 70°C XR88C681CP/28 28 PDIP 0°C to 70°C XR88C681CP/40 40 PDIP 0°C to 70°C XR88C681J 44 PLCC -40°C to +85°C XR88C681N/40 40 CDIP -40°C to +85°C XR88C681P/28 28 PDIP -40°C to +85°C XR88C681P/40 40 PDIP -40°C to +85°C

Figure 1. Block Diagram of the XR88C681

Rev. 2.11 PIN CONFIGURATION VCC IP2 -CS RESET X1/CLK RXDA TXDA -WR -RD RXDB TXDB OP0OP1 D0D1 D2D3 D4D5 D6D7 -INTRGND 28 Lead PDIP (0.600”) 11 18 12 17 40 Lead PDIP, CDIP (0.600”) -INTR OP6 OP0 OP2 OP4 X1/CLK RXDA TXDA IP2 -CS RESET IP4/IEI IP5/IEO -IP6/IACK VCC GND OP7 OP1 OP3 OP5 -RD RXDB TXDB -WR IP0 IP3 IP1 XR-68C681CJ PLCC CS -RESET X1/CLK RXDA NC TXDA OP0 OP2 OP4OP5 OP3 OP1 TXDB NC RXDB -RD -WR IP0

44 Lead PLCC

-IP6/IACK IP2 GND NC -INTR

Rev. 2.11 PIN DESCRIPTION

44 PLCC 40 PDIP,

28 PDIP Symbol Type Description

1 NC No Connection. 2 1 1 A0 I LSB of Address Input. This input, along with Address Inputs, A1 - A3 are used to select certain registers within the DUART device, during READ and WRITE operations with the CPU. 3 2 IP3 (TXCA - I) (RXCA - Z) I Input Port 3. General Purpose Input - When the DUART is operating in the I-mode, this input can also be used as the external clock input for the Channel A Transmitter (TXCA). When the DUART is operating in the Z-Mode, this input can be used as the external clock input for the Channel A Receiv- er (RXCA). 4 3 2 A1 I Address Input. 5 4 IP1 (-CTSB) I Input Port 1. General Purpose Input - This input can also be used as the Active Low, “Channel B Clear to Send”input. (-CTSB) 6 5 3 A2 I Address Input. 7 6 4 A3 I MSB of Address Input. This input, along with Address In- puts, A0 - A2 are used to select certain registers within the DUART device, during READ and WRITE operations with the CPU. 8 7 IP0 (-CTSA) I Input 0. General Purpose Input - This input can also be used as the active-low, “Channel A Clear-to-Send”input. (-CTSA) 9 8 5 -WR I Write Strobe (Active-Low). A “low”on this input while -CS is also “low”writes the contents of the Data Bus into the ad- dressed register, within the DUART. The transfer occurs on the rising edge of -WR. 10 9 6 -RD I Read Strobe (Active Low). A “low”on this input while -CS is also “low”places the contents of the addressed DUART regis- ter, on the data bus. 11 10 7 RXDB I Receive Serial Data Input (Channel B). The least significant bit of the character is received first. If external receiver clock, RXCB, is specified, the data is sampled on the rising edge of this clock. 12 NC No Connect. 13 11 8 TXDB O Transmitter Serial Data Output (Channel B). The least sig- nificant bit of the character is transmitted first. This output is held in the high (marking state) when the transmitter is idle, disabled, or when the channel is operating in the local LOOP- BACK mode. If an external transmitter clock is specified, TXCB, the transmitted data is shifted out of the TSR (Trans- mitter Shift Register) on the falling the edge of this clock.

Rev. 2.11 (-RTSB) O Output 1 (General Purpose Output). This output can also be programmed to function as the active-low, “Channel B Request-to-Send”Output (-RTSB). 15 13 OP3 (TXCB_1X) (RXCB_1X) (-C/T_RDY) O Output 3 (General Purpose Output). This output port can also be programmed to function as: the “Channel B Trans- mitter 1X clock”output (TXCB_1X), the “Channel B Receiv- er 1X clock”output (RXCB_1X), or the open drain, active- low “Counter/Timer Ready”output (-C/T_RDY). 16 14 OP5 (-RXRDY/ -FFULL_B) O Output 5 (General Purpose Output Pin). This output port pin can also be programmed to function as the open-drain, active-low, Channel B “Receive Ready”or “Receiver FIFO Full”indicator output (-RXRDY_B/-FFULL_B). 17 15 OP7 (TXRDY_B) O Output 7. (General Purpose Output Pin). This output port pin can also be programmed to function as the open-drain, active-low, “Transmitter Ready”indicator output for Channel B (-TXRDY_B). 18 16 10 D1 I/O Bi-Directional Data Bus. 19 17 11 D3 I/O Bi-Directional Data Bus. 20 18 12 D5 I/O Bi-Directional Data Bus. 21 19 13 D7 I/O MSB of the Eight Bit Bi-Directional Data Bus. All transfers between the CPU and the DUART take place over this bus (consisting of pins D0 - D7). The bus is tri-stated when the -CS input is “high”, except during an IACK cycle (in the Z- Mode). 22 20 14 GND PWR Signal Ground. 23 NC No Connect. 24 21 15 -INTR O Interrupt Request Output (Active Low, Open Drain). -INTR is asserted upon the occurrence of one or more of the chip’s maskable interrupting conditions. This signal will re- main asserted throughout the Interrupt Service Routine and will be negated once the condition(s) causing the Interrupt Request has been eliminated. 25 22 16 D6 I/O Bi-Directional Data Bus. 26 23 17 D4 I/O Bi-Directional Data Bus. 27 24 18 D2 I/O Bi-Directional Data Bus. 28 25 19 D0 I/O LSB of the Eight Bit Bi-Directional Data Bus. All transfers between the CPU and the DUART take place over this bus. The bus is tri-stated when the -CS input is “high”, except during an IACK cycle (in the Z-Mode). 29 26 OP6 (-TXRDY_A) O Output 6 (General Purpose Output). This output pin can also be programmed to function as the open drain, active- low, “Transmitter Ready”indicator output for Channel A (-TXRDY_A).

Rev. 2.11 (RXRDY/ FFULL_A) O Output 4 (General Purpose Output). This output pin can also be programmed to function as the open-drain, active-low, “Receiver Ready”or “FIFO Full”indicator output for Channel A. (-RXRDY_A/-FFULL_A) 31 28 OP2 (TXCA_16) (TXCA-1X) (RXCA_1X) O Output 2 (General Purpose Output). This output pin can also be programmed to function as any of the fol- lowing: The Channel A Transmitter 16X or 1X clock output (TXCA_16X or TXCA_1X), or the Channel A Receiver 1X clock output (RXCA_1X). 32 29 20 OP0 (-RTSA) O Output 0 (General Purpose Output). This output pin can also be programmed to function as the active-low, Request-to-Send output for Channel A (-RTSA). 33 30 21 TXDA O Transmitter Serial Data Output (Channel A). The least significant bit of the character is transmitted first. This output is held in the marking (high) state when the transmitter is idle, disabled, or operating in the Local LOOPBACK mode. If an external transmitter clock is specified, TXCA, the data is shifted out of the TSR (Transmitter Shift Register) on the falling the edge of the clock. 34 NC No Connect. 35 31 22 RXDA I Receive Serial Data Input (Channel A). The least significant bit of the character is received first. If an external receiver clock, RXCA, is specified, the data is sampled on the rising edge of the clock. 36 32 23 X1/CLK I Crystal Output of External Clock Input. This pin is the connection for one side of the crystal and a capaci- tor to ground when the internal oscillator is used. If the oscillator is not used, an external clock signal must be supplied at this input. In order for the XR88C681 device to function properly, the user must supply a signal with frequencies be- tween 2.0MHz and 4.0MHz. This requirement can be met by either a crystal oscillator or by the external TTL-compatible clock signal. 37 33 24 X2 O Crystal Input. Connection for the one side of the crys- tal (opposite of X1/CLK). If the oscillator is used, a capacitor must also be connected from this pin to ground. This pin must be left open if an external clock is supplied at X1/CLK.

Rev. 2.11 38 34 25 RESET I Master Reset (Active High). Asserting this input clears in- ternal registers, SR, ISR, IMR, OPR, OPCR, and initializes the IVR to 0F16. Asserting this input also stops the Counter/ Timer, puts OP0 - OP7 in the high state, and places both serial channels in the inactive state with TXDA and TXDB outputs marking (high). 39 35 26 -CS I Chip Select (Active Low). The data bus is tri-stated when -CS is “high.” Data transfers between the CPU and the DUART via D0 - D7 are enabled when -CS is “low”. 40 36 27 IP2 (C/T_EX) I Input 2. (General Purpose Input). This input pin can also be programmed to function as the “Counter/Timer external clock”input (C/T_EX). 41 37 IP6 (RXCB) I Input 6 (I-Mode). General Purpose Input pin. This input pin can also be programmed to function as the External Receiv- er Clock for Channel B (RXCB). 41 37 -IACK I Interrupt Acknowledge Input (Z-Mode). Active Low. This input is the CPU’s response to the Interrupt Request issued by the DUART device. When the CPU asserts this input, it indicates that the DUART’s interrupt request is about to be serviced, and that the very next cycle will be an Inter- rupt Acknowledge Cycle. The DUART will respond to the CPU’s Interrupt Acknowledge by placing the contents of the Interrupt Vector Register (IVR) on the data bus (D0 - D7). 42 38 IP5 (TXCB) I Input 5 (I-Mode). General Purpose Input pin. This pin can also be configured to function as the external clock input for the Transmitter of Channel B (TXCB). 42 38 IEO (Z-Mode) O Interrupt Enable Output (Z-Mode). Active High. This output pin is normally “high”. However, either of the following two conditions can cause this output pin to be ne- gated (toggled “low”). 1. If the IEI (Interrupt Enable Input) pin is “low”. If IEO is “low”because of the IEI pin, IEO will toggle “high”once the IEI has toggled “high”. 2. The DUART has issued an Interrupt Request to the CPU (-INTR pin is toggled “low”). If IEO is “low”because the DUART has requested an Interrupt, then IEO will remain “low”, throughout the Interrupt Service Routine, until the CPU has invoked the “”command. 43 39 IP4 (RXCA) I Input 4 (I-Mode). General Purpose Input pin. This input pin can also be configured to function as the external clock input for the Receiver of Channel A (RXCA). 43 39 IEI (Z-Mode) I Interrupt Enable Input (Z-Mode). Active High. If this active-high input is at a logic “high”, the DUART is ca- pable of generating all non-masked Interrupt Requests to the CPU. If this input is at a logic “low”, the DUART is inhibited from generating any Interrupt Requests to the CPU. 44 40 28 VCC PWR Most Positive Power Supply.

Rev. 2.11 DC ELECTRICAL CHARACTERISTICS1, 2, 3 Test Conditions: TA = 0 - 70°C, VCC = 5V ¦ 5% unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit Conditions VIL Input Low Voltage 0.5 0.8 V VIH Input High Voltage 2.0 VCC V VIH Input High Voltage (Military) 2.2 V TA = -55°C to 125°C VIHX1 Input High Voltage (X1/CLK) 4.0 VCC V VOL Output Low Voltage 0.4 V IOL = 2.4mA VOH Output High Voltage 2.4 V IOH = -400A IIL Input Leakage Current -25 25 A VIN = 0 to VCC IILSEL Select Pin Leakage Current -30 +30 A VIN = 0 to VCC IX1L X1 Input Low Current -20 A VIN = 0 IX2L X2 Input Low Current -7 mA IXIH X1 Input High Current 20 A VIN = VCC IX2H X2 Input High Current 20 A VIN = VCC ILL Data Bus Tri-State Leakage Current -10 10 A VO = 0 to VCC IOC Open Drain Output Leakage Current -10 10 A VO = 0 to VCC ICCA Power Supply Current4 6 15 mA Active Mode ICCS Power Supply Current4 3 10 mA Standby Mode Notes 1.Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25°C, VCC = 5V and typical processing parameters. 2.All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns 3.For prime grade N, P, J, L, M, ML, VCC = 5V + 10%. 4.Measured operating with a 3.6864MHz crystal and with all outputs open.

Rev. 2.11 AC ELECTRICAL CHARACTERISTICS 1, 2, 3 Test Conditions: TA = 0 - 70°C, VCC = 5V ¦ 5% unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit Conditions Reset Timing (See Figure 51) tRES RESET Pulse Width 1.0 A XR88C681 Read and Write Cycle Timing (Figure 52)4 tAS A0-A3 Setup Time to RD, WR Low 10 ns tAH A0-A3 Hold Time from RD, WR Low 0 ns tCS CS Setup Time to RD, WR Low 0 ns tCH CS Hold Time from -RD, -WR High 0 ns tRW -RD, -WR Pulse Width 225 ns tDD Data Valid from -RD Low 60 175 ns tDF Data Bus Floating from -RD High 10 100 ns tDS Data Setup Time to -WR High 100 ns tDH Data Hold Time from -WR High 5 ns tRWD High Time Between Reads and/or Writes5, 6 100 ns Z-Mode Interrupt Cycle Timing (Figure 53) tDIO IEO Delay Time from IEI 100 ns tIAS -IACK Setup Time to -RD Low7 ns tIAH -IACK Hold Time from -RD High 0 ns tEIS IEI Setup Time to RD Low 50 ns tEOD IEO Delay Time from -INTR Low 100 ns Port Timing (Figure 54)4 tPS Port Input Setup Time to -RD/-CS Low 0 ns tPH Port Input Hold Time from -RD/-CS High 0 ns tPD Port Output Valid from -WR/-CS High 400 ns Interrupt Output Timing (Figure 55) tIR -INTR or OP3 - OP7 when used as Interrupts High from: Clear of Interrupts Status Bits in ISR or IPCR Clear of Interrupt Mask in IMR 300 300 ns ns Clock Timing (Figure 56)

Rev. 2.11 Symbol ConditionsUnitMax.Typ.Min.Parameter tCLK X1/CLK (External) High or Low Time 100 ns tCLK X1/CLK Crystal or External Frequency

7.372 MHz

Rev. 2.11 AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONT’D) Test Conditions: TA = 0 - 70°C, VCC = 5V ¦ 5% unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit Conditions Clock Timing (Figure 56) (Cont’d.) tCTC Counter/Timer External Clock High or Low Time (IP2) 100 ns tCTC Counter/Timer External Clock Frequency 0 7.372 MHz tRTX RXCn and TXCn (External) High or Low Time8 220 ns fRTX RXCn and TXCn (External) Frequency 16X 16.0 1.0 MHz MHz Transmitter Timing (Figure 57) tTXD TXD Output Delay - TXC (External) Low 350 ns tTCS TXD Output Delay - TXC (Internal) Output Low 150 ns tRXS RXD Data Setup Time to RXC (External) High 240 ns tRXH RXD Data Hold Time from RXC (External) High 200 ns Notes 1.Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25°C, VCC = 5V and typical processing parameters. 2.All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns 3.AC test conditions for outputs: CL = 50pF, RL = 2.7k to VCC. 4.If -CS is used as the strobing input, this parameter defines the minimum high time between -CSs. 5.Consecutive write operations to the same register require at least three edges of the X1 clock between writes. 6.This specification imposes a 6 MHz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous read or write cycle. A higher 68000 clock can be used if this is not the case. 7.This specification imposes a lower bound on -CS and -IACK low, guaranteeing that they will be low for at least one CLK period. 8.The minimum high time must be at least 1.5 times the X1/CLK period and the minimum low time must be at least equal to the X1/CLK period if either channel’s Receiver is operating in external 1X clock mode. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS1 All Voltages with 1.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat- ing only, and functional operation of the device at these or any other conditions above those indicated in the “Electrical Characteris- tics”section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. 2.11 2.This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive stat- ic charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltage larger than the rated maximum.

Rev. 2.11 SYSTEM DESCRIPTION The XR88C681 consists of two independent, full-duplex communication channels; each consisting of their own Transmitter and Receiver. Each channel of the DUART may be independently programmed for operating mode and data format. The DUART can interface to a wide range of processors with a minimal amount of components. The operating speed of each receiver and transmitter may be selected from one of 23 internally generated fixed bit rates, from a clock derived from an internal counter/timer, or from an externally supplied 1x or 16x clock. The bit rate generator (the source of the 23 different fixed bit rates) can operate directly from a crystal connected across two pins or from an external clock. The ability to independently program the operating speed of the receiver and transmitter of each channel makes the DUART attractive for split speed channel applications such as clustered terminal systems. Receiver data is quadrupled buffered and the transmitter data is dual-buffered via on-chip FIFOs in order to minimize the risk of receiver overrun and to reduce overhead in interrupt driven applications. The DUART also provides a flow control capability to inhibit transmission from a remote device when the buffer of the receiving DUART is full, thus preventing loss of data. The DUART also provides a general purpose 16 bit counter/timer (which may also be used as programmable bit rate generators), a 7 bit multi-purpose input port and an 8 bit multi-purpose output port (for the 40 pin DIP and 44 pin PLCC packages only). PRINCIPLES OF OPERATION Figure 1 presents an overall block diagram of the DUART. As illustrated in the block diagram, the DUART consists of the following major functional blocks: D Data Bus Buffer D Interrupt Control D Input Port D Serial Communication Channels A and B D Operation Control D Timing Control D Output Port A. DATA BUS BUFFER The data bus buffer provides the interface between the internal (within the chip) and external data buses. It is controlled by the operation control block to allow data transfers to take place between the host CPU and the DUART. B. OPERATION CONTROL BLOCK The control logic of the Operation Control block receives operating commands from the CPU and generates proper signals to the various sections of the DUART. The Operation Control Block functions as the user interface to the rest of the device. Specifically, it is responsible for DUART Register Address Decoding, and Command Decoding. Therefore all commands to set baud rates, parity, other communication protocol parameters, start or stop the Counter/Timer or reading a “status register”to monitor data communication performance must go through the Operation Control Block. The Operation Control Block will control DUART performance based upon the following input signals. Address Inputs, A0 - A3 -RD -WR -CS RESET When using the 6800 family processor, the DUART will require some glue logic. Interfacing a 6800 Family Processor to the DUART can be easily achieved by including a small amount of external logic devices, as depicted in Figure 2.

Figure 2. External Logic Circuitry required to interface a 6800 Family Additionally, the DUART contains the following registers that support/control both channels. as the parallel ports and the counters/timers.

00 Mode Register,

01 Status Register,

02 Masked Interrupt

03 Rx Holding Register,

04 Input Port Change

05 Interrupt Status

06 Counter/Timer Upper

07 Counter/Timer Lower

08 Mode Register,

09 Status Register,

Table 1. DUART Port and Register Addressing Note: The shaded blocks are not Read/Write registers but are rather “Address-Triggered”Commands. of the MR1n register to that of the MR2n register, immediately following any Read or Write access to the MR1n register.

Registers are discussed in detail in Section G.3. commands. The bit format for each Command Register is presented herewith. Table 2. (CRA, CRB) Bit Format for Command Registers of Channels A & B or disable the Transmitter and/or Receiver. effects system (or chip) level operation. ceiver as if a Hardware Reset has been applied. The Receiver is disabled and the FIFO is flushed. transmitter as if a Hardware Reset had been applied. The TXDn output is forced to a high level. Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers,

Overrun Error (OE) status bits, SR[7:3]. only upon the character that is at the top of the RHR. nel’s break change interrupt status bit. TXEMP must be true before the break will begin. fore the next character, if any, is transmitted. “Receiver BRG Select Extend Bit”to 1. nel’s “Receiver BRG Select Extend Bit”to 0. “Transmitter BRG Select Extend Bit”to 1. nel’s “Transmitter BRG Select Extend Bit”to 0.

the Interrupt-Under-Service (IUS) latch to be reset. and resumes normal operation.

registers, their address location (within the DUART). Table 4. Listing and Brief Description of Interrupt System Registers Table 5. ISR Bit Format service this interrupt by reading the IPCR (if ISR[7] = 1). For a detailed description of the IPCR, see Section F.

1. Write the appropriate data to the lower nibble of the

“Input Port Change”Interrupt request.

Rev. 2.11 2. Write a logic “1”to IMR[7]. ISR[6] Delta Break Indicator - Channel B When this bit is set, it indicates that the Channel B receiver has detected the beginning or end of a received break (RB). This bit is cleared (or reset) when the CPU invokes a channel B “RESET BREAK CHANGE INTERRUPT” command (see Table 3). For more information into the DUART’s response to a BREAK condition, please see Section G.2. ISR[5] RXRDY/FFULL B - Channel B Receiver Ready or FIFO Full The function of this bit is selected by programming MR1B[6]. If programmed as the Receiver Ready indicator (RXRDYB), it indicates that at least one character of data is in RHRB and is ready to be read by the CPU. This bit is set when a character is transferred from the receiver shift register to RHRB and is cleared when the CPU reads the RHRB. If there are still more characters in RHRB after the read operation, the bit will be set again after RHRB is “popped”. If this bit is programmed as FIFO full indicator (FFULLB), it is set when a character is transferred from the RSR to RHRB and the transfer causes RHRB to become full. This bit is cleared when the CPU reads RHRB; and thereby “popping”the FIFO, making room for the next character. If a character is waiting in the RSR because RHRB is full, this bit will be set again after the read operation, when that character is loaded into RHRB. Note: If this bit is configured to reflect the FFULLB indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in RHRB, following data reception. Hence, it is possible that the last two char- acters in a string of data (being received) could be lost due to this phenomenon. ISR[4] TXRDYB - Channel B Transmitter Ready This bit is a duplicate of TXRDY B, SRB[2]. This bit, when set, indicates that THRB is empty and is ready to accept a character from the CPU. The bit is cleared when the CPU writes a new character to THRB; and is set again, when that character is transferred to the TSR. TXRDYB is set when the transmitter is initially enabled and is cleared when the transmitter is disabled. Characters loaded into THRB while the transmitter is disabled will not be transmitted. ISR[3] Counter Ready In the TIMER mode, the C/T (Counter/Timer) will set ISR[3] once each cycle of the resultant square wave (available at the OP3 pin). ISR[3] will be cleared by invoking the “STOP COUNTER”command. Bear in mind, that in the TIMER mode, the “STOP COUNTER” command will not stop the C/T. In the COUNTER mode, this bit is set when the counter reaches the terminal count (000016) and is cleared when the counter is stopped by a “STOP COUNTER” command. When the Counter/Timer is in the COUNTER Mode, the “STOP COUNTER” command will stop the Counter/Timer. ISR[2]: Delta Break A - Channel A Change in Break Assertion of this bit indicates that the channel A receiver has detected the beginning of or the end of a received break (RB). This bit is cleared when the CPU invokes a channel A “RESET BREAK CHANGE INTERRUPT” command. For more information into the DUART’s response to a BREAK condition, please see Section G.2. ISR[1] RXRDYA/FFULL A - Channel A Receiver Ready or FIFO Full The function of this bit is selected by programming MR1A[6]. If programmed as the Receiver Ready indicator (RXRDYA), this bit indicates that there is at least one character of data in RHRA, and is ready to be read by the CPU. This bit is set when a character is transferred from the RSR to RHRA and is cleared when the CPU reads (or “pops”) RHRA. If there are still more characters in RHRA, following the read operation, the bit will be set again after RHRA is “popped”. If this bit is programmed as the FIFO (RHR) full indicator (FFULLA), it is set when a character is transferred from the RSR to RHRA and the newly transferred character causes RHRA to become full. This bit is cleared when the CPU reads RHRA. If a character is waiting in the RSR because RHRA is full, this bit will be set again, following the read operation, when that character is loaded into RHRA. Note: If this bit is configured to reflect the FFULLA indicator, this bit will not be set (nor will produce an interrupt request) if

This bit is a duplicate of TXRDY A, SRA[2]. enabled and is cleared when the transmitter is disabled. disabled will not be transmitted. bit-format of the IMR is essentially the same as the ISR. Table 6. IMR Bit Format FF16 (all “1”s) to this registers. therefore not be read by the processor. ANDing the ISR and IMR together. eliminated via use of the MISR. when the DUART is commanded into the special Z-Mode.

Rev. 2.11 Receiver problems such as Parity Error (PE), Receiver Overrun Error (OE), or Framing Error (FE). The DUART also does not offer the user to ability to configure one of the output ports to relay the occurrence of any of these conditions. Therefore, unless the user is implementing some sort of “Data Link Layer”error checking scheme such as CRC, the user is advised to “validate” the received data by frequently reading the Status Register; and checking for any non-zero upper-nibble values. This is especially the case if the user has set the Error Mode to “Character”(MR1n[5] = 0). C.6 Servicing DUART Interrupts Interrupt servicing with the XR88C681 DUART falls into two broad categories: I-Mode and Z-Mode. I-Mode has historically been referred to as the “Intel”Mode. Likewise, the Z-Mode has been referred to as the “Zilog”Mode. When the DUART is operating in the Z-Mode, the DUART will place an 8 bit “interrupt vector”on the data bus, to the CPU, during the “Interrupt Acknowledge”or IACK cycle. The CPU will read this interrupt vector from the Data Bus, and determine (from the Interrupt Vector data) the location of the appropriate interrupt service routine, in system memory. Additionally, the Z-Mode gives the user a hardware approach to prioritize the interrupt requests among numerous peripheral devices. This phenomenon is discussed in greater detail in Section C.6.2. When the DUART is operating in the I-Mode, the DUART will not provide any interrupt vector information to the CPU, during the IACK cycle. Interrupt Vector information, or any means to route program control to the appropriate Interrupt Service Routine, is accomplished external to the DUART. The DUART will be in the I-Mode following power up or a hardware reset. The user must invoke the “Set Z-Mode” command, in order to command the DUART into the Z-Mode. Although the I-Mode has been referred to as the “Intel” Mode, and the Z-Mode as the “Zilog”Mode; this does not mean that the user should only operate the DUART in the Z-Mode when interfacing a Zilog microprocessor, or in the I-Mode when interfacing to an Intel microprocessor. The division between I-Mode and Z-Mode is not necessary along “corporate”lines. If you are interfacing the DUART to the following microprocessors/ microcontrollers, then the DUART must operate in the I-Mode. D 8051P D 8080CP D 8085P D 68HC11C D Z-80P (Interrupt Modes 0 and 1) However, the DUART should be operating in the Z-Mode when interfacing the following microprocessors/ microcontrollers. D 8088P D 8086P D 80286 - 80486Ps D PentiumP D Z-80P (Interrupt Modes 2) The next few sections will provide detailed discussions of DUART/Microprocessor interfacing and interrupt processing on each of the above-mentioned microprocessors. From this discussion, a detailed description of I-Mode Interrupt processing and Z-Mode Interrupt processing will emerge. C.6.1 I-Mode Interrupt Servicing The DUART will be in the I-Mode following power up of the IC, or a hardware reset. In general, a CPU interfacing to a DUART operating in the I-Mode, will function as follows, during interrupt servicing. If the DUART requires interrupt service from the CPU, it will asserts the -INTR pin to the CPU. Once the CPU has detected the interrupt request, it will determine the location of the appropriate interrupt service routine, and will branch program control to that location. The CPU will accomplish all of this without providing an “Interrupt Acknowledge”signal or any further interaction with the DUART. Once the CPU has eliminated the cause(s) of the DUART’s interrupt request, the DUART will then negate its -INTR pin. The CPU will then exit the “DUART” interrupt service routine and will resume normal processing. In general there are two approaches that CPUs commonly use to locate the appropriate interrupt service routine, when interfaced with an I-Mode DUART. D Direct Interrupt Processing D (External) Vectored-Interrupt Processing Direct Interrupt Processing If a CPU employs “Direct Interrupt Processing”then once the CPU has detected the interrupt request, and has completed its current instruction, the CPU will branch

program control to a specific location in system memory. fixed by the CPU circuitry itself. CALL instruction to a special “RESTART subroutine”. routine) resides at this location in memory. presented in greater detail in the following sections. Table 7. Table 7 also presents the type of interrupt processing that is employed by each of these Ps/Cs. for “CALL”instructions to the Interrupt Service Routines. the “CALL”instructions on to the Data Bus. has the exact same “vector”options as does the 8080A P. interrupt request pin is asserted. Table 7. Summary of P/C and their types of Interrupt Processing (I - Mode) The information presented in Table 7 is discussed in detail in the following sections.

Figure 4. Pin Out of the 8051 Microcontroller ports have alternate functions, as will be discussed here. lines or as external inputs to the third timer. more than 256 bytes of external data memory (A8 - A15).

functions. Each of these pins have an alternate purpose, as listed in Table 8. Table 8. Alternate Functions of Port 3 Pins either of these inputs are asserted. Table 9. Interrupt Service Routine locations (in routine) is located at one of these address locations. demultiplex the Address and Data bus signals. XR88C681 DUART can be interfaced to the 8051C.

8051 CPU XR88C681

Figure 5. An Approach to Interfacing the XR88C681 DUART to the 8051 Microcontroller service routine and resume normal operation. other chips, in order to create a “complete”CPU module.

Table 10. 8080A and 8085 CPU Restart Instructions control will be branched to the “Restart Address”location. location in memory (see Table 10). Service Routine is located at 002016 in memory. -INTA signals are both routed to a two-input OR gate. U3. This value is the op-code for the “RST 4”command.

Figure 7. Circuit Schematic depicting approach to Interface the XR88C681 DUART requested the interrupt service. bits of the Address Bus share pins with the 8 bit Data Bus. demultiplex the Address and Data buses.

Figure 8 presents a schematic of the 8085 CPU Module. Figure 8. A Schematic of the 8085 CPU Module

8085 CPU

are connected to the -RD and -WR pins of the DUART). to the -RD and -WR pins of the DUART, respectively).

Figure 9. Schematic of the XR88C681 Interface to the 8085 CPU Module (Memory Mapped).

8085 CPU Module Interrupt Structure

supports “External Vectored Interrupt” processing.

Figure 10. The XR88C681/8085 CPU Interface for Direct Interrupt Processing case, the Interrupt Service Routine for the DUART must begin at 002016 in system memory.

Figure 11. The XR88C681/8085 CPU Interface for Vectored Interrupt Processing (In-

Rev. 2.11 Accumulator. Three of the input pins support input capture functions; and four of the output pins support output compare functions. Port B Port B consists of 8 output pins. If the 68HC11 C is operating in the single chip mode, this port functions as a general purpose output port. However, if the 68HC11 is operating in the expanded-multiplexed mode, then this port will function as the upper address byte for memory/peripheral device interfacing (A8 - A15). Port C Port C consists of 8 bi-directional pins. When the 68HC11 is operating in the single-chip mode, this port functions as a general purpose bi-directional port. However, if the 68HC11 is operating in the expanded-multiplexed mode then this port will function as the multiplexed address/data bus (AD0 - AD7). Specifically, during the first half of a memory cycle, this port will function as the lower address byte (Port B is the upper address byte) for addressing memory devices and peripheral components. During the second half of the memory cycle, this port will function as the bi-directional data bus. This port can be demultiplexed via the use of the AS (Address Strobe) pin and a 74LS373 latch device. Port D Port D consists of 8 bi-directional pins. However, this port can be configured to support the on-chip Serial Peripheral Interface (SPI), and Serial Communications Interface (SCI). Port E Port E consists of either 4 or 8 inputs (depending upon the packaging option). This port can be configured to function as a general purpose input or as the inputs to the on-chip A/D converter. There are numerous other pins that are pertinent for interfacing to the XR88C681 DUART device. Some of these pins are discussed here. IRQ This is the “maskable”interrupt request input. If this input is asserted (e.g., toggled “low”), then the 68HC11 C will branch program control to FFF2, FFF3 in system memory (on-chip ROM). The user is responsible for insuring that the appropriate interrupt service routine resides at this location in memory. AS/STRA AS or “Address Strobe”can be used to demultiplex the address/data bus of Port C. This pin is at a logic “high” during the first half of a memory cycle; and at a logic “low” during the second half of a memory cycle. If the 68HC11 is intended to operate in the expanded-multiplexed mode and interface to more than 256 bytes of addressable memory space, then both Ports B and C are required as shown in Figure 13. Figure 13 also illustrates how the XR88C681 DUART could be connected to the 68HC11 C for interrupt driven operation. If the DUART requests an interrupt, its active low -INTR pin will be asserted (toggle low), which will, in turn, cause the -IRQ pin of the CPU to be asserted. When this occurs the C will continue executing its current instruction. After completion of this instruction, program control will shift to location FFF2, FFF3 in system memory. The user is responsible to insure that the DUART’s interrupt service routine resides at this location in memory. The C will not issue an interrupt acknowledge signal to the DUART. Instead, the C will just processes through the interrupt service routine. Once the C has eliminated the cause(s) of the DUART’s interrupt request, the -INTR pin will be negated and the C will return from the Interrupt Service Routine and resume normal processing. One more point should be mentioned about Figure 13. The glue-logic circuitry required to generate the -WR, -RD, and the RESET signals for the DUART, from the -R/W, -RESET, and E clock presented in Figure 2. This circuitry has also been included in Figure 14.

Figure 13. XR88C681/MC68HC11 Microcontroller Interfacing Approach

Figure 14. Glue Logic Circuitry Required to Interface the MC68HC11C to the XR88C681 DUART function as follows during interrupt servicing. IACK (Interrupt Acknowledge) signal back to the DUART. “interrupt vector”information). location of the interrupt service routine.

Figure 17. Pin Out of the Z80 CPU Device control bus signals from these CPU control pins.

Figure 18. Schematic of Z-80 CPU Module only concerned with the -INT pin. CPU and will be discussed in the following sections.

the appropriate Interrupt service routine resides. Table 12. Z-80 CPU Restart Instructions control will be branched to the “Restart Address”location. operating in Interrupt Mode 0. interrupt request and returns to normal operation. prior to interrupt servicing.

Note: The LSB of the IVR is always set to “0”once read by the CPU. Interrupt Service Routines must begin at even ddresses. Table 13. The Relationship between the Contents of the Interrupt Vector Register (of the DUART) Additionally, the user must be aware of the contents that he/she loads into the I Register of the CPU, during run time. Figure 19. Schematic of an Approach to Interface the DUART to the Z-80

package. These additional labels will be explained later in this text.

8086 CPU

Figure 20. Pin Out of the 8086 Microprocessor Device low by multiplexing the functions of many of these pins.

generator to form a CPU module.

24 HOLD -RQ/-GT0

25 HLDA -RQ/-GT1

27 M/-IO -S2

28 DT/R -S1

30 ALE QS0

Table 14. MN/-MX Mode and Function of Pins 24-31 of 8086 CPU Device. the memory and I/O control bus signals. -S2 “max”mode status signals. Table 15. 8086 Processor State/8288 Bus Controller Active Output as a function of -S0, -S1 and -S2

Figure 21 and Figure 22 present the 8086 CPU Mode, when operating in the “min”and “max”modes, respectively. Figure 21. Schematic of the 8086 CPU Mode (Min Mode)

8288 Bus Controller

Figure 22. Schematic of the 8086 CPU Mode (Max Mode)

8086 P can accommodate up to 256 different interrupt

DUART interfacing to a “min”Mode 8086 CPU device. for the IEI input to the DUART device.

Figure 23. Schematic of the XR88C681 DUART Device Interfacing to a block for the XR88C681 device.

Figure 24. Block Diagram of DUART Timing Control Block schematic for the XTAL Oscillator circuitry.

diagram of the BRG circuitry is presented in Figure 27. Figure 27. Block Diagram of the Bit Rate Generator portion of the Timing Control Block

bit rate generator for both Transmitters and Receivers. Figure 28. A Block Diagram of the Circuitry Associated with the Table 16. ACR[6:4] Bit Field Definition - C/T

Rev. 2.11 D.3.1 Timer Mode: Please note that of the two C/T Modes, the Timer Mode is the only mode which is relevant to the function of Bit Rate Selection. However, for completeness, the Counter Mode is also discussed here. In the Timer mode, the C/T acts as a programmable divider and generates a square wave whose period is twice the value (in clock periods) of the contents of the Counter/Timer Registers, CTUR and CTLR. The C/T can be used as a programmable bit rate generator in order to produce a 16X clock for any bit rate not provided by the BRG. The square-wave, originating from the C/T is output on Output Port pin, OP3. If the C/T is programmed to operate in the Timer mode, the frequency of the resulting C/T square wave can be expressed as follows: C/T Output Frequency = Frequency of Selected Timing Source 2·([CTUR]·28 + [CTLR] ) Where: [CTUR] = the contents of the CTUR register in decimal form [CTUR] = the contents of the CTLR register in decimal form Since the C/T Output is handled as a 16X clock signal by the DUART circuitry, the resulting bit rate is 1/16 the frequency of the C/T Output signal. Therefore, the bit rate, derived from the C/T can be expressed as follows: Bit Rate = Frequency of Selected Timing Source 32·([CTUR]·28 + [CTLR] ) The contents of the CTUR and CTLR registers may be changed at any time, but will only begin to take effect at the next half cycle of the square wave. The C/T begins operation using the values in CTUR/CTLR upon receipt of the Address-Trigger “START COUNTER”command (See Table 1). The C/T then runs continuously. A subsequent “START COUNTER”command causes the C/T to terminate the current timing cycle and begin a new timing cycle using the current values stored in CTUR and CTLR. The COUNTER READY status bit, in the Interrupt Status Register (ISR[3]), is set once each cycle of the square wave. This allows the use of the C/T as a periodic interrupt generator, if the condition is programmed to generate an interrupt via the interrupt mask register (IMR). The ISR[3] can be cleared by issuing the address-triggered “STOP COUNTER” command (See Table 1). In the TIMER mode, however, the command does not actually stop the C/T. D.3.2 COUNTER MODE In the Counter Mode, the C/T counts down the number of pulses written into CTUR/CTLR, beginning at the receipt of a “START COUNTER” command. The COUNTER/READY status bit (ISR[3]) is set upon reaching the count of 000016. The C/T will continue to count past the 000016 and underflow (with the next count being FFFF16) until it is stopped by the CPU via a “STOP COUNTER”command. If OP3 is programmed to be the output of the C/T, the output will remain high until the terminal count is reached, at which time the output goes low. It then returns to the high state and ISR[3] is cleared when the C/T is stopped (via the “STOP COUNTER” command). A “START COUNTER”command while the counter is running restarts the counter with the values in CTUR/CTLR. The CPU may change the contents of CTUR or CTLR at any time but the new count takes effect only on after the subsequent START COUNTER command. If new values are not programmed the previous values are preserved and used for the next cycle. D.4 External Inputs The DUART allows for some of the Input Port pins (IP2 - IP5) to be used as direct external inputs to the Timing Control Block as timing sources for the Transmitters and Receivers of both channels. Please note that the user can specify whether a clock signal, applied to one of these external inputs, is a 1X or a 16X clock signal; via the Clock Select Registers (see Section D.5). For a more detailed discussion on the Input Port pins and their function, please see Section E. D.5 Clock Select Registers, CSRA and CSRB In Figure 24, the Clock Select Registers are the 32:1 MUX’s. The Clock Select Registers are the means that the user can select which clock signals will drive the Transmitters and Receivers of both channels. The CSRs allow the user to select the 23 different standard bit rates from the BRG, the Counter/Timer output, or to use an external input as the timing source for the Transmitters

driving the Transmitters and Receivers. Table 17. Bit Format of the Clock Select Registers, CSRA and CSRB Note: the b suffix denotes a binary expression. x = don’t care value. Table 18. Bit Format of the Clock Select Registers, CSR[3:0] and CSR[7:4] appropriate data to the channel’s Command Register. Although this information can be found in Table 3.

Table 19. Command Register Controls Over the Extend Bit

3.6864 MHz

provided that fo is between 2.0 MHz and 4.0 MHz. Additionally, as in the case for standard baud rates, the actual frequency of the clock signal will be 16 times these values. over-samples the received serial data by a factor of 16. following paragraphs will clarify the reasons. remote transmitter (TX), and a local receiver (RX). Figure 29. Example of a Serial Data

been detected, this oversampling procedure is repeated.

1 Bit Period

Figure 32. The Typical Sampling Pattern of Each Receiver Within the XR88C681 Device.

Rev. 2.11 The oversampling technique mitigates many of the serial data bit errors by attempting to adjust the receiver sampling point, to near the midpoint of the bit periods, on a character to character basis. This approach is successful for two reasons: 1. It offers periodic correction to the Receiver sampling point. 2. It limits the Receiver drift phenomenon (between sampling point adjustments) to typically at most 12 bits (8 bit character + parity and STOP bits). Therefore, if the user selects to receive data at a baud rate of 9600 baud; upon detection of the START bit, the Receiver will begin sampling the data at (9600 x 16) = 153,600Hz. However, once the Receiver has oversampled up to the 7th 153.6kHz clock pulse, it will mark this location as the midpoint of the START bit. From this point on, the 153.6kHz clock signal is divided by 16 to generate the sample clock (9600Hz) for the remaining data and overhead bits of the character. The XR88C681 devices gives the user the option to declare an external input clock signal as either a 1X or 16X clock signal. Whenever the user is given a choice to use either the 1X or 16X clock signal (per the Clock Select Registers), the user is advised to always use the 16X clock, in order to mitigate the effects of receiver drift. The user is further advised never to use the 1X clock features of the DUART, unless the incoming serial data stream is synchronous with the Receiver (1X) clock. D.6 Application Examples using the Timing Control Block In order to clarify the roles of the assets within the Timing Control Block, three examples are included. Example A: Using the BRG Suppose that the user wishes to receive and transmit data at a rate of 115.2kbps via Channel A. The user must do the following: 1. Use a 3.6864 MHz crystal oscillator across the X1/CLK and X2 pins; or driving a 3.6864 MHz TTL signal into the X1/CLK pin (with the X2 pin floating). 2. Write 0A16 to Command Register A. This step will set the Transmitter BRG Select Extend bit (X = 1). 3. Write 0816 to Command Register A. This step will set the Receiver BRG Select Extend bit (X = 1). 4. Write 1xxxxxxxb to ACR This step selects “Bit Rate” Set #2 per Table 18 of this data sheet. Where the b suffix denotes a binary expression, and x denotes a “don’t care”value for the binary expression. 5. Write 8816 to CSRA. This step sets the Receive and Transmit bit rate for Channel A to 115.2kbps (per Table 17 and Table 18). Example B: Programming the Bit Rate via the Counter/Timer Suppose the user wishes to transmit and receive data at 62.5kbps via Channel B. Please note that this particular bit rate is not offered by the BRG. In this case the user can do the following. 1. Drive a 4 MHz TTL signal into the X1/CLK pin, while the X2 pin is left floating. 2. Write 0016 to CTUR and 0216 to CTLR. This steps results in the C/T generating a square wave of frequency = 4 MHz/2.[2] = 1 MHz. 3. Write 110b to ACR[6:4] This will set the C/T into the Timer mode, and select the Timing source for the C/T to be the X1/CLK input. 4. Write DD16 to CSRB. This will specify that the timing source for the Receiver and Transmitter of Channel B will be derived from the C/T. Please note that when the DUART is programmed in this configuration, the C/T output represents a 16X over sample of the Transmitted and Received data. Therefore, the chip circuitry will divide the 1 MHz square wave by 16, just like for clock signals originating from the BRG. Thus: Bit Rate = 1 MHz/16 = 62.5kbps. Example C: Using the External Input Ports Suppose that, in addition to running Channel B at 62.5kbps (see Example B), he/she wants to Transmit and Receive data at 1 Mbps via Channel A. The user needs to perform all of the steps presented in Example B, along with the following: 1. Write xxxx01xxb to the OPCR (Output Port Configuration Register). This step allows the 1 MHz square wave from the C/T to be output on OP3. Note: x = don’t care The b suffix denotes a binary expression

1. Externally connect the OP3 pin to the IP3 and IP4 pins.

MHz (1X) clock signal; in order to minimize bit errors. confusion by numerous users. Table 20. Clock Timing (Figure 13) Now, here is an explanation for each of these parameters. pin must reside at the high and low states. can only apply between 2.0 and 4.0 MHz at this input. Counter/Timer, can reside at the high and low states. pin, and still be properly handled by the Counter/Timer.

Rev. 2.11 This spec is not related to the parameter tRTX, which also specifies limits on signals applied to IP2 or other input pins, for use at the External Clock Source for Transmitter and Receivers. D tRTX - RXC and TXC (External) High or Low Time - via IP2, IP3, IP4 and IP5 This spec places a lower limit on the amount of time that a signal, being applied at the General Purpose Input Pins, IP2 - IP5, for use as the Transmitter and Receiver Clock source, can reside at the high or low state. This spec has no relationship to tCTC, even though it is also applies to Input pin IP2. D fRTX - RXC and TXC (External) Frequency - via IP2, IP3, IP4, and IP5 This spec places limits on both the 1X and 16X external signals that are to be used to clock the Transmitters and Receivers. If the user wishes to use a 1X clock, he/she can only apply a signal with frequencies up to 1.0 MHz. This input will results in a bit rate of 1 Mbps (see Example C). If the user wishes to use a 16X clock, he/she can only apply a signal with frequencies up to 2.0 MHz. Since this signal is a 16X signal, this will result in a bit rate of 125kbps. In summary, the DUART Timing Control block gives the user the ability to generate virtually any baud rate that he or she desires. The Timing Control Block gives the user access to the following resources: D 23 different standard bit rates via the BRG. D The Counter/Timer, which can be configured to gen- erate bit rates which are not available from the BRG. D Inputs to the Timing Control Block (via some Input Port pins) which allows the use of external clock sig- nals to generate a custom bit rate. E. INPUT PORT The Input Port can be used as a general purpose input or the DUART can be programmed to use some of these inputs for special functions. The current state of the inputs to this unlatched port can be read by the CPU by reading the IP register (for the states of IP0 - IP5). A high input signal at the IPn pin results in a logic “1”in the IPR[n] bit position, within the IP register. Likewise, a “low”input signal at the IPn pin results in a logic “0”in the IPR[n] bit position, within the IP register. E.1 Alternate Functions for the Input Port Table 17 describes the alternate uses for the input pins, such as clock inputs and data flow control signals and includes a brief summary as how to program the alternate function. A read of the IP registers will show the logic state at the pin, regardless of its programmed function.

IP0 -CTSA: Clear to Send (CTS) input for Channel A. IP1 -CTSB: Clear to Send (CTS) input for Channel B. discussion on this function, please see Section G.3. IP2 CT_EX: Counter/Timer External Clock Input. Table 21. Listing of Alternate Function for the Input Port generate an interrupt via the “Input Port Change of State”interrupt. Table 22. Input Port Configuration Register - IPCR

In order to enable the “Input Port Change of State”interrupt, one must do the following. note that the applicable bits, within the ACR register, are shaded. Table 23. ACR- Auxiliary Control Register enable or disable this interrupt. D The input pin(s) that toggled. D The final state of the changing input pin. Clock input for Receiver Channel B). Register (OPR), and the output port pins themselves. state of the Output Port pins. Output Port pin, following a POR is logic “1”.

“Address Triggered”commands. state of the corresponding Output Port pin is unchanged. command is illustrated in Figure 33. Figure 33. Illustration of the “SET OUTPUT PORT BIT” Command and its Effect on the Output Port Register and the State of the Output Port Pins.

turn the state of the Output Port pin is unchanged. command is illustrated in Figure 34. Figure 34. Illustration of the “CLEAR OUTPUT PORT BIT” Command and its Effect on the Output Port Register and the State of the Output Port Pins. the state of the Output Port pin, OPn. Output Port pin to a logic “1”.

functions. Table 24 lists the Alternate Functions of each of the Output Port pins. OP2 TXCA_16X Output: Channel A 16X Transmitter Clock Output. TXCA_1X Output: Channel A 1X Transmitter Clock Output. RXCA_1X Output: Channel A 1X Receiver Clock Output. OP3 TXCB_1X Output: Channel B 1X Transmitter Clock Output. RXCB_1X Output: Channel B 1X Receiver Clock Output. Open-Drain output when used as the Counter/Timer Ready Output. This is an Open-Drain output for the RXRDY/FFULL_A function. This is an Open-Drain output for the RXRDY/FFULL_B function. output for the TXRDY_A function. output for the TXRDY_B function. Table 24. Listing of the Alternate Functions for the Output Port Many of the Alternate Functions of the various Output Port pins are selected by writing the appropriatedata to the OPCR. be General Purpose Output Ports. Table 25. Output Port Configuration Register - OPCR

functions available to this version of the XR88C681. mode used for multi-drop applications. definition of some of these symbols follows. required by the asynchronous protocol. serialized and is transmitted out of the chip via the TXDn pin. Figure 35. A Simplified Drawing Depicting the Transmit Shift Register and the Transmit Holding Register.

protocol (8 bits per character, No-parity, 1-Stop Bit). Figure 36. The Output Waveform of the Transmitter While Sending computing and checking parity, if parity is being used. the RXDn pin, where it is processed through the RSR. simplified drawing of the Receiver.

Figure 37. A Simplified Drawing of the Receiver Shift Register inactive and is not receiving or processing any data.

1. To verify that the detected “low”level in the RXDn input
2. To establish the phase relationship between the 1x bit

sampling clock, and the incoming serial data stream.

phenomenon obviously results in a loss of data. detected several things happen.

1. The “Received Break” condition is flagged in the

Status Register (SRn[7] = 1).

1. The “Break” character is loaded into the RHR.
2. The corresponding “Delta Break” interrupt is

the Interrupt Status Register. or FFULL condition via the Channel Mode Registers. IMR[5] for Channels A and B, respectively. MR1, the MR pointer will automatically point to MR2. Table 26. Mode Registers - MR1A, MR1B

Table 27. Mode Registers - MR2A, MR2B Channel A and ISR[5] for Channel B. particular channel will operate in the “Block”Error Mode. receiver performs a parity check on received characters. Multi-Drop mode it selects the state of the A/D flag bit. START, PARITY, and STOP bits.

Each Channel can operate in one of four modes. ing conditions apply while in this mode. Figure 38. A Block Diagram Depicting Normal Mode Operation.

duration can be programmed from 1-1/16 to 2 bit times. nibble of the Status Register. Table 28. Status Register - SRA, SRB edges of the internal or external 1x clock. STATUS”command has been invoked. condition one bit-time following the last data or parity bit. “high”flagging the occurrence of a Frame Error (FE).

Rev. 2.11 this bit is set for a given character, it will be cleared if the STOP bit is properly detected in the next character. If the “Error”Mode has been set to “Block”mode, then this bit, once set will remain asserted until the “RESET ERROR STATUS”command has been invoked (please see Table 3). Please note that if the Error Mode is “Block” this bit, in the Status Register will remain set, for all subsequent characters, independent of the condition of these received characters, until the “RESET ERROR STATUS”command has been invoked. SRn[5] Parity Error This bit is set when the “WITH PARITY” or “FORCE PARITY” modes are programmed and if the corresponding character in the data FIFO was received with incorrect parity. If the Error Mode has been set to “Character”Mode, this bit only applies to the Character at the top of the RHR. If this bit is set for a given character, it will be cleared if the received parity is correct in the next character. If the “Error”Mode has been set to “Block”mode, then this bit, once set will remain asserted until the “RESET ERROR STATUS”command has been invoked (please see Table 3). Please note that if the Error Mode is “Block” this bit, in the Status Register will remain set, for all subsequent characters, independent of the condition of these received characters, until the “RESET ERROR STATUS”command has been invoked. SRn[4] Overrun Error If set, this bit indicates that one or more characters in the received data have been lost, it is set upon receipt of a new character when the FIFO is full and a character is already in the RSR waiting for an empty FIFO position. When this occurs, the character in the RSR is overwritten. Please note that unlike the Status Register bits for FE (Framing Error), PE (Parity Error) and RB (Received Break), the OE (Overrun Error) indicator is always flagged on a “Block”Error Mode basis. The OE condition is never flagged on a character-to-character basis, and only cleared when the “RESET ERROR STATUS”command is invoked. SRn[3] Transmitter Empty (TXEMT) This bit is set when the transmitter underruns. It is set after transmission of the last stop bit of a character and if there is no character in the THR or TSR awaiting transmission. This bit is cleared when the transmitter is disabled, or when the CPU writes a new character to the THR. SRn[2] Transmitter Ready (TXRDY) This bit, when set, indicates that the THR is empty and ready to accept a character from the CPU. The bit is cleared when the CPU writes a new character to the THR, and is set when that character is transferred to the TSR. TXRDY is set when the transmitter is initially enabled and is reset when the transmitter is disabled. Characters loaded into the THR while the transmitter is disabled will not be transmitted. SRn[1] FIFO Full (FFULL) This bit is set when a character is transferred from the RSR to the RHR and the transfer causes it to become full, i.e., all three FIFO positions are occupied. It is reset when the CPU reads the RHR. If a character is waiting in the RSR because the FIFO is full, FFULL will not be reset when the CPU reads the RHR. SRn[0] Receiver Ready (RXRDY) This bit indicates that at least one character has been received and is waiting in the FIFO to be read by the CPU. It is set when a character is transferred from the RSR to the RHR and is cleared with the CPU reads the last character currently stored in the FIFO. Please note that some of the conditions that are flagged by the Status Register can also be programmed to generate an Interrupt Request to the CPU. However, there are some conditions that are flagged by the Status Register that cannot be programmed to generate an Interrupt. These conditions are listed here: D SRn[6] - Framing Error D SRn[5] - Parity Error D SRn[4] - Overrun Error Therefore, if system level error-checking is not employed, the user is recommended to validate each character by checking the Status Register.

negate the RTS output (to the Transmitting device). operation of the Receiver-Controlled RTS configuration. Figure 42. Block Diagram and Timing Sequence of Two DUARTs Connected

Figure 43. A Flow Diagram Depicting an Algorithm That Could be Used to Apply mode allows the Transmitter to negatye the RTS signal, one bit period after emptying the THR and TSR.

Figure 44. Block Diagram and Timing Sequence of Two DUARTs Connected in the Transmitter-RTS Controlled Configuration.

Receiver Controlled RTS Function. Data transmission is now permitted. Data transmission is disabled. Figure 45. A Flow Diagram depicting an Algorithm that could be used to Realize the Multi-Drop mode is discussed in Section H.2.1. station is possible, as depicted in Figure 46.

Figure 46. An Illustration Depicting the Concept of Multi-Drop Mode

8 Bit Character

Figure 47. Bit Format of Character Data Being Transmitted in the Multi-Drop Mode Address Byte and a “0”in a Data Byte.

and will continue to ignore the data bytes that follows. is transmitted by the “Master Device”. identifies it as an address. Figure 48. A Flow Diargam Depicting a Procedure That Can Be Used to

character will be discarded if its A/D bit is “0”(Data flag). preparation for the subsequent blocks of data. SRn[5] in order to verify that it is a “0”(Data characters). SRn[5] =“1”, it should compare this address with its own. Figure 49. A Flow Diagram Depicting a Procedure That Can Be Used to Receive Characters in the Multi-Drop Mode.

package do not have the following features. by the CPU. Register addressing is shown in . certain changes may result in improper operation. assignments for each register. Table 29. Mode Registers 1: MR1A, MR1B

Table 30. Mode Register 2: MR2A, MR2B Table 31. Clock Select Registers: CSRA, CSRB Table 32. Command Registers: CRA, CRB Table 33. Status Registers: SRA, SRB Table 34. Output Port Configuration Register: OPCR

Table 35. Auxiliary Control Register: ACR Table 36. Input Port Configuration Register , IPCR Table 37. Interrupt Status Register, ISR Table 38. Interrupt Mask Register, IMR Table 39. Counter/Timer Upper Byte Register, CTUR Table 40. Counter/Timer Lower Byte Register, CTLR Table 41. Interrupt Vector Register: IVR

Figure 52. XR88C681 Read and Write Cycle Timing

Figure 53. XR88C681 Z Mode Interrupt Cycle Timing

Figure 56. Clock Timing

1 Bit Time

Figure 57. Transmitter Timing Figure 58. Receiver Timing

Rev. 2.11

44 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC) Rev. 1.00 D A D D1 A 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ. 12.70 typ. e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS B e Seating Plane 2 44 Note: The control dimension is the inch column 45° x H2 45° x H1 C R

Rev. 2.11 D B e

40 LEAD CERAMIC DUAL-IN-LINE

(600 MIL CDIP) Rev. 1.00 1 20 a c L Seating Plane Base Plane A A 0.100 0.225 2.54 5.72 A1 0.015 0.075 0.38 1.91 B 0.014 0.026 0.36 0.66 B1 0.045 0.065 1.14 1.65 c 0.008 0.018 0.20 0.46 D 1.990 2.090 50.55 53.09 E1 0.550 0.610 13.97 15.49 E 0.600 BSC 15.24 BSC e 0.100 BSC 2.54 BSC L 0.125 0.200 3.18 5.08 a 0° 15° 0° 15° SYMBOL MIN MAX MIN MAX INCHES MILLIMETERS E Note: The control dimension is the inch column

Rev. 2.11

28 LEAD PLASTIC DUAL-IN-LINE

(600 MIL PDIP) Rev. 1.00 SYMBOL MIN MAX MIN MAX INCHES A 0.160 0.250 4.06 6.35 A1 0.015 0.070 0.38 1.78 A2 0.125 0.195 3.18 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.380 1.565 35.05 39.75 E 0.600 0.625 15.24 15.88 E1 0.485 0.580 12.32 14.73 e 0.100 BSC 2.54 BSC eA 0.600 BSC 15.24 BSC eB 0.600 0.700 15.24 17.78 L 0.115 0.200 2.92 5.08 a 0° 15° 0° 15° MILLIMETERS D E A L B Seating Plane a e C Note: The control dimension is the inch column eB eA

Rev. 2.11 D e

40 LEAD PLASTIC DUAL-IN-LINE

(600 MIL PDIP) Rev. 1.00 SYMBOL MIN MAX MIN MAX A 0.160 0.250 4.06 6.35 A1 0.015 0.070 0.38 1.78 A2 0.125 0.195 3.18 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.980 2.095 50.29 53.21 E 0.600 0.625 15.24 15.88 E1 0.485 0.580 12.32 14.73 e 0.100 BSC 2.54 BSC eA 0.600 BSC 15.24 BSC eB 0.600 0.700 15.24 17.78 L 0.115 0.200 2.92 5.08 a 0° 15° 0° 15° INCHES MILLIMETERS E A L Seating Plane a B C Note: The control dimension is the inch column eB eA

Rev. 2.11 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im- prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de- scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum- stances. Copyright 2006 EXAR Corporation Datasheet June 2006 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Revision History

From Rev 2.10 to 2.11 (June 2006) Corrected pinout on 28--pin PDIP package on page 3 (pin 1 is A0). Added Revision History.