MSPM0G3507-Q1 TI | Alldatasheet
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MSPM0G350x Automotive Mixed-Signal Microcontrollers With CAN-FD Interface
1 Features
- Qualified for automotive applications
- Core – Arm® 32-bit Cortex®-M0+ CPU with memory protection unit, frequency up to 80 MHz
- Operating characteristics – Extended temperature: –40°C up to 125°C – Wide supply voltage range: 1.62 V to 3.6 V
- Memories – Up to 128KB of flash memory with error correction code (ECC) – Up to 32KB of SRAM with hardware parity
- High-performance analog peripherals – Two simultaneous sampling 12-bit 4-Msps analog-to-digital converters (ADCs) with up to 17 external channels
- 14-bit effective resolution at 250-ksps with hardware averaging – One 12-bit 1-MSPS digital-to-analog converter with integrated output buffer (DAC) – Two zero-drift zero-crossover chopper op-amps (OPA)
- 0.5-µV/°C drift with chopping
- Integrated programmable gain stage, up to 32x – One general-purpose amplifier (GPAMP) – Three high-speed comparators (COMP) with 8- bit reference DACs
- 32-ns propagation delay in high-speed mode
- Support low-power mode operation down to 0.7 µA – Programmable analog connections between ADC, OPAs, COMP and DAC – Configurable 1.4-V or 2.5-V internal shared voltage reference (VREF) – Integrated temperature sensor – Integrated supply monitor
- Optimized low-power modes – RUN: 96 µA/MHz (CoreMark) – SLEEP: 467 µA at 4 MHz – STOP: 46 µA at 32 kHz – STANDBY: 1.5 µA with RTC and SRAM retention – SHUTDOWN: 80 nA with IO wake-up capability
- Intelligent digital peripherals – 7-channel DMA controller – Math accelerator supports DIV, SQRT, MAC and TRIG computations – Seven timers supports up to 22 PWM channels
- One 16-bit general-purpose timer
- One 16-bit general-purpose timer supports QEI
- Two 16-bit general-purpose timers support low-power operation in STANDBY mode
- One 32-bit high-resolution general-purpose timer
- Two 16-bit advanced timers with deadband support up to 12 PWM channels – Two window-watchdog timers – RTC with alarm and calendar mode
- Enhanced communication interfaces – Four UART interfaces; one supports LIN, IrDA, DALI, Smart Card, Manchester, and three support low-power operation in STANDBY mode – Two I2C interfaces support up to FM+ (1 Mbit/s), SMBus/PMBus, and wakeup from STOP mode – Two SPIs, one SPI supports up to 32 Mbits/s – One Controller Area Network (CAN) interface supports CAN 2.0 A or B and CAN-FD
- Clock system – Internal 4- to 32-MHz oscillator with up to ±1.2% accuracy (SYSOSC) – Phase-locked loop (PLL) up to 80 MHz – Internal 32-kHz low-frequency oscillator (LFOSC) with ±3% accuracy – External 4- to 48-MHz crystal oscillator (HFXT) – External 32-kHz crystal oscillator(LFXT) – External clock input
- Data integrity and encryption – Cyclic redundancy checker (CRC-16, CRC-32) – True random number generator (TRNG) – AES encryption with 128 or 256-bit key
- Flexible I/O features – Up to 60 GPIOs
- Two 5-V tolerant IOs
- Two high-drive IOs with 20-mA drive strength
- Development support – 2-pin serial wire debug (SWD)
- Package options – 64-pin LQFP – 48-pin LQFP, VQFN – 32-pin VQFN – 28-pin VSSOP – 24-pin VQFN
- Family members (also see Device Comparison) – MSPM0G3505: 32KB flash, 16KB RAM – MSPM0G3506: 64KB flash, 32KB RAM ADVANCE INFORMATION MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
– MSPM0G3507: 128KB flash, 32KB RAM
- Development kits and software (also see Tools and Software) – LP-MSPM0G3507 LaunchPad™ development kit – MSP Software Development Kit (SDK)
- Automotive qualification – AEC-Q100 Grade 1 (-40°C to 125°C) – 24 , 32 and 48 -pin QFN with wettable flanks option
2 Applications
- Automotive body electronics and Lighting
- Automotive Gateway
- Steering Wheel Systems
- Automotive Motor Control
- DC to AC Inverters
- Automotive Interior Lighting
- Door handle modules
- Kick to open modules
- Vehicle Occupancy Detection
- Seat Comfort Module
3 Description
MSPM0G350x microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU family based on the enhanced Arm® Cortex®-M0+ 32-bit core platform operating at up to 80-MHz frequency. These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V. The MSPM0G350x devices provide up to 128KB embedded flash program memory with built-in error correction code (ECC) and up to 32KB SRAM with hardware parity option. These MCUs also incorporate a memory protection unit, 7-channel DMA, math accelerator, and a variety of high-performance analog peripherals such as two 12-bit 4-Msps ADCs, configurable internal shared voltage reference, one 12-bit 1-Msps DAC, three high speed comparators with built-in reference DACs, two zero-drift zero-crossover op-amps with programmable gain, and one general-purpose amplifier. These devices also offer intelligent digital peripherals such as two 16-bit advanced control timers, five general-purpose timers (with one 16-bit general-purpose timer for QEI interface, two 16-bit general-purpose timers for STANDBY mode, and one 32-bit general-purpose timer), two windowed-watchdog timers, and one RTC with alarm and calendar modes. These devices provide data integrity and encryption peripherals (AES, CRC, TRNG) and enhanced communication interfaces (four UART, two I2C, two SPI, CAN 2.0/FD). The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers find the MCU that meets their project's needs. The MSPM0 MCU platform combines the Arm Cortex-M0+ platform with a holistic ultra-low-power system architecture, allowing system designers to increase performance while reducing energy consumption. MSPM0G350x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get the design started quickly. Development kits include a LaunchPad available for purchase. TI also provides a free MSP Software Development Kit (SDK), which is available as a component of Code Composer Studio ™ IDE desktop and cloud version within the TI Resource Explorer . MSPM0 MCUs are also supported by extensive online collateral, training with MSP Academy , and online support through the TI E2E™ support forums. For complete module descriptions, see the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. CAUTION System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level ESD Considerations for more information. The principles in this application note are applicable to MSPM0 MCUs. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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4 Functional Block Diagram
Figure 4-1 shows the MSPM0G350x functional block diagram. SPI0 SPI1 CPU SUB SYSTEM Arm Cortex-M0+ fmax = 80 MHz NVIC MPU SWD + MTB IOPORT AHB BUS (MCLK) FLASH Up to 128KB SRAM Up to 32KB ROM BCR, BSL CPU-ONLY PD1 PERIPHERAL BUS (MCLK) DMA 7-ch PD1 PERIPHERAL BUS (MCLK) AES CRC TRNG UART3 GPIO tIOBUSt PD0 PERIPHERAL BUS (ULPCLK) 12b ADC0 12b ADC1 TIMG0 TIMG8 UART0 I2C0 I2C1 IOMUX PMCU (SYSCTL) GPAMP FLASHCTL ULPCLK ULPCLK PD1, CPU ACCESS ONLY PD1, CPU/DMA ACCESS PD1/PD0, CPU/DMA ACCESS PD0, CPU/DMA ACCESS LEGEND EVENTRTC WWDT0 WWDT1 CAN-FD TIMA0 TIMA1 TIMG6 TIMG7 TIMG12 32-bit UART1 UART2 VREF PD0 PERIPHERAL BUS (ULPCLK) OPA0 OPA1 COMP0 COMP1 COMP2 TEMP SENSOR SYSOSC SYSPLL LFXT HFXT LFOSC CKM LDO PMU BOR POR VBOOST 12b DAC0 DEBUG RTC_OUT TX, RX, CTS, RTS TX, RX, CTS, RTS SDA, SCL 2-CH IN+, IN-, OUT DAC_OUT IN+, IN-, OUT IN+, IN-, OUT VREF+, VREF- A0_x A1_x 2-CH 2-CH 2-CH 2-CH FAULT 4-CH FAULT POCI, PICO, SCK, CSx TX, RX, CTS, RTS TX, RX PAx, PBx LFXIN, LFXOUT HFXIN, HFXOUT ROSC CLK_OUT, FCC_IN VDD, VSS VCORE, NRST Each COMPx includes an 8b reference DAC; COMP0 and COMP1 reference DACs connect to OPA0 and OPA1, respectively 2-CH QEI/HALL MATHACL SWCLK, SWDIO Figure 4-1. MSPM0G350x Functional Block Diagram www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
11 Mechanical, Packaging, and Orderable
MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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5 Device Comparison
The following table summarizes the features of each device that is described in this data sheet. Table 5-1. Device Comparison DEVICE NAME (1) (4) FLASH /SRAM (KB) QUAL(2) MATH ACCEL ADC / CHAN COMP DAC OPA GPAMP UART/I2C/SPI CAN TIMA TIMG GPIO PACKAGE [PACKAGE SIZE] (3) MSPM0G3505xPM 32 / 16 Q Y 2 / 17 3 1 2 1 4 / 2 / 2 1 2 5 60 64 LQFP [12 mm × 12 mm]MSPM0G3506xPM 64 / 32 MSPM0G3507xPM 128 / 32 MSPM0G3505xPT 32 / 16 Q Y 2 / 16 3 1 2 1 4 / 2 / 2 1 2 5 44 48 LQFP [9 mm × 9 mm]MSPM0G3506xPT 64 / 32 MSPM0G3507xPT 128 / 32 MSPM0G3505xRGZ 32 / 16 Q Y 2 / 16 3 1 2 1 4 / 2 / 2 1 2 5 44 48 VQFN 7 mm × 7 mmMSPM0G3506xRGZ 64 / 32 MSPM0G3507xRGZ 128 / 32 MSPM0G3505xRHB 32 / 16 Q Y 2 / 11 3 1 2 1 4 / 2 / 2 1 2 5 28 32 VQFN [5 mm × 5 mm] (5)MSPM0G3506xRHB 64 / 32 MSPM0G3507xRHB 128 / 32 MSPM0G3505xRGE 32 / 16 Q Y 2 / 9 3 1 2 1 4 / 2 / 2 1 2 5 20 24 VQFN 4 mm × 4 mmMSPM0G3506xRGE 64 / 32 MSPM0G3507xRGE 128 / 32 MSPM0G3505xDGS28 32 / 16 Q Y 2 / 11 3 1 2 1 4 / 2 / 2 1 2 5 24 28 VSSOP [7.1 mm × 3 mm]MSPM0G3506xDGS28 64 / 32 MSPM0G3507xDGS28 128 / 32 (1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 11, or see the TI website. (2) Device Qualifications:
- Q = –40°C to 125°C , AEC-Q100 qualified (3) The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section 11. (4) For more information about the device name, see Section 10.2 (5) 24, 32 and 48-pin VQFN packages are available with wettable flanks www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
6 Pin Configuration and Functions
The System Configuration tool provides a graphical interface to enable, configurable, and generate initialization code for pin multiplexing and simplifying pin settings. The following pin diagrams show the primary peripheral functions, some of the integrated device features, and available clock signals to simplify the device pinout. For full descriptions of the pin functions, see the Pin Attributes and Signal Descriptions sections.
6.1 Pin Diagrams
High-Speed I/O (HSIO) 5-V Tolerant Open-Drain I/O (ODIO) High-Drive I/O (HDIO) Figure 6-1. Pin Diagram Color Coding LQFP64 PB12 PB11 / CLK_OUT PB10 PB9 PB8 PB7 PB6 PA11 PA10 / CLK_OUT PA9 / RTC_OUT / CLK_OUT PA8 PB5 PB4 PB3 PB2 PA7 / CLK_OUT PB1 PB0 PA6 / HFCLK_IN / HFXOUT PA5 / HFXIN / FCC_IN PA4 / LFCLK_IN / LFXOUT PA3 / LFXIN PA2 / ROSC VSS VDD PA31 / CLK_OUT NRST PA30 PA29 PA28 PA1 PA0 / FCC_IN PB13 PB14 PB15 PB16 PA12 / FCC_IN PA13 PA14 / CLK_OUT / A0_12 PA15 / A1_0 PA16 /A1_1 /FCC_IN PA17 / A1_2 PA18 / A1_3 PA19 / SWDIO PA20 / SWCLK PB17 / A1_4 PB18 / A1_5 PB19 / A1_6 PA21 / A1_7 / VREF- PA22 / CLK_OUT / A0_7 PB20 / A0_6 PB21 PB22 PB23 PB24 / A0_5 PA23 VREF+ PA24 / A0_3 PA25 / A0_2 PB25 / A0_4 PB26 PB27 PA26 / A0_1 PA27/ A0_0 VCORE Figure 6-2. 64-Pin PM (LQFP) (Top View) MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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PB17 / A1_4 PA20 / SWCLK PA19 / SWDIO PA18 / A1_3 PA17 / A1_2 PA16 / A1_1 /FCC_IN PA15 / A1_0 PA14 / CLK_OUT /A0_12 PA13 PA12 / FCC_IN PB16 PB15 VCORE PA27 / RTC_OUT / A0_0 PA26 / A0_1 PA25 / A0_2 / OPA0_IN1+ PA24 / A0_3 PB24 / A0_5 PB20 / A0_6 PA22 / CLK_OUT / A0_7 PA21 / A1_7 / VREF- PB19 / A1_6 PB18 / A1_5 PA23 / VREF+ PA0 / FCC_IN PA1 PA28 NRST PA31 / CLK_OUT VDD VSS PA2 / ROSC PA3 / COMP1_OUT / LFXIN PA4 / LFCLK_IN / LFXOUT PA5 / HFXIN / FCC_IN PA6 / HFCLK_IN / HFXOUT PA7 / CLK_OUT PB2 PB3 PA8 PA9 / RTC_OUT / CLK_OUT PA10 / CLK_OUT PA11 PB6 PB7 PB8 PB9 PB14 Figure 6-3. 48-Pin PT (LQFP) (Top View) www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
PA27 / RTC_OUT / A0_0 PA26 / A0_1 PA25 / A0_2 PA24 / A0_3 PB24 / A0_5 PB20 / A0_6 PA22 / CLK_OUT / A0_7 PA21 / A1_7 / VREF- PB19 / A1_6 PB18 / A1_5 PA0 / FCC_IN PA1 PA28 NRST PA31 / CLK_OUT VDD VSS PA2 / ROSC PA3 / LFXIN PA4 / LFCLK_IN / LFXOUT PA5 / HFXIN / FCC_IN PA6 / HFCLK_IN / HFXOUT PA7 / CLK_OUT PB2 PB3 PA8 PA9 / RTC_OUT / CLK_OUT PA10 / CLK_OUT PA11 PB6 PB7 PB8 PB9 PB14 PB17 / A1_4 PA20 / SWCLK PA19 / SWDIO PA18 / A1_3 PA17 / A1_2 PA16 / A1_1 /FCC_IN PA15 / A1_0 PA14 / CLK_OUT / A0_12 PA13 PA12 / FCC_IN PB16 PB15 VQFN48 Thermal pad PA23 / VREF+ Figure 6-4. 48-Pin RGZ (VQFN) (Top View) MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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PA0 / FCC_IN PA1 PA2 / ROSC PA3 / LFXIN PA4 / LFCLK_IN / LFXOUT PA9 / RTC_OUT / CLK_OUT PA10 / CLK_OUT PA11 PA20 / SWCLK PA19 / SWDIO PA18 / A1_3 PA17 / A1_2 PA16 / A1_1 / FCC_IN PA15 / A1_0 PA26 / A0_1 PA25 / A0_2 PA24 /A0_3 PA22 / CLK_OUT / A0_7 PA21 / A1_7 / VREF- PA23 / VREF+ Figure 6-7. 24-Pin RGE (VQFN) (Top View) Note For the full pin configuration and description of the functions for each package option, see Pin Attributes and Signal Descriptions. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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6.2 Pin Attributes
The following table describes the functions available on every pin for each device package. Note Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that lets users configure the desired Pin Function using the PINCM.PF control bits. Table 6-1. Pin Attributes PINCMx PIN NAME SIGNAL NAMES PIN NUMBER IO STRUCTU REANALOG DIGITAL [PIN FUNCTION] (1)
64 LQFP
48 LQFP, VQFN
32 VQFN
28 VSSOP
24 VQFN
N/A VCORE 32 48 32 3 23 Power N/A NRST 38 4 3 6 2 Reset
1 PA0
UART0_TX [2] / I2C0_SDA [3] / TIMA0_C0 [4] / TIMA_FAL1 [5] / TIMG8_C1 [6] / FCC_IN [7]/(Default BSL I2C_SDA) 33 1 1 4 24 5V Tol. Open- Drain
2 PA1
UART0_RX [2] / I2C0_SCL [3] / TIMA0_C1 [4] / TIMA_FAL2 [5] / TIMG8_IDX [6] / TIMG8_C0 [7]/ (Default BSL I2C_SCL) 34 2 2 5 1 5V Tol. Open- Drain
7 PA2 ROSC TIMG8_C1 [2] / SPI0_CS0 [3] / TIMG7_C1 [4] /
SPI1_CS0 [5] 42 8 6 9 5 Standard
8 PA3 LFXIN
TIMG8_C0 [2] / SPI0_CS1 [3] / UART2_CTS [4] / TIMA0_C2 [5] / COMP1_OUT [6] / TIMG7_C0 [7] / TIMA0_C1 [8] / I2C1_SDA [9] 43 9 7 10 6 Standard
9 PA4 LFXOUT
TIMG8_C1 [2] / SPI0_POCI [3] / UART2_RTS [4] / TIMA0_C3 [5] / LFCLK_IN [6] / TIMG7_C1 [7] / TIMA0_C1N [8] / I2C1_SCL [9] 44 10 8 11 7 Standard
10 PA5 HFXIN TIMG8_C0 [2] / SPI0_PICO [3] / TIMA_FAL1 [4] /
TIMG0_C0 [5] / TIMG6_C0 [6] / FCC_IN [7] 45 11 9 12 - Standard
11 PA6 HFXOUT
TIMG8_C1 [2] / SPI0_SCK [3] / TIMA_FAL0 [4] / TIMG0_C1 [5] / HFCLK_IN [6] / TIMG6_C1 [ 7] / TIMA0_C2N [8] 46 12 10 13 - Standard
14 PA7
COMP0_OUT [2] / CLK_OUT [3] / TIMG8_C0 [4] / TIMA0_C2 [5] / TIMG8_IDX [6] / TIMG7_C1 [7] / TIMA0_C1 [8] 49 13 11 – - Standard
19 PA8 UART1_TX [2] / SPI0_CS0 [3] / UART0_RTS [4] /
TIMA0_C0 [5] / TIMA1_C0N [6] 54 16 12 – - Standard
20 PA9
UART1_RX [2] / SPI0_PICO [3] / UART0_CTS [4] / TIMA0_C1 [5] / RTC_OUT [6] / TIMA0_C0N [7] / TIMA1_C1N [8] / CLK_OUT [9] 55 17 13 14 8 High- Speed
21 PA10
UART0_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] / TIMA1_C0 [5] / TIMG12_C0 [6] / TIMA0_C2 [7] / I2C1_SDA [8] / CLK_OUT [9]/(Default BSL UART_TX) 56 18 14 15 9 High-Drive
22 PA11
UART0_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] / TIMA1_C1 [5] / COMP0_OUT [6]/ TIMA0_C2N [7] / I2C1_SCL [8]/(Default BSL UART_RX) 57 19 15 16 10 High-Drive
34 PA12 UART3_CTS [2] / SPI0_SCK [3] / TIMG0_C0 [4] /
CAN_TX [5] / TIMA0_C3 [6] / FCC_IN [7] 5 27 16 – - High- Speed
35 PA13 COMP0_IN2- UART3_RTS [2] / SPI0_POCI [3] / UART3_RX [4] /
TIMG0_C1 [5] / CAN_RX [6] / TIMA0_C3N [7] 6 28 17 – - High- Speed www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 6-1. Pin Attributes (continued) PINCMx PIN NAME SIGNAL NAMES PIN NUMBER IO STRUCTU REANALOG DIGITAL [PIN FUNCTION] (1)
36 PA14 COMP0_IN2+ / A0_12 UART0_CTS [2] / SPI0_PICO [3] / UART3_TX [4] /
TIMG12_C0 [5] / CLK_OUT [6] 7 29 18 17 - High- Speed
37 PA15
A1_0 / DAC_OUT / OPA0_IN2+ / OPA1_IN2+/ COMP0_IN3+ / COMP1_IN3+ UART0_RTS [2] / SPI1_CS2 [3] / I2C1_SCL [4] / TIMA1_C0 [5] / TIMG8_IDX [6] / TIMA1_C0N [7] / TIMA0_C2 [8] 8 30 19 18 11 Standard
38 PA16 A1_1 / OPA1_OUT
COMP2_OUT [2] / SPI1_POCI [3] / I2C1_SDA [4] / TIMA1_C1 [5] / TIMA1_C1N [6] / TIMA0_C2N [7] / FCC_IN [8] 9 31 20 19 12 Standard
39 PA17 A1_2 / OPA1_IN1- /
COMP0_IN1- UART1_TX [2] / SPI1_SCK [3] / I2C1_SCL [4] / TIMA0_C3 [5] / TIMG7_C0 [6] / TIMA1_C0 [7] 10 32 21 20 13 Standard with wake(2)
40 PA18
A1_3 / OPA1_IN1+ / COMP0_IN1+ / GPAMP_IN- UART1_RX [2] / SPI1_PICO [3] / I2C1_SDA [4] / TIMA0_C3N [5] / TIMG7_C1 [6] / TIMA1_C1 [7]/Default BSL_Invoke 11 33 22 21 14 Standard with wake(2)
41 PA19 SWDIO [2] 12 34 23 22 15 High-
42 PA20 SWCLK [2] 13 35 24 23 16 Standard
46 PA21 A1_7 / COMP2_IN1- /
UART2_TX [2] / TIMG8_C0 [3] / UART1_CTS [4] / TIMA0_C0 [5] / TIMG6_C0 [6] 17 39 25 24 17 Standard
47 PA22 A0_7 / GPAMP_OUT /
OPA0_OUT UART2_RX [2] / TIMG8_C1 [3] / UART1_RTS [4] / TIMA0_C1 [5] / CLK_OUT [6] / TIMA0_C0N [7] / TIMG6_C1 [8] 18 40 26 25 18 Standard
53 PA23 COMP1_IN1- / VREF+
UART2_TX [2] / SPI0_CS3 [3] / TIMA0_C3 [4] / TIMG0_C0 [5] / UART3_CTS [6] / TIMG7_C0 [7]/ TIMG8_C0 [8] 24 43 27 26 19 Standard
54 PA24 A0_3 / OPA0_IN1-
UART2_RX [2] / SPI0_CS2 [3] / TIMA0_C3N [4] / TIMG0_C1 [5] / UART3_RTS [6] / TIMG7_C1 [7] / TIMA1_C1 [8] 25 44 28 27 20 Standard
55 PA25 A0_2 / OPA0_IN1+ UART3_RX [2] / SPI1_CS3 [3] / TIMG12_C1 [4] /
TIMA0_C3 [5] / TIMA0_C1N [6] 26 45 29 28 21 Standard
59 PA26
A0_1 / COMP0_IN0+ / OPA0_IN0+ / GPAMP_IN+ UART3_TX [2] / SPI1_CS0 [3] / TIMG8_C0 [4] / TIMA_FAL0 [5] / CAN_TX [6] / TIMG7_C0 [7] 30 46 30 1 1 Standard
60 PA27 A0_0 / COMP0_IN0- /
OPA0_IN0- RTC_OUT [2] / SPI1_CS1 [3] / TIMG8_C1 [4] / TIMA_FAL2 [5] / CAN_RX [6] / TIMG7_C1 [7] 31 47 31 2 - Standard
3 PA28 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C3 [4] /
TIMA_FAL0 [5] / TIMG7_C0 [6] / TIMA1_C0 [ 7] 35 3 – – - High-Drive
4 PA29 I2C1_SCL [2] / UART2_RTS [3] / TIMG8_C0 [4] /
TIMG6_C0 [5] 36 – – – - Standard
5 PA30 I2C1_SDA [2] / UART2_CTS [3] / TIMG8_C1 [4] /
TIMG6_C1 [5] 37 – – – - Standard
6 PA31
UART0_RX [2] / I2C0_SCL [3] / TIMA0_C3N [4] / TIMG12_C1 [5] / CLK_OUT [6]/ TIMG7_C1 [7] / TIMA1_C1 [8] 39 5 – – - High-Drive
12 PB0 UART0_TX [2] / SPI1_CS2 [3] / TIMA1_C0 [4] /
TIMA0_C2 [5] 47 – – – - Standard
13 PB1 UART0_RX [2] / SPI1_CS3 [3] / TIMA1_C1 [4] /
TIMA0_C2N [5] 48 – – – - Standard MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 6-1. Pin Attributes (continued) PINCMx PIN NAME SIGNAL NAMES PIN NUMBER IO STRUCTU REANALOG DIGITAL [PIN FUNCTION] (1)
15 PB2
UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] / TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] / TIMA1_C0 [8] 50 14 – – - Standard
16 PB3
UART3_RX [2] / UART2_RTS [3] / I2C1_SDA [4] / TIMA0_C3N[5] / UART1_RTS [6] / TIMG6_C1 [7] / TIMA1_C1 [8] 51 15 – – - Standard
17 PB4 UART1_TX [2] / UART3_CTS [3] / TIMA1_C0 [4] /
TIMA0_C2 [5] / TIMA1_C0N [6] 52 – – – - Standard
18 PB5 UART1_RX [2] / UART3_RTS [3] / TIMA1_C1 [4] /
TIMA0_C2N [5] / TIMA1_C1N [6] 53 – – – - Standard
23 PB6
UART1_TX [2] / SPI1_CS0 [3] / SPI0_CS1 [4] / TIMG8_C0 [5] / UART2_CTS [6] / TIMG6_C0 [7] / TIMA1_C0N [8] 58 20 – – - Standard
24 PB7
UART1_RX [2] / SPI1_POCI [3] / SPI0_CS2 [4] / TIMG8_C1 [5] / UART2_RTS [6] / TIMG6_C1 [7] / TIMA1_C1N [8] 59 21 – – - Standard
25 PB8 UART1_CTS [2] / SPI1_PICO [3] / TIMA0_C0 [4] /
COMP1_OUT [5] 60 22 – – - Standard
26 PB9 UART1_RTS [2] / SPI1_SCK [3] / TIMA0_C1 [4] /
TIMA0_C0N [5] 61 23 – – - Standard
27 PB10 TIMG0_C0 [2] / TIMG8_C0 [3] / COMP1_OUT [4] /
TIMG6_C0 [5] 62 – – – - Standard
28 PB11 TIMG0_C1 [2] / TIMG8_C1 [3] / CLK_OUT [4] /
TIMG6_C1 [5] 63 – – – - Standard
29 PB12 UART3_TX [2] / TIMA0_C2 [3] / TIMA_FAL1 [4] /
TIMA0_C1 [5] 64 – – – - Standard
30 PB13 UART3_RX [2] / TIMA0_C3 [3] / TIMG12_C0 [4] /
TIMA0_C1N [5] 1 – – – - Standard
31 PB14 SPI1_CS3 [2] / SPI1_POCI [3] / SPI0_CS3 [4] /
TIMG12_C1 [5] / TIMG8_IDX [6] / TIMA0_C0 [7] 2 24 – – - Standard
32 PB15 UART2_TX [2] / SPI1_PICO [3] / UART3_CTS [4] /
TIMG8_C0 [5] / TIMG7_C0 [6] 3 25 – – - Standard
33 PB16 UART2_RX [2] / SPI1_SCK [3] / UART3_RTS [4] /
TIMG8_C1 [5] / TIMG7_C1 [6] 4 26 – – - Standard
43 PB17 A1_4 / COMP1_IN2- UART2_TX [2] / SPI0_PICO [3] / SPI1_CS1 [4] /
TIMA1_C0 [5] / TIMA0_C2 [6] 14 36 – – - Standard
44 PB18 A1_5 / COMP1_IN2+ UART2_RX [2] / SPI0_SCK [3] / SPI1_CS2 [4] /
TIMA1_C1 [5] / TIMA0_C2N [6] 15 37 – – - Standard
45 PB19 A1_6 / COMP2_IN1+ /
OPA1_IN0+ COMP2_OUT [2] / SPI0_POCI [3] / TIMG8_C1 [4] / UART0_CTS [5] / TIMG7_C1 [6] 16 38 – – - Standard
48 PB20 A0_6 / OPA1_IN0-
SPI0_CS2 [2] / SPI1_CS0 [3] / TIMA0_C2 [4] / TIMG12_C0 [5] / TIMA_FAL1 [6] / TIMA0_C1 [7] / TIMA1_C1N [8] 19 41 – – - Standard
49 PB21 COMP2_IN0+ SPI1_POCI [2] / TIMG8_C0 [3] 20 – – – - Standard
50 PB22 COMP2_IN0- SPI1_PICO [2] / TIMG8_C1 [3] 21 – – – - Standard
51 PB23 SPI1_SCK [2] / COMP0_OUT [3] / TIMA_FAL0 [4] 22 – – – - Standard
52 PB24 A0_5 / COMP1_IN1+ SPI0_CS3 [2] / SPI0_CS1 [3] / TIMA0_C3 [4] /
TIMG12_C1 [5] / TIMA0_C1N [6] / TIMA1_C0N [7] 23 42 – – - Standard www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 6-1. Pin Attributes (continued) PINCMx PIN NAME SIGNAL NAMES PIN NUMBER IO STRUCTU REANALOG DIGITAL [PIN FUNCTION] (1)
56 PB25 A0_4 UART0_CTS [2] / SPI0_CS0 [3] / TIMA_FAL2 [4] 27 – – – - Standard
57 PB26 COMP1_IN0+ UART0_RTS [2] / SPI0_CS1 [3] / TIMA0_C3 [4] /
TIMG6_C0 [5] / [6] 28 – – – 22 Standard
58 PB27 COMP1_IN0- COMP2_OUT [2] / SPI1_CS1 [3] / TIMA0_C3N [4] /
TIMG6_C1 [5] / TIMA1_C1 [6] 29 – – – - Standard (1) Set PINCM.PF and PINCM.PC in IOMUX to 0 for analog functions (for example, OPA inputs or outputs, and COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. (2) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for details. Table 6-2. Digital IO Features by IO Type IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC Standard drive Y Y Y Standard drive with wake(2) Y Y Y Y High drive Y Y Y Y Y High speed Y Y Y Y 5-V tolerant open drain Y Y Y Y
6.3 Signal Descriptions
Table 6-3. Signal Descriptions FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION
64 PM 48 PT,
A0_0 31 47 31 2 – I ADC0 analog input 0 A0_1 30 46 30 1 22 I ADC0 analog input 1 A0_2 26 45 29 28 21 I ADC0 analog input 2 A0_3 25 44 28 27 20 I ADC0 analog input 3 A0_4 27 – – – – I ADC0 analog input 4 A0_5 23 42 – – – I ADC0 analog input 5 A0_6 19 41 – – – I ADC0 analog input 6 A0_7 18 40 26 25 18 I ADC0 analog input 7 A0_12 7 29 18 17 – I ADC0 analog input 12 A1_0 8 30 19 18 11 I ADC1 analog input 0 A1_1 9 31 20 19 12 I ADC1 analog input 1 A1_2 10 32 21 20 13 I ADC1 analog input 2 A1_3 11 33 22 21 14 I ADC1 analog input 3 A1_4 14 36 – – – I ADC1 analog input 4 A1_5 15 37 – – – I ADC1 analog input 5 A1_6 16 38 – – – I ADC1 analog input 6 A1_7 17 39 25 24 17 I ADC1 analog input 7 MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION BSL BSL_invoke 11 33 22 21 14 I Input pin used to invoke bootloader BSL (I2C) BSLSCL 34 2 2 5 1 I/O Default I2C BSL clock BSLSDA 33 1 1 4 24 I/O Default I2C BSL data BSL (UART) BSLRX 57 19 15 16 10 I Default UART BSL receive BSLTX 56 18 14 15 9 O Default UART BSL transmit CAN CAN_TX 5 30 1 22 O CAN-FD transmit data CAN_RX 6 31 2 – I CAN-FD receive data Clock CLK_OUT O Configurable clock output HFCLK_IN 46 12 10 13 – I Digital high-frequency clock input HFXIN 45 11 9 12 – I Input for high-frequency crystal oscillator HFXT HFXOUT 46 12 10 13 – O Output for high-frequency crystal oscillator HFXT LFCLK_IN 44 10 8 11 7 I Digital low-frequency clock input LFXIN 43 9 7 10 – I Input for low-frequency crystal oscillator LFXT LFXOUT 44 10 8 11 7 O Output of low-frequency crystal oscillator LFXT ROSC 42 8 6 9 5 I External resistor used for improving oscillator accuracy www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION COMP0_IN0- 31 47 31 2 – I Comparator 0 inverting input 0 COMP0_IN0+ 30 46 30 1 22 I Comparator 0 noninverting input 0 COMP0_IN1- 10 32 21 20 13 I Comparator 0 inverting input 1 COMP0_IN1+ 11 33 22 21 14 I Comparator 0 noninverting input 1 COMP0_IN2- 6 28 17 – – I Comparator 0 inverting input 2 COMP0_IN2+ 7 29 18 17 – I Comparator 0 noninverting input 2 COMP0_IN3+ 8 30 19 18 11 I Comparator 0 noninverting input 3 COMP0_OUT 15 16 10 O Comparator 0 output COMP1_IN0- 29 – – – – I Comparator 1 inverting input 0 COMP1_IN0+ 28 – – – – I Comparator 1 noninverting input 0 COMP1_IN1- 24 43 27 26 19 I Comparator 1 inverting input 1 COMP1_IN1+ 23 42 – – – I Comparator 1 noninverting input 1 COMP1_IN2- 14 36 – – – I Comparator 1 inverting input 2 COMP1_IN2+ 15 37 – – – I Comparator 1 noninverting input 2 COMP1_IN3+ 8 30 19 18 11 I Comparator 1 noninverting input 3 COMP1_OUT 22 7 10 6 O Comparator 1 output COMP2_IN0- 21 – – – – I Comparator 2 inverting input 0 COMP2_IN0+ 20 – – – – I Comparator 2 noninverting input 0 COMP2_IN1- 17 39 25 24 17 I Comparator 2 inverting input 1 COMP2_IN1+ 16 38 – – – I Comparator 2 noninverting input 1 COMP2_OUT 38 20 19 12 O Comparator 2 output DAC DAC_OUT 8 30 19 18 11 O DAC output Debug SWCLK 13 35 24 23 16 I Serial wire debug input clock SWDIO 12 34 23 22 15 I/O Serial wire debug data input/output FCC FCC_IN
14 I Frequency clock counter input
GPAMP_IN+ 30 46 30 1 22 I GPAMP noninverting terminal input GPAMP_IN- 11 33 22 21 14 I GPAMP inverting terminal input GPAMP_OUT 18 40 26 25 18 O GPAMP output MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION PA0 33 1 1 4 24 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1 34 2 2 5 1 I/O General-purpose digital I/O with wake up from SHUTDOWN PA2 42 8 6 9 5 I/O General-purpose digital I/O PA3 43 9 7 10 6 I/O General-purpose digital I/O PA4 44 10 8 11 7 I/O General-purpose digital I/O PA5 45 11 9 12 – I/O General-purpose digital I/O PA6 46 12 10 13 – I/O General-purpose digital I/O PA7 49 13 11 – – I/O General-purpose digital I/O PA8 54 16 12 – – I/O General-purpose digital I/O PA9 55 17 13 14 8 I/O General-purpose digital I/O PA10 56 18 14 15 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA11 57 19 15 16 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA12 5 27 16 – – I/O General-purpose digital I/O PA13 6 28 17 – – I/O General-purpose digital I/O PA14 7 29 18 17 – I/O General-purpose digital I/O PA15 8 30 19 18 11 I/O General-purpose digital I/O PA16 9 31 20 19 12 I/O General-purpose digital I/O PA17 10 32 21 20 13 I/O General-purpose digital I/O with wake up from SHUTDOWN PA18 11 33 22 21 14 I/O General-purpose digital I/O with wake up from SHUTDOWN PA19 12 34 23 22 15 I/O General-purpose digital I/O PA20 13 35 24 23 16 I/O General-purpose digital I/O PA21 17 39 25 24 17 I/O General-purpose digital I/O PA22 18 40 26 25 18 I/O General-purpose digital I/O PA23 24 43 27 26 19 I/O General-purpose digital I/O PA24 25 44 28 27 20 I/O General-purpose digital I/O PA25 26 45 29 28 21 I/O General-purpose digital I/O PA26 30 46 30 1 22 I/O General-purpose digital I/O PA27 31 47 31 2 – I/O General-purpose digital I/O PA28 35 3 – – – I/O General-purpose digital I/O with wake up from SHUTDOWN PA29 36 – – – – I/O General-purpose digital I/O PA30 37 – – – – I/O General-purpose digital I/O PA31 39 5 – – – I/O General-purpose digital I/O with wake up from SHUTDOWN www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION PB0 47 – – – – I/O General-purpose digital I/O PB1 48 – – – – I/O General-purpose digital I/O PB2 50 14 – – – I/O General-purpose digital I/O PB3 51 15 – – – I/O General-purpose digital I/O PB4 52 – – – – I/O General-purpose digital I/O PB5 53 – – – – I/O General-purpose digital I/O PB6 58 20 – – – I/O General-purpose digital I/O PB7 59 21 – – – I/O General-purpose digital I/O PB8 60 22 – – – I/O General-purpose digital I/O PB9 61 23 – – – I/O General-purpose digital I/O PB10 62 – – – – I/O General-purpose digital I/O PB11 63 – – – – I/O General-purpose digital I/O PB12 64 – – – – I/O General-purpose digital I/O PB13 1 – – – – I/O General-purpose digital I/O PB14 2 24 – – – I/O General-purpose digital I/O PB15 3 25 – – – I/O General-purpose digital I/O PB16 4 26 – – – I/O General-purpose digital I/O PB17 14 36 – – – I/O General-purpose digital I/O PB18 15 37 – – – I/O General-purpose digital I/O PB19 16 38 – – – I/O General-purpose digital I/O PB20 19 41 – – – I/O General-purpose digital I/O PB21 20 – – – – I/O General-purpose digital I/O PB22 21 – – – – I/O General-purpose digital I/O PB23 22 – – – – I/O General-purpose digital I/O PB24 23 42 – – – I/O General-purpose digital I/O PB25 27 – – – – I/O General-purpose digital I/O PB26 28 – – – – I/O General-purpose digital I/O PB27 29 – – – – I/O General-purpose digital I/O I2C I2C0_SCL
10 I/O I2C0 serial clock
I2C0_SDA
24 I/O I2C0 serial data
I2C1_SCL I/O I2C1 serial clock I2C1_SDA I/O I2C1 serial data MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION (Zero-Drift Op-Amp) OPA0_IN0+ 30 46 30 1 22 I OPA0 noninverting terminal input 0 OPA0_IN1+ 26 45 29 28 21 I OPA0 noninverting terminal input 1 OPA0_IN2+ 8 30 19 18 11 I OPA0 noninverting terminal input 2 OPA0_IN0- 31 47 31 2 – I OPA0 inverting terminal input 0 OPA0_IN1- 25 44 28 27 20 I OPA0 inverting terminal input 1 OPA0_OUT 18 40 26 25 18 O OPA0 output OPA1_IN0+ 16 38 – – I OPA1 noninverting terminal input 0 OPA1_IN1+ 11 33 22 21 14 I OPA1 noninverting terminal input 1 OPA1_IN2+ 8 30 19 18 11 I OPA1 noninverting terminal input 2 OPA1_IN0- 19 41 – – I OPA1 inverting terminal input 0 OPA1_IN1- 10 32 21 20 13 I OPA1 inverting terminal input 1 OPA1_OUT 9 31 20 19 12 O OPA1 output Power VSS 41 7 5 8 6 P Ground supply VDD 40 6 4 7 5 P Power supply VCORE 32 48 32 3 3 P Regulated core power supply output QFN Pad – Pad Pad – Pad P QFN package exposed thermal pad. TI recommends connection to VSS. RTC RTC_OUT 31
10 O RTC clock output
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Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION SPI0_CS0 12 9 7 I/O SPI0 chip-select 0 SPI0_CS1 7 10 – I/O SPI0 chip-select 1 SPI0_CS2 28 27 20 I/O SPI0 chip-select 2 SPI0_CS3 27 26 19 I/O SPI0 chip-select 3 SPI0_SCK I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 15 11 I/O SPI0 controller in/peripheral out SPI0_PICO
10 I/O SPI0 controller out/peripheral in
SPI1_CS0
7 I/O SPI1 chip-select 0
SPI1_CS1 47 31 2 2 I/O SPI1 chip-select 1 SPI1_CS2 37 19 18 – I/O SPI1 chip-select 2 SPI1_CS3 45 29 28 – I/O SPI1 chip-select 3 SPI1_SCK 21 20 14 I/O SPI1 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI1_POCI 20 19 – I/O SPI1 controller in/peripheral out SPI1_PICO 22 21 15 I/O SPI1 controller out/peripheral in System NRST 38 4 3 6 4 I Reset input active low MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION TIMG0_C0 I/O General purpose timer 0 CCR0 capture input/ compare output TIMG0_C1
20 I/O General purpose timer 0 CCR1 capture input/
TIMG6_C0 24 8 I/O General purpose timer 6 CCR0 capture input/ compare output TIMG6_C1
18 I/O General purpose timer 6 CCR1 capture input/
TIMG7_C0
19 I/O General purpose timer 7 CCR1 capture input/
TIMG7_C1 I/O General purpose timer 7 CCR1 capture input/ compare output TIMG8_C0 I/O General purpose timer 8 CCR0 capture input/ compare output www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION (continued) TIMG8_C1 I/O General purpose timer 8 CCR1 capture input/ compare output TIMG8_IDX 18 – I General purpose timer 8 quadrature encoder index pulse input TIMG12_C0 17 11 I/O 32-bit general purpose timer 0 CCR0 capture input/ compare output TIMG12_C1 29 28 – I/O 32-bit general purpose timer 0 CCR1 capture input/ compare output TIMA0_C0 24 – I/O Advanced control timer 0 CCR0 capture input/ compare output TIMA0_C0N
18 I/O Advanced control timer 0 CCR0 compare output
(inverting) TIMA0_C1
18 I/O Advanced control timer 0 CCR1 capture input/
TIMA0_C1N
10 I/O Advanced control timer 0 CCR1 compare output
(inverting) MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION (continued) TIMA0_C2
11 I/O Advanced control timer 0 CCR2 capture input/
TIMA0_C2N
10 I/O Advanced control timer 0 CCR2 compare output
(inverting) TIMA0_C3 I/O Advanced control timer 0 CCR3 capture input/ compare output TIMA0_C3N
20 I/O Advanced control timer 0 CCR3 compare output
(inverting) TIMA1_C0
14 I/O Advanced control timer 1 CCR0 capture input/
TIMA1_C0N 19 18 – I/O Advanced control timer 0 CCR3 compare output (inverting) TIMA1_C1 I/O Advanced control timer 1 CCR1 capture input/ compare output TIMA1_C1N 19 10 I/O Advanced control timer 1 CCR1 compare output (inverting) www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION (continued) TIMA_FAL0
9 I Advanced control timer 0 fault handling input
TIMA_FAL1 12 8 I Advanced control timer 1 fault handling input TIMA_FAL2 5 2 I Advanced control timer 2 fault handling input UART UART0_TX 15 11 O UART0 transmit data UART0_RX 16 12 I UART0 receive data UART0_CTS 17 10 I UART0 "clear to send" flow control input UART0_RTS 19 18 – O UART0 "request to send" flow control output UART1_TX 21 20 14 O UART1 transmit data UART1_RX
15 I UART1 receive data
UART1_CTS 25 24 – I UART1 "clear to send" flow control input UART1_RTS 26 25 18 O UART1 "request to send" flow control output UART2_TX 26 19 O UART2 transmit data UART2_RX
20 I UART2 receive data
UART2_CTS 7 10 – I UART2 "clear to send" flow control input UART2_RTS 8 11 – O UART2 "request to send" flow control output MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 6-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION UART3_TX 17 1 O UART3 transmit data UART3_RX 29 28 – I UART3 receive data UART3_CTS 27 26 13
19 I UART3 "clear to send" flow control input
UART3_RTS 28 27 20 O UART3 "request to send" flow control output Voltage Reference (3) VREF+ 24 43 27 26 19 I/O Voltage reference (VREF) power supply - external reference input / internal reference output VREF- 17 39 25 24 – I/O Voltage reference (VREF) ground supply - external reference input / internal reference output (1) – = not available (2) I = input, O = output, I/O = input or output, P = power (3) When using VREF+/- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
6.4 Connections for Unused Pins
Table 6-4 lists the correct termination of unused pins. Table 6-4. Connection of Unused Pins PIN (1) POTENTIAL COMMENT PAx and PBx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with the internal pullup or pulldown resistor enabled. NRST VCC NRST is an active-low reset signal. Pull the pin high to VCC, or the device cannot start. For more information, see Section 9.1. (1) Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx and PBx" unused pin connection guidelines. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Supply voltage At VDD pin –0.3 4.1 V VI Input voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V VI Input voltage Applied to any common tolerance pins –0.3 VDD + 0.3 (4.1 MAX) V IVDD Current into VDD pin (source) -40℃ ≤ Tj ≤ 130℃ 80 mA Current into VDD pin (source) -40℃ ≤ Tj ≤ 85℃ 100 mA IVSS Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 130℃ 80 mA Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 85℃ 100 mA IIO Current of SDIO pin Current sunk or sourced by SDIO pin 6 mA Current of HS_IO pin Current sunk or sourced by HSIO pin 6 mA Current of HDIO pin Current sunk or sourced by HDIO pin 20 mA Current of ODIO pin Current sunk by ODIO pin 20 mA ID Supported diode current Diode current at any device pin ±2 mA TJ Junction temperature Junction temperature -40 130 °C Tstg Storage temperature Storage temperature –40 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002(1) ±2000 V Charged device model (CDM), per AEC- Q100-011 , All pins ±500 V Charged device model (CDM), per AEC- Q100-011 , Corner pins ±750 V (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 1.62 3.6 V VCORE Voltage on VCORE pin (2) 1.35 V CVDD Capacitor connected between VDD and VSS (1) 10 µF CVCORE Capacitor connected between VCORE and VSS (1) (2) 470 nF TA Ambient temperature, Q version –40 125 °C TJ Max junction temperature, Q version 130 °C www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT fMCLK (PD1 bus clock) MCLK, CPUCLK frequency with 2 flash wait states (3) 80 MHzMCLK, CPUCLK frequency with 1 flash wait state (3) 48 MCLK, CPUCLK frequency with 0 flash wait states (3) 24 fULPCLK (PD0 bus clock) ULPCLK frequency 40 MHz (1) Connect CVDD and CVCORE between VDD/VSS and VCORE/VSS, respectively, as close to the device pins as possible. A low-ESR capacitor with at least the specified value and tolerance of ±20% or better is required for CVDD and CVCORE. (2) The VCORE pin must only be connected to CVCORE. Do not supply any voltage or apply any external load to the VCORE pin. (3) Wait states are managed automatically by the system controller (SYSCTL) and do not need to be configured by application software unless MCLK is sourced from a high speed clock source (HSCLK sourced from HFCLK or SYSPLL).
7.4 Thermal Information
THERMAL METRIC(1) PACKAGE VALUE UNIT RθJA Junction-to-ambient thermal resistance LQFP-64 (PM) 63.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 23.8 °C/W RθJB Junction-to-board thermal resistance 35.3 °C/W ΨJT Junction-to-top characterization parameter 2.2 °C/W ΨJB Junction-to-board characterization parameter 35 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-48 (RGZ) 30.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 20.7 °C/W RθJB Junction-to-board thermal resistance 12.5 °C/W ΨJT Junction-to-top characterization parameter 0.3 °C/W ΨJB Junction-to-board characterization parameter 12.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4.2 °C/W RθJA Junction-to-ambient thermal resistance LQFP-48 (PT) 69.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27.4 °C/W RθJB Junction-to-board thermal resistance 32.6 °C/W ΨJT Junction-to-top characterization parameter 2.6 °C/W ΨJB Junction-to-board characterization parameter 32.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-32 (RHB) 32.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 23.6 °C/W RθJB Junction-to-board thermal resistance 13.0 °C/W ΨJT Junction-to-top characterization parameter 0.3 °C/W ΨJB Junction-to-board characterization parameter 13.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 3.3 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-28 (DGS28) 78.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.6 °C/W RθJB Junction-to-board thermal resistance 41.3 °C/W ΨJT Junction-to-top characterization parameter 3.4 °C/W ΨJB Junction-to-board characterization parameter 41.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.4 Thermal Information (continued)
THERMAL METRIC(1) PACKAGE VALUE UNIT RθJA Junction-to-ambient thermal resistance VQFN-24 (RGE) 44.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJB Junction-to-board thermal resistance 21.9 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 21.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.5 Supply Current Characteristics
7.5.1 RUN/SLEEP Modes
-40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX RUN Mode IDDRUN MCLK=SYSPLL, SYSPLLREF=SYSOSC, CoreMark, execute from flash mA MCLK=SYSOSC, CoreMark, execute from flash MCLK=SYSPLL, SYSPLLREF=SYSOSC, CoreMark, execute from SRAM MCLK=SYSOSC, CoreMark, execute from SRAM IDDRUN, per MHz MCLK=SYSPLL, SYSPLLREF=SYSOSC, CoreMark, execute from flash 80MHz 94 96 99 100 107 µA/MHz MCLK=SYSPLL, SYSPLLREF=SYSOSC, While(1), execute from flash 80MHz 52 55 53 57 55 61 57 68 64 74 SLEEP Mode IDDSLEEP MCLK=SYSPLL, SYSPLLREF=SYSOSC, CPU is halted 80MHz 2974 3154 3039 3211 3262 3350 3350 3389 3439 4900 µA 48MHz 2025 2174 2075 2330 2262 2437 2337 2998 2778 4000 MCLK=SYSOSC, CPU is halted 32MHz 1355 1460 1399 1506 1567 1750 1675 2320 2094 3000 4MHz 440 513 467 620 662 898 737 1400 1140 2834
7.5.2 STOP/STANDBY Modes
-40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 331 355 338 360 343 362 346 364 357 380 µAIDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 174 196 179 198 185 203 188 206 198 219 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 44 54 46 56 51 61 53 64 62 83 STANDBY Mode IDDSTBY0 LFCLK=LFXT, STOPCLKSTBY=0, RTC enabled 32kHz 2 5 2 5 4 10 7 18 16 42 µA IDDSTBY1 LFCLK=LFOSC, STOPCLKSTBY=1, RTC enabled 1.4 3 1.5 4 3 10 6 17 13 40 LFCLK=LFXT, STOPCLKSTBY=1, RTC enabled 1.4 3 1.5 4 4 10 6 17 13 40 LFCLK=LFXT, STOPCLKSTBY=1, GPIOA enabled 1.4 3 1.5 4 4 10 6 17 13 40 MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.5.3 SHUTDOWN Mode
All inputs tied to 0V or VDD. Outputs do not source or sink any current. Core regulator is powered down. PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX IDDSHDN Supply current in SHUTDOWN mode 3.3V 40 80 730 1730 4800 nA
7.6 Power Supply Sequencing
7.6.1 POR and BOR
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us Falling (2) 0.01 Falling, STANDBY 0.1 V/ms VPOR+ Power-on reset voltage level Rising (1) 1.04 1.30 1.5 V VPOR- Falling (1) 0.99 1.25 1.48 V VHYS, POR POR hysteresis 30 58 74 mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising (1) 1.48 1.54 1.61 VVBOR0+ Rising (1) (2) 1.56 1.58 1.62 VBOR0- Falling (1) (2) 1.55 1.57 1.61 VBOR0, STBY STANDBY mode (1) 1.54 1.56 1.60 VBOR1+ Brown-out-reset voltage level 1 Rising (1) (2) 2.15 2.17 2.23 VVBOR1- Falling (1) (2) 2.12 2.14 2.19 VBOR1, STBY STANDBY mode (1) 2.06 2.13 2.20 VBOR2+ Brown-out-reset voltage level 2 Rising (1) (2) 2.74 2.77 2.83 VVBOR2- Falling (1) (2) 2.71 2.73 2.80 VBOR2, STBY STANDBY mode (1) 2.68 2.71 2.82 VBOR3+ Brown-out-reset voltage level 3 Rising (1) (2) 2.88 2.96 3.04 VVBOR3- Falling (1) (2) 2.85 2.93 3.01 VBOR3, STBY STANDBY mode (1) 2.80 2.92 3.02 VHYS,BOR Brown-out reset hysteresis Level 0 (1) 14 18 mV Levels 1-3 (1) 34 38 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 5 us STANDBY mode 100 us (1) |dVDD/dt| ≤ 3V/s (2) Device operating in RUN, SLEEP, or STOP mode.
7.6.2 Power Supply Ramp
Figure 7-1 shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
POR BOR Running Running BOR POR BOR Running Supply Voltage (VDD) POR- POR+ BOR0- BOR0+ No reset asserted BOR asserted POR asserted BOR releasedPOR released POR released BOR released Time (t)POR/BOR levels are met for specified |dVDD/dt| BOR released Figure 7-1. Power Cycle POR and BOR Conditions
7.7 Flash Memory Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply VDDPGM/ERASE Program and erase supply voltage 1.62 3.6 V IDDERASE Supply current from VDD during erase operation Supply current delta 10 mA IDDPGM Supply current from VDD during program operation Supply current delta 10 mA Endurance NWEC(LOWER) Erase/program cycle endurance (lower 32kB flash) (1) 100 k cycles NWEC(UPPER) Erase/program cycle endurance (remaining flash) (1) 10 k cycles NE(MAX) Total erase operations before failure (2) 802 k erase operations NW(MAX) Write operations per word line before sector erase (3) 83 write operations Retention tRET_85 Flash memory data retention -40°C <= Tj <= 85°C 60 years tRET_105 Flash memory data retention -40°C <= Tj <= 105°C 11.4 years Program and Erase Timing tPROG (WORD, 64) Program time for flash word (4) (6) 50 275 µs tPROG (SEC, 64) Program time for 1kB sector (5) (6) 6.4 ms tERASE (SEC) Sector erase time ≤2k erase/program cycles, Tj≥25°C 4 20 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles, Tj≥25°C 20 150 ms tERASE (SEC) Sector erase time <10k erase/program cycles 20 200 ms tERASE (BANK) Bank erase time <10k erase/program cycles 22 220 ms (1) The lower 32kB flash address space supports higher erase/program endurance to enable EEPROM emulation applications. On devices with <=32kB flash memory, the entire flash memory supports NWEC(LOWER) erase/program cycles. (2) Total number of cumulative erase operations supported by the flash before failure. A sector erase or bank erase operation is considered to be one erase operation. (3) Maximum number of write operations allowed per word line before the word line must be erased. If additional writes to the same word line are required, a sector erase is required once the maximum number of write operations per word line is reached. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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(4) Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller. (5) Sector program time is defined as the time from when the first word program command is triggered until the final word program command completes and the interrupt flag is set in the flash controller. This time includes the time needed for software to load each flash word (after the first flash word) into the flash controller during programming of the sector. (6) Flash word size is 64 data bits (8 bytes). On devices with ECC, the total flash word size is 72 bits (64 data bits plus 8 ECC bits).
7.8 Timing Characteristics
VDD=3.3V, Ta=25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Wakeup Timing tWAKE, SLEEP1 Wakeup time from SLEEP1 to RUN (1) 1.5 us tWAKE, SLEEP2 Wakeup time from SLEEP2 to RUN (1) 2.1 us tWAKE, STANDBY0 Wakeup time from STANDBY0 to RUN (1) 15.2 us tWAKE, STANDBY1 Wakeup time from STANDBY1 to RUN (1) 15.2 us tWAKE, STOP0 Wakeup time from STOP0 to RUN (SYSOSC enabled) (1) 12.1 us tWAKE, STOP1 Wakeup time from STOP1 to RUN (SYSOSC enabled) (1) 13.5 us tWAKE, STOP2 Wakeup time from STOP2 to RUN (SYSOSC disabled) (1) 12.9 tWAKEUP, SHDN Wakeup time from SHUTDOWN to RUN (2) Fast boot enabled 240 us Fast boot disabled 252 Asynchronous Fast Clock Request Timing tDELAY, SLEEP1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP1 0.33 us tDELAY, SLEEP2 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.93 us tDELAY, STANDBY0 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STANDBY0 3.2 us tDELAY, STANDBY1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STANDBY1 3.2 us tDELAY, STOP0 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP0 0.1 us tDELAY, STOP1 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP1 2.4 us tDELAY, STOP2 Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is STOP2 0.9 us Startup Timing tSTART, RESET Device cold startup time from reset/ power-up (3) Fast boot enabled 260 us Fast boot disabled 308 NRST Timing tRST, BOOTRST Pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 1.5 us ULPCLK=32kHz 80 tRST, POR Pulse length on NRST pin to generate POR 1 s (1) The wake-up time is measured from the edge of an external wake-up signal (GPIO wake-up event) to the time that the first instruction of the user program is executed, with glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1) . (2) The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
(3) The start-up time is measured from the time that VDD crosses VBOR0- (cold start-up) to the time that the first instruction of the user program is executed.
7.9 Clock Specifications
7.9.1 System Oscillator (SYSOSC)
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz SYSOSCCFG.FREQ=01 4 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 fSYSOSC SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed (1) (2) SETUSEFCL=1, Ta = 25 ℃ -0.41 0.58 SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 85 ℃ -0.80 0.93 SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 105 ℃ -0.80 1.09 SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃ -0.80 1.30 fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies(1) SETUSEFCL=1, Ta = 25 ℃, ±0.1% ±25ppm ROSC -0.5 0.7 SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 85 ℃, ±0.1% ±25ppm ROSC -1.1 1.2 SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 105 ℃, ±0.1% ±25ppm ROSC -1.1 1.4 SETUSEFCL=1, -40 ℃ ≤ Ta ≤ 125 ℃, ±0.1% ±25ppm ROSC -1.1 1.7 fSYSOSC SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled when the internal ROSC resistor is used (4) SETUSEFCL=1 -40 ℃ ≤ Ta ≤ 125 ℃ -1.4 1.8 % fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40 ℃ ≤ Ta ≤ 125 ℃ -2.6 1.8 fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40 ℃ ≤ Ta ≤ 125 ℃ -2.7 2.3 fSYSOSC External resistor put between ROSC pin and VSS (1) SETUSEFCL=1 100 kΩ fSYSOSC Settling time to target accuracy (3) SETUSEFCL=1, ±0.1% 25ppm ROSC (1) 30 us fSYSOSC fSYSOSC additional undershoot accuracy during tsettle (3) SETUSEFCL=1, ±0.1% 25ppm ROSC (1) -11 % (1) The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL. Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy). See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies. ROSC does not need to be populated if the FCL is not enabled. (2) Represents the device accuracy only. The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy. Performance for a ±0.1% ±25ppm ROSC is given as a reference point. (3) When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved. (4) The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an internal reference resistor when using the FCL. See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.9.1.1 SYSOSC Typical Frequency Accuracy
Temperature (°C) SYSOSC Accuracy (%) -40 -20 0 20 40 60 80 100 120 -1.5 -0.5 0.5 1.5 Typical Max Min Figure 7-2. SYSOSC Accuracy with FCL On (32MHz) FCL-on accuracy is based on a 0.1% tolerance 25 ppm/°C ROSC resistor. Temperature (°C) SYSOSC Accuracy (%) -40 -20 0 20 40 60 80 100 120 -2.5 -1.5 -0.5 0.5 1.5 Typical Max Min Figure 7-3. SYSOSC Accuracy with FCL Off (32MHz)
7.9.2 Low Frequency Oscillator (LFOSC)
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLFOSC LFOSC frequency 32768 Hz LFOSC accuracy ILFOSC LFOSC current consumption 300 nA tstart, LFOSC LFOSC start-up time 1.7 ms
7.9.3 System Phase Lock Loop (SYSPLL)
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSYSPLLREF SYSPLL reference frequency range 4 48 MHz fVCO VCO output frequency 80 400 MHz fSYSPLL SYSPLL output frequency range (1) SYSPLLCLK0, SYSPLLCLK1 2.5 200 MHz SYSPLLCLK2X 10 800 DCPLL SYSPLL output duty cycle fSYSPLLREF=32MHz, fVCO=160MHz 45 55 % JitterSYSPLL SYSPLL RMS cycle-to-cycle jitter fSYSPLLREF=32MHz, fVCO=160MHz ps SYSPLL RMS period jitter 15.5 ISYSPLL SYSPLL current consumption fSYSPLLREF=32MHz, fVCO=160MHz 316 µA tstart, SYSPLL SYSPLL start-up time fSYSPLLREF=32MHz, fVCO=160MHz, ±0.5% accuracy 7 18 us (1) The SYSPLL may support higher output frequencies than the device clock system supports. Ensure that the device maximum frequency specifications are not violated when configuring the SYSPLL output frequencies.
7.9.4 Low Frequency Crystal/Clock
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low frequency crystal oscillator (LFXT) fLFXT LFXT frequency 32768 Hz www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.9.4 Low Frequency Crystal/Clock (continued)
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DCLFXT LFXT duty cycle 30 70 % OALFXT LFXT crystal oscillation allowance 419 kΩ CL, eff Integrated effective load capacitance(1) 1 pF tstart, LFXT LFXT start-up time 483 640 ms ILFXT LFXT current consumption XT1DRIVE=0, LOWCAP=1 200 nA Low frequency digital clock input (LFCLK_IN) fLFIN LFCLK_IN frequency (2) SETUSEEXLF=1 29491 32768 36045 Hz DCLFIN LFCLK_IN duty cycle (2) SETUSEEXLF=1 40 60 % LFCLK Monitor fFAULTLF LFCLK monitor fault frequency (3) MONITOR=1 2800 4200 8400 Hz (1) This includes parasitic bond and package capacitance (≈2pF per pin), calculated as CLFXIN×CLFXOUT/(CLFXIN+CLFXOUT), where CLFXIN and CLFXOUT are the total capacitance at LFXIN and LFXOUT, respectively. (2) The digital clock input (LFCLK_IN) accepts a logic level square wave clock. (3) The LFCLK monitor may be used to monitor the LFXT or LFCLK_IN. It will always fault below the MIN fault frequency, and will never fault above the MAX fault frequency.
7.9.5 High Frequency Crystal/Clock
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High frequency crystal oscillator (HFXT) fHFXT HFXT frequency HFXTRSEL=00 4 8 MHz HFXTRSEL=01 8.01 16 HFXTRSEL=10 16.01 32 HFXTRSEL=11 32.01 48 DCHFXT HFXT duty cycle HFXTRSEL=00 40 65 HFXTRSEL=01 40 60 HFXTRSEL=10 40 60 HFXTRSEL=11 40 60 OAHFXT HFXT crystal oscillation allowance HFXTRSEL=00 (4 to 8MHz range) 2 kΩ CL, eff Integrated effective load capacitance(1) 1 pF tstart, HFXT HFXT start-up time (2) HFXTRSEL=11, 32MHz crystal 0.5 ms IHFXT HFXT current consumption(2) fHFXT=4MHz, Rm=300Ω, CL=12pF 75 µAfHFXT=48MHz, Rm=30Ω, CL=12pF, Cm=6.26fF, Lm=1.76mH 600 High frequency digital clock input (HFCLK_IN) fHFIN HFCLK_IN frequency (3) USEEXTHFCLK=1 4 48 MHz DCHFIN HFCLK_IN duty cycle (3) USEEXTHFCLK=1 40 60 % (1) This includes parasitic bond and package capacitance (≈2pF per pin), calculated as CHFXIN×CHFXOUT/(CHFXIN+CHFXOUT), where CHFXIN and CHFXOUT are the total capacitance at HFXIN and HFXOUT, respectively. (2) The HFXT startup time (tstart, HFXT) is measured from the time the HFXT is enabled until stable oscillation for a typical crystal. Start-up time is dependent upon crystal frequency and crystal specifications. Refer to the HFXT section of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.Current consumption increases with higher RSEL and start up time is decreases with higher RSEL. (3) The digital clock input (HFCLK_IN) accepts a logic level square wave clock. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.10 Digital IO
7.10.1 Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level input voltage ODIO (1) VDD≥1.62V 0.7*VDD 5.5 V VDD≥2.7V 2 5.5 V All I/O except ODIO & Reset VDD≥1.62V 0.7*VDD VDD+0.3 V VIL Low level input voltage ODIO VDD≥1.62V -0.3 0.3*VDD V VDD≥2.7V -0.3 0.8 V All I/O except ODIO & Reset VDD≥1.62V -0.3 0.3*VDD V VHYS Hysteresis ODIO 0.05*VDD V All I/O except ODIO 0.1*VDD V Ilkg High-Z leakage current SDIO(2) (3) 50(4) nA RPU Pull up resistance All I/O except ODIO 40 kΩ RPD Pull down resistance 40 kΩ CI Input capacitance 5 pF VOH High level output voltage SDIO VDD≥2.7V, |IIO|,max=6mA VDD≥1.71V, |IIO|,max=2mA VDD≥1.62V, |IIO|,max=1.5mA -40 °C ≤Tj≤25 °C VDD-0.4 V VDD≥2.7V, |IIO|,max=6mA VDD≥1.71V, |IIO|,max=2mA VDD≥1.62V, |IIO|,max=1.5mA -40 °C ≤Tj≤130 °C VDD-0.45 HSIO VDD≥2.7V, DRV=1, |IIO|,max=6mA VDD≥1.71V, DRV=1, |IIO|,max=3mA VDD≥1.62V, DRV=1, |IIO|,max=2mA -40 °C ≤Tj≤25 °C VDD-0.4 VDD≥2.7V, DRV=1, |IIO|,max=6mA VDD≥1.71V, DRV=1, |IIO|,max=3mA VDD≥1.62V, DRV=1, |IIO|,max=2mA -40 °C ≤Tj≤130 °C VDD-0.4 VDD≥2.7V, DRV=0, |IIO|,max=4mA VDD≥1.71V, DRV=0, |IIO|,max=2mA VDD≥1.62V, DRV=0, |IIO|,max=1.5mA -40 °C ≤Tj≤25 °C VDD-0.45 VDD≥2.7V, DRV=0, |IIO|,max=4mA VDD≥1.71V, DRV=0, |IIO|,max=2mA VDD≥1.62V, |IIO|,max=1.5mA -40 °C ≤Tj≤130 °C VDD-0.45 HDIO VDD≥2.7V, DRV=1, |IIO|,max=20mA VDD≥1.71V, DRV=1, |IIO|,max=10mA VDD-0.4 VDD≥2.7V, DRV=0, |IIO|,max=6mA VDD≥1.71V, DRV=0, |IIO|,max=2mA VDD-0.4 www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.10.1 Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Low level output voltage SDIO VDD≥2.7V, |IIO|,max=6mA VDD≥1.71V, |IIO|,max=2mA VDD≥1.62V, |IIO|,max=1.5mA -40 °C ≤Tj≤25 °C 0.4 V SDIO VDD≥2.7V, |IIO|,max=6mA VDD≥1.71V, |IIO|,max=2mA VDD≥1.62V, |IIO|,max=1.5mA -40 °C ≤Tj≤130 °C 0.45 HSIO VDD≥2.7V, DRV=1, |IIO|,max=6mA VDD≥1.71V, DRV=1, |IIO|,max=3mA VDD≥1.62V, DRV=1, |IIO|,max=2mA Tj≤85 °C 0.4 HSIO VDD≥2.7V, DRV=1, |IIO|,max=6mA VDD≥1.71V, DRV=1, |IIO|,max=3mA VDD≥1.62V, DRV=1, |IIO|,max=2mA -40 °C ≤Tj≤130 °C 0.45 HSIO VDD≥2.7V, DRV=0, |IIO|,max=4mA VDD≥1.71V, DRV=0, |IIO|,max=2mA VDD≥1.62V, DRV=0, |IIO|,max=1.5mA Tj≤85 °C 0.4 HSIO VDD≥2.7V, DRV=0, |IIO|,max=4mA VDD≥1.71V, DRV=0, |IIO|,max=2mA VDD≥1.62V, DRV=0, |IIO|,max=1.5mA -40 °C ≤Tj≤130 °C 0.45 HDIO VDD≥2.7V, DRV=1, |IIO|,max=20mA VDD≥1.71V, DRV=1, |IIO|,max=10mA 0.4 HDIO VDD≥2.7V, DRV=0, |IIO|,max=6mA VDD≥1.71V, DRV=0, |IIO|,max=2mA 0.4 ODIO VDD≥2.7V, IOL,max=8mA VDD≥1.71V, IOL,max=4mA -40 °C ≤Tj≤25 °C 0.4 ODIO VDD≥2.7V, IOL,max=8mA VDD≥1.71V, IOL,max=4mA -40 °C ≤Tj≤130 °C 0.45 (1) I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed (2) The leakage current is measured with VSS or VDD applied to the corresponding pin(s), unless otherwise noted. (3) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. (4) This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be as high as 100nA.
7.10.2 Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO VDD ≥ 1.71V, CL= 20pF 16 MHz VDD ≥ 2.7V, CL= 20pF 32 HSIO VDD ≥ 1.71V, DRV = 0, CL= 20pF 16 VDD ≥ 1.71V, DRV = 1, CL= 20pF 24 VDD ≥ 2.7V, DRV = 0, CL= 20pF 32 VDD ≥ 2.7V, DRV = 1, CL= 20pF 40 HDIO VDD ≥ 1.71V, DRV = 0, CL= 20pF 16 VDD ≥ 2.7V, DRV = 0, CL= 20pF 20 ODIO VDD ≥ 1.71V, FM+, CL= 20pF - 100pF 1 MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.10.2 Switching Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3*fmax s tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL= 20pF-100pF 20*VDD/5.5 120 ns
7.11 Analog Mux VBOOST
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVBST VBOOST current adder MCLK/ULPCLK is LFCLK 0.7 µAMCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz 10.6 tSTART,VBST VBOOST startup time 12 20 us
7.12 ADC
7.12.1 Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vin(ADC) Analog input voltage range(1) Applies to all ADC analog input pins 0 VDD V VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from internal reference (VREF) VREF V VR- Negative ADC reference voltage 0 V FS ADC sampling frequency RES = 0x0 (12-bit mode) 4 MspsRES = 0x1 (10-bit mode) 4 RES = 0x2 (8-bit mode) , SCOMP = 2 5.3 I(ADC) Operating supply current into VDD terminal FS = 4MSPS, VR+ = VDD 1.5(2) mA CS/H ADC sample-and-hold capacitance 3.3 pF Rin ADC input resistance 0.5 kΩ ENOB Effective number of bits External reference (3) 10.9 11.1 bit External reference (4), HW Averaging Enabled, 16 Samples and 2bit shift 12.3 12.5 Internal reference, VR+ = VREF = 2.5V (VRSEL = 1h)(5) 9.9 10.8 Internal reference, VR+ = VREF = 2.5V (VRSEL = 2h) 9.2 SNR Signal-to-noise ratio External reference (3) 68 dB External reference (4), HW Averaging Enabled, 16 Samples and 2bit shift 78 Internal reference, VR+ = VREF = 2.5V (VRSEL = 1h)(5) 66 Internal reference, VR+ = VREF = 2.5V (VRSEL = 2h) 57 PSRRDC Power supply rejection ratio, DC External reference (3), VDD = VDD(min) to VDD(max) 62 dBVDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 53 PSRRAC Power supply rejection ratio, AC External reference (3), ΔVDD = 0.1 V at 1 kHz 61 dBΔVDD = 0.1 V at 1 kHz Internal reference, VR+ = VREF = 2.5V 52 Twakeup ADC Wakeup Time Assumes internal reference is active 5 us www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.12.1 Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor (4)(6) -1.5 1 % ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 µA (1) The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results. (2) The internal reference (VREF) supply current is not included in current consumption parameter I(ADC). (3) All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin (4) Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3. (5) Please note that to achieve this ENOB using internal reference VREF, VRSEL bit in MEMCTL register needs to be set to the external reference mode. This will set the REFN as VREF- and REFP as VREF+. In this configuration ,no external connections can be made on the VREF- and VREF+ pins. The REFN pin should be connected to device ground. (6) Characterized using external reference (VREFSEL = 1)
7.12.2 Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fADCCLK ADC clock frequency 4 48 MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 62.5 ns tSample_PGA Sampling time with OPA (1) 12-bit mode GBW = 0x1, PGA gain = x1 0.22 µs GBW = 0x1, PGA gain = x32 2.6 µs tSample_DAC Sampling time with DAC as input (2) 0.5 µs tSample_GPAMP Sampling time with GPAMP 3 µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 5 µs (1) Only applies for devices with OPA (2) Only applies for devices with DAC
7.12.3 Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all linearity parameters are measured using 12-bit resolution mode (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EI Integral linearity error (INL) External reference (2) External reference (2) -2 2 LSB ED Differential linearity error (DNL) No missing codes External reference (2) External reference (2) -1 1 LSB EO Offset error Internal or External reference (2) -2 2 mV EG Gain error External reference (2) -3 3 LSB (1) Total Unadjusted Error (TUE) can be calculated from EI , EO , and EG using the following formula: TUE = √( EI 2 + |EO|2 + EG 2 ) Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate (2) All external reference specifications are measured with VR+ = VREF+ = VDD and VR- = VSS = 0V, external 1uF cap on VREF+ pin. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.12.4 Typical Connection Diagram
Figure 7-4. ADC Input Network 1. Refer to ADC Electrical Characteristics for the values of Rin and CS/H 2. Refer to Digital IO Electrical Characteristics for the value of CI 3. Cpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitry Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: 1. Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI) 2. K= ln(2n/Settling error) – ln((Cpar + CI)/CS/H) 3. T (Min sampling time) = K × Tau
7.13 Temperature Sensor
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSTRIM Factory trim temperature (1) ADC and VREF configuration: RES=0 (12-bit mode), VRSEL= 0h (VDD = 3.3V), ADC tsample = 12.5uS 27 30 33 ℃ TSc Temperature coefficient -40℃ ≤ Tj ≤ 130℃ -1.9 -1.8 -1.7 mV/℃ tSET, TS Temperature sensor settling time (2) ADC and VREF configuration: RES=0 (12-bit mode), VRSEL= 0h (VDD = 3.3V), ADC CHANNEL=11 12.5 us (1) Higher absolute accuracy may be achieved through user calibration. Please refer to temperature sensor chapter in detailed description section. (2) This is the minimum required ADC sampling time when measuring the temperature sensor.
7.14 VREF
7.14.1 Voltage Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 0 2.7 V BUFCONFIG = 1 1.62 VREF Voltage reference output voltage BUFCONFIG = 1 1.38 1.4 1.42 V BUFCONFIG = 0 2.46 2.5 2.54
7.14.2 Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 166 330 µA IDrive VREF output drive strength (1) Drive strength supported on VREF+ device pin 100 µA ISC VREF short circuit current 100 mA www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.14.2 Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TCVREF Temperature coefficient of VREF (Bandgap+VRBUF) (3) BUFCONFIG = {1} BUFCONFIG = {1} 75 ppm/°C TCVREF Temperature coefficient of VREF (Bandgap+VRBUF) (3) BUFCONFIG = {0} BUFCONFIG = {0} 75 ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 -57 -63 dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 -49 -53 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFCONFIG = 1 500 µVrms BUFCONFIG = 0 900 CVREF Recommended VREF decoupling capacitor on VREF+ pin (3) (4) (5) 0.7 1 1.15 µF Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V, CVREF = 1µF 200 µS Trefresh VREF External capacitor refresh time 31.25 (1) The specified MAX output drive strength is supported regardless of which peripherals are being used in the device. (2) The temperature coefficient of the VREF output is the sum of TCVRBUF and the temperature coefficient of the internal bandgap reference. (3) Decoupling capacitor (CVREF) is required when using the internal voltage reference VREF and should be connected from the VREF+ pin to VREF-/GND. When using the VREF+/- pins to supply an external reference, a decoupling capacitor value should be selected based on the external reference source. (4) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable (5) The VREF module should only be enabled when CVREF is connected and should not be enabled otherwise.
7.15 Comparator (COMP)
7.15.1 Comparator Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V Voffset Input offset voltage -20 20 mV Vhys DC input hysteresis HYST=00h 0.4 mV HYST=01h 5 15 HYST=02h 10 30 HYST=03h 15 45 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns Output Filter off, Overdrive = 100 mV, Low Power Mode 1.2 4 µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode (comparator only) 10 µs Startup time to reach propagation delay specification, Low Power Mode (comparator only) 10 µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 130 200 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.84 2.7 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 102 180 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.15.1 Comparator Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V INL Integral nonlinearity of 8-bit DAC -1 1 LSB DNL Differential nonlinearity of 8- bit DAC -1 1 LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Offset error Offset error of 8-bit DAC -5 5 mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs
7.16 DAC
7.16.1 DAC_Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREF Reference voltage VDD, External, Internal(1.4V, 2.5V) 1.4 VDD V IDAC DAC current consumption from VDD VREF= VDD, No load 300 µA
7.16.2 DAC Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output voltage range No load, Vref = VDD, DATA = 0x0 20 mV VO Output voltage range No load, Vref = VDD, DATA = 0xFFF VDD-0.05 VDD-0.01 VDD V VO Output voltage range Rload = 3.3kΩ, Vref = VDD, DATA = 0x0 0.13 V VO Output voltage range Rload = 3.3kΩ, Vref = VDD, DATA = 0xFFF VDD-0.13 VDD-0.1 VDD V CL(DAC) Load capacitance 100 pF IL(DAC) Load current -1 1 mA ROUT(DAC) Output resistance Rload = 3.3kΩ, Vref = VDD 1.2 10 Ω
7.16.3 DAC Dynamic Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate DATA = 0x80 → 0xF7F → 0x80, Vref = external reference 5.5 V/µs GE Glitch energy DATA = 0x800 → 0x7FF → 0x800, Vref = external reference 1.2 nV-s PSRR_DC Power supply rejection ratio, DC ΔVDD = 100 mV, DATA = 0xFFF, Vref = external reference 79.5 dB PSRR_AC Power supply rejection ratio, AC ΔVDD = 100mV at 100kHz, DATA = 0xFFF, Vref = external reference 25.7 dB SNR Signal-to-noise ratio Vref = external reference, 4kHz input with 1Msps sampling rate(1) 80.9 dB THD Total harmonic distortion Vref = external reference, 4kHz input with 1Msps sampling rate(1) 71.5 dB SINAD Signal-to-noise and distortion Vref = external reference, 4kHz input with 1Msps sampling rate(1) 71.1 dB ENOB Effective number of bits Vref = external reference, 4kHz input with 1Msps sampling rate(1) 11.5 bits (1) A low pass filter with 300 Hz to 4 kHz pass band connected at DAC output pin. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.16.4 DAC Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 bits DNL Differential nonlinearity Vref = internal or external or VDD reference(1) -1 1 LSB INL Integral nonlinearity Vref = internal or external or VDD reference(1) -2 2 LSB EG Gain error Vref = internal or external or VDD reference(1) -1 -0.5 1 %FSR EO Offset error Vref = internal or external reference or vdd, With calibration (1) -2 0.5 2 mV EO Offset error Vref = internal or external or VDD reference, without calibration (1) -20 20 mV tcal Time for offset calibration 1.3 ms (1) DAC valid output range is 0.3 to VDD-0.3
7.16.5 DAC Timing Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tON,12b Turn on time from off state (VREF ready) DATA = 0xFFF, Error < ±2 LSB, Vref = internal reference 4.5 6.9 µs tS(FS) Full scale settling time DATA = 0x1EC->0xFFF->0x1EC, Error< ±2 LSB, Vref = internal reference 0.8 1 µs
7.17 GPAMP
7.17.1 Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1 VRRI = 0x1 1 VDD-0. RRI = 0x2 -0.1 VDD-0. Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA IO= 0 mA, RRI = 0x1 or 0x2 93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOP = 0x0 ±0.2 ±6.5 mV CHOP = 0x1 ±0.08 ±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOP = 0x0 7.7 µV/°C CHOP = 0x1 0.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOP=0x0 TA = 25°C ±40 pA TA = 125°C ±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOP = 0x1 TA = 25°C ±200 TA = 125°C ±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOP = 0x0 48 77 dB CHOP = 0x1 56 105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz en f = 10 kHz 19 Rin Input resistance (1) 0.65 kΩ Cin Input capacitance Common mode 4 pF Differential 2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.17.1 Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs THDN Total Harmonic Distortion + Noise 0.012 % ILoad Output load current 4 mA CLoad Output load capacitance 200 pF (1) Rin here means the input resistance of mux in GPAMP.
7.17.2 Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tdisable GPAMP disable time 4 ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs
7.18 OPA
7.18.1 Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V RRI = 0x1 -0.1 VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV Iq Quiescent current, per op-amp IO= 0mA, RRI = 0x0 GBW = 0x0 94 µA GBW = 0x1 319 IO= 0mA, RRI = 0x1 GBW = 0x0 116 134 GBW = 0x1 401 500 IBCS Burn-out current source current 2 µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBW = 0x1 6 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV CHOP = 0x1 or 0x2 ±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 8.5 µV/°CGBW = 0x1 6 CHOP = 0x1 or 0x2 0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB CHOP = 0x1 or 0x2 74 86 www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.18.1 Electrical Characteristics (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Ibias Input bias current 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±50 pA TA = 125°C ±0.35 ±100 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA TA = 125°C ±0.4 ±104 nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1V RRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CHOP = 0x1 or 0x2 73 102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz f = 10kHz 88 Integrated voltage noise, input referred f = 0.1Hz to 10Hz, GBW = 0x0, Noninverting, unity gain CHOP = 0x0 75 µVpp CHOP = 0x1 or 0x2 2 Integrated voltage noise, output referred f = 0.1Hz to 10MHz, GBW = 0x0, CHOP = 0x0, Noninverting, unity gain 1.5 mVpp Rin Input resistance (1) 2.6 kΩ Cin Input capacitance Common mode 3 pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB PM phase margin CL = 40pF GBW = 0x0 57 degree GBW = 0x1 50 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs GBW = 0x1 4.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 ILoad Output load current GBW = 0x0 ±9 mA GBW = 0x1 ±30 CLoad Output load capacitance 40 pF (1) Rin here means the input resistance of mux in OPA.
7.18.2 Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs GBW = 0x1 4.4 6 tdisable OPA disable time 4 ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz GAIN = 0x1 62.5 GAIN = 0x2 31.25 GAIN = 0x3 15.625 GAIN = 0x4 7.8 GAIN = 0x5 3.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs GBW = 0x1 1.3 5 MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.18.3 PGA Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G non- inverting gain Buffer Mode(1) –0.05% 1 +0.05% V/V GAIN = 0x3 –1% 8 +1% inverting gain RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ R2 (feedback resistor) 64 GAIN = 0x2 R1 32 R2 (feedback resistor) 96 GAIN = 0x3 R1 16 R2 (feedback resistor) 112 GAIN = 0x4 R1 8 R2 (feedback resistor) 120 GAIN = 0x5 R1 4 R2 (feedback resistor) 124 G/dV Gain supply drift 0.02 1 %/V G/dT Gain temperature drift 0.002 0.02 %/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 75 dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 55 (1) OPA operates with unity gain in buffer mode, providing impedance matching and signal buffering without the amplification.
7.19 I2C
7.19.1 I2C Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fSCL SCL clock frequency 0.1 0.4 1 MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW LOW period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 ns tSU,DAT Data setup time 250 100 50 ns tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF bus free time between a STOP and START condition 4.7 1.3 0.5 us www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.19.1 I2C Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX tVD;DAT data valid time 3.45 0.9 0.45 us tVD;ACK data valid acknowledge time 3.45 0.9 0.45 us
7.19.2 I2C Filter
over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns
7.19.3 I2C Timing Diagram
tSU,DAT tHD,STAtHD,STA tVD,DAT tSU,STO tBUFtSU,STA tSPttHIGHtttLOWt tHD,DAT Figure 7-5. I2C Timing Diagram
7.20 SPI
7.20.1 SPI
over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SPI fSPI SPI clock frequency Clock max speed = 32MHz 1.62 < VDD < 3.6V Controller mode
16 MHz
Clock max speed = 32MHz 1.62 < VDD < 3.6V Peripheral mode Clock max speed >= 32MHz 1.62 < VDD < 3.6V Controller mode Clock max speed >= 48MHz 1.62 < VDD < 2.7V Controller mode with High speed IO
24 MHz
Clock max speed >= 64MHz 2.7 < VDD < 3.6V Controller mode with High speed IO
32 MHz
Clock max speed >= 32MHz 1.62 < VDD < 3.6V Peripheral mode MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.20.1 SPI (continued)
over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSPI SPI clock frequency Clock max speed >= 48MHz 1.62 < VDD < 2.7V Peripheral mode with High speed IO Clock max speed >= 64MHz 2.7 < VDD < 3.6V Peripheral mode with High speed IO DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tCS.LEAD CS lead-time, CS active to clock SPH=0 1 SPI Clock tCS.LEAD CS lead-time, CS active to clock SPH=1 1/2 SPI Clock tCS.LAG CS lag time, Last clock to CS inactive
1 SPI
tCS.ACC CS access time, CS active to PICO data out 1/2 SPI Clock tCS.DIS CS disable time, CS inactive to PICO high inpedance tSU.CI POCI input data setup time (1) 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns tSU.CI POCI input data setup time (1) 1.62 < VDD < 2.7V, delayed sampling enabled 1 ns tSU.CI POCI input data setup time (1) 2.7 < VDD < 3.6V, no delayed sampling 29 ns tSU.CI POCI input data setup time (1) 1.62 < VDD < 2.7V, no delayed sampling 37 ns tHD.CI POCI input data hold time delayed sampling enabled 24 ns tHD.CI POCI input data hold time no delayed sampling 0 ns tVALID.CO PICO output data valid time (2) 10 ns tHD.CO PICO output data hold time (3) 6 ns Peripheral tCS.LEAD CS lead-time, CS active to clock 11 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out 26 ns tCS.DIS CS disable time, CS inactive to POCI high inpedance 26 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 0 ns tVALID.PO POCI output data valid time(2) 2.7 < VDD < 3.6V 25 ns tVALID.PO POCI output data valid time(2) 1.62 < VDD < 2.7V 31 ns tHD.PO POCI output data hold time(3) 5 ns (1) The POCI input data setup time can be fully compensated when delayed sampling feature is enabled. (2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge (3) Specifies how long data on the output is valid after the output changing SCLK clock edge www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
7.20.2 SPI Timing Diagram
(SPO = 0) POCI SCLK (SPO = 1) CS (inverted) CS PICO tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,CI tHD,CI tVALID,CO tHD,CO 1 / fSPI tSCLK_H/L tSCLK_H/L Controller Mode, SPH = 0 CS (inverted) CS tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,CI tHD,CI tVALID,CO tHD,CO SCLK (SPO = 0) POCI SCLK (SPO = 1) PICO 1 / fSPI tSCLK_H/L tSCLK_H/L Controller Mode, SPH = 1 Figure 7-6. SPI Timing Diagram - Controller Mode CS (inverted) CS tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,PI tHD,PI tVALID,PO tHD,PO SCLK (SPO = 0) PICO SCLK (SPO = 1) POCI 1 / fSPI tSCLK_H/L tSCLK_H/L Peripheral Mode, SPH = 0 CS (inverted) CS tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,PI tHD,PI tVALID,PO tHD,PO SCLK (SPO = 0) PICO SCLK (SPO = 1) POCI 1 / fSPI tSCLK_H/L tSCLK_H/L Peripheral Mode, SPH = 1 Figure 7-7. SPI Timing Diagram - Peripheral Mode
7.21 UART
over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency UART in Power Domain1 80 MHz fUART UART input clock frequency UART in Power Domain0 40 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain1 10 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) UART in Power Domain0 5 MHz MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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7.21 UART (continued)
over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns
7.22 TIMx
over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tres Timer resolution time TIMx in Power Domain 1, fTIMxCLK = 80MHz 12.5 ns TIMx in Power Domain 0, fTIMxCLK = 40MHz 25 ns 1 tTIMxCLK
7.23 TRNG
7.23.1 TRNG Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TRNGIACT TRNG active current TRNG clock = 20MHz 115 µA
7.23.2 TRNG Switching Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TRNGCLKF TRNG input clock frequency 9.5 10 25 MHz TRNGSTARTUP TRNG startup time 520 µs TRNGLAT32 Latency to generate 32 random bits Decimation ratio = 4, TRNG clock = 20MHz 6.4 µs TRNGLAT256 Latency to generate 256 random bits Decimation ratio = 4, TRNG clock = 20MHz 51.2 µs
7.24 Emulation and Debug
7.24.1 SWD Timing
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSWD SWD frequency 10 MHz www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
8 Detailed Description
The following sections describe all of the components that make up the devices in this data sheet. The peripherals integrated into these devices are configured by software through Memory Mapped Registers (MMRs). For more details, see the corresponding chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.1 CPU
The CPU sub system (MCPUSS) implements an Arm Cortex-M0+ CPU, an instruction pre-fetch/cache, a system timer, a memory protection unit, and interrupt management features. The Arm Cortex-M0+ is a cost-optimized, 32-bit CPU which delivers high performance and low power to embedded applications. Key features of the CPU Sub System include:
- Arm Cortex-M0+ CPU supporting clock frequencies from 32kHz to 80 MHz – Armv6-M Thumb instruction set (little endian) with single-cycle 32x32 multiply instruction – Single-cycle access to GPIO registers via Arm single-cycle IO port
- Pre-fetch logic to improve sequential code execution, and I-cache with 4 64-bit cache lines
- System timer (SysTick) with 24-bit down counter and automatic reload
- Memory protection unit (MPU) with 8 programmable regions
- Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail-chaining
- Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency
8.2 Operating Modes
MSPM0G MCUs provide five main operating modes (power modes) to allow for optimization of the device power consumption based on application requirements. In order of decreasing power, the modes are: RUN, SLEEP, STOP, STANDBY, and SHUTDOWN. The CPU is active executing code in RUN mode. Peripheral interrupt events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN mode completely disables the internal core regulator to minimize power consumption, and wake is only possible via NRST, SWD, or a logic level match on certain IOs. RUN, SLEEP, STOP, and STANDBY modes also include several configurable policy options (for example, RUN.x) for balancing performance with power consumption. To further balance performance and power consumption, MSPM0G devices implement two power domains: PD1 (for the CPU, memories, and high performance peripherals), and PD0 (for low speed, low power peripherals). PD1 is always powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 is always powered in RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both disabled in SHUTDOWN mode.
8.2.1 Functionality by Operating Mode (MSPM0G350x)
Supported functionality in each operating mode is given in Table 8-1. Functional key:
- EN: The function is enabled in the specified mode.
- DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained.
- OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.
- NS: The function is not automatically disabled in the specified mode, but it is not supported.
- OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 8-1. Supported Functionality by Operating Mode OPERATING MODE RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT(1) EN DIS DIS DIS OFF LFOSC or LFXT EN (LFOSC or LFXT) OFF HFXT OPT DIS DIS OPT DIS DIS DIS DIS DIS DIS DIS OFF SYSPLL OPT DIS DIS OPT DIS DIS DIS DIS DIS DIS DIS OFF Clocks CPUCLK 80 MHz 32 kHz 32 kHz DIS OFF MCLK to PD1 80 MHz 32 kHz 32 kHz 80 MHz 32 kHz 32 kHz DIS OFF ULPCLK to PD0 40 MHz 32 kHz 32 kHz 40 MHz 32 kHz 32 kHz 4 MHz (1) 4 MHz 32 kHz DIS OFF ULPCLK to TIMG0/8 40 MHz 32 kHz 32 kHz 40 MHz 32 kHz 32 kHz 4 MHz (1) 4 MHz 32 kHz OFF RTCCLK 32 kHz OFF MFCLK OPT DIS OPT DIS OPT DIS OFF MFPCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32 kHz DIS OFF LFCLK to TIMG0/8 32 kHz OFF LFCLK Monitor OPT OFF MCLK Monitor OPT DIS OFF PMU POR monitor EN BOR monitor EN OFF Core regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT DIS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals CRC OPT DIS OFF UART3 OPT DIS OFF SPI0, SPI1 OPT DIS OFF MATHACL OPT OFF AES OPT OFF MCAN0 OPT OFF TIMA0, TIMA1 OPT OFF TIMG6, TIMG7 OPT OFF TIMG1, TIMG12 OPT OFF www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 8-1. Supported Functionality by Operating Mode (continued) OPERATING MODE RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 PD0 Peripherals TIMG0, TIMG8 OPT OFF RTC OPT OFF UART0, UART1, UART2 OPT OPT(2) OFF I2C0, I2C1 OPT OPT(2) OFF GPIOA, GPIOB(3) OPT OPT(2) OFF WWDT0, WWDT1 OPT DIS OFF Analog TRNG OPT OFF ADC0, ADC1(3) OPT NS (triggers supported) OFF DAC0 OPT NS OFF OPA0, OPA1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0, COMP1, COMP2 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD (1) If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as it was in RUN1, and ULPCLK remains at 32 kHz as it was in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as it was in RUN2, and ULPCLK remains at 32 kHz as it was in RUN2. (2) When using the STANDBY1 policy for STANDBY, only TIMG0, TIMG8, and the RTC are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked. (3) For ADCx and GPIO Ports A and B, the digital logic is in PD0 and the register interface is in PD1. These peripherals support fast single-cycle register access when PD1 is active and also support basic operation down to STANDBY mode where PD0 is still active.
8.3 Power Management Unit (PMU)
The power management unit (PMU) generates the internally regulated core supplies for the device and provides supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the PMU itself as well as analog peripherals. Key features of the PMU include:
- Power-on reset (POR) supply monitor
- Brownout reset (BOR) supply monitor with early warning capability using three programmable thresholds
- Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance performance with power consumption
- Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management trim is corrupted For more details, see the PMU chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.4 Clock Module (CKM)
The clock module provides the following oscillators: MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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- LFOSC: Internal low-frequency oscillator (32 kHz)
- SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user trim)
- LFXT/LFCKIN : Low-frequency external crystal oscillator or digital clock input (32 kHz)
- HFXT/HFCKIN: High-frequency external crystal oscillator or digital clock input (4 to 48 MHz)
- SYSPLL: System phase locked loop with 3 outputs (32 to 80 MHz) The following clocks are distributed by the clock module for use by the processor, bus, and peripherals:
- MCLK: Main system clock for PD1 peripherals, derived from SYSOSC, LFCLK, or HSCLK, active in RUN and SLEEP modes
- CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode
- ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes
- MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes
- MFPCLK: 4-MHz fixed mid-frequency precision clock, available in RUN, SLEEP, and STOP modes
- LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes
- ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes
- CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes
- HFCLK: High-frequency clock derived from HFXT or HFCLK_IN, available in RUN and SLEEP mode
- HSCLK: High-speed clock derived from HFCLK or the SYSPLL, available in RUN and SLEEP mode
- CANCLK: CAN functional clock, derived from HFCLK or SYSPLL For more details, see the CKM chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.5 DMA
The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral. The DMA in these devices support the following key features:
- 7 independent DMA transfer channels – 3 full-feature channel (DMA0, DMA1 and DMA2), supporting repeated transfer modes – 4 basic channels (DMA3, DMA4, DMA5 and DMA6) supporting single transfer modes
- Configurable DMA channel priorities
- Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capability
- Transfer counter block size supports up to 64k transfers of any data type
- Configurable DMA transfer trigger selection
- Active channel interruption to service other channels
- Early interrupt generation for ping-pong buffer architecture
- Cascading channels upon completion of activity on another channel
- Stride mode to support data re-organization, such as 3-phase metering applications Table 8-2 lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers. Table 8-2. DMA Trigger Mapping Trigger 0:12 Source Trigger 13:24 Source
0 Software 13 SPI1 Publisher 1
1 Generic Subscriber 0 (FSUB_0) 14 SPI1 Publisher 2
2 Generic Subscriber 1 (FSUB_1) 15 UART3 Publisher 1
3 AES Publisher 1 16 UART3 Publisher 2
4 AES Publisher 2 17 UART0 Publisher 1
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Table 8-2. DMA Trigger Mapping (continued) Trigger 0:12 Source Trigger 13:24 Source
5 AES Publisher 3 18 UART0 Publisher 2
6 DAC0 Publisher 2 19 UART1 Publisher 1
7 I2C0 Publisher 1 20 UART1 Publisher 2
8 I2C0 Publisher 2 21 UART2 Publisher 1
9 I2C1 Publisher 1 22 UART2 Publisher 2
10 I2C1 Publisher 2 23 ADC0 Publisher 2
11 SPI0 Publisher 1 24 ADC1 Publisher 2
12 SPI0 Publisher 2
For more details, see the DMA chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.6 Events
The event manager transfers digital events from one entity (for example, a peripheral) to another (for example, a second peripheral, the DMA, or the CPU). The event manager implements event transfer through a defined set of event publishers (generators) and subscribers (receivers) which are interconnected through an event fabric containing a combination of static and programmable routes. Events that are transferred by the event manager include:
- Peripheral event transferred to the CPU as an interrupt request (IRQ) (Static Event) – Example: RTC interrupt is sent to the CPU
- Peripheral event transferred to the DMA as a DMA trigger (DMA Event) – Example: UART data receive trigger to DMA to request a DMA transfer
- Peripheral event transferred to another peripheral to directly trigger an action in hardware (Generic Event) – Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling Refer to the Event chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for more information. Table 8-3. Generic Event Channels A generic route is either a point-to-point (1:1) route or a point-to-two (1:2) splitter route in which the peripheral publishing the event is configured to use one of several available generic route channels to publish its event to another entity (or entities, in the case of a splitter route), where an entity may be another peripheral, a generic DMA trigger event, or a generic CPU event. CHANID Generic Route Channel Selection Channel Type
0 No generic event channel selected N/A
1 Generic event channel 1 selected 1 : 1
2 Generic event channel 2 selected 1 : 1
3 Generic event channel 3 selected 1 : 1
4 Generic event channel 4 selected 1 : 1
5 Generic event channel 5 selected 1 : 1
6 Generic event channel 6 selected 1 : 1
7 Generic event channel 7 selected 1 : 1
8 Generic event channel 8 selected 1 : 1
9 Generic event channel 9 selected 1 : 1
10 Generic event channel 10 selected 1 : 1
11 Generic event channel 11 selected 1 : 1
12 Generic event channel 12 selected 1 : 2 (splitter)
13 Generic event channel 13 selected 1 : 2 (splitter)
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Table 8-3. Generic Event Channels (continued) A generic route is either a point-to-point (1:1) route or a point-to-two (1:2) splitter route in which the peripheral publishing the event is configured to use one of several available generic route channels to publish its event to another entity (or entities, in the case of a splitter route), where an entity may be another peripheral, a generic DMA trigger event, or a generic CPU event. CHANID Generic Route Channel Selection Channel Type
14 Generic event channel 14 selected 1 : 2 (splitter)
15 Generic event channel 15 selected 1 : 2 (splitter)
8.7 Memory
8.7.1 Memory Organization
Table 8-4 summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map section in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual . Table 8-4. Memory Organization MEMORY REGION SUBREGION MSPM0G3505 MSPM0G3506 MSPM0G3507 Code (Flash) ECC Corrected 32KB-8B(1) 0x0000.0000 to 0x0000.7FF8 64KB-8B(1) 0x0000.0000 to 0x0000.FFF8 128KB-8B(1) 0x0000.0000 to 0x0001.FFF8 ECC Uncorrected 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 0x0040.0000 to 0x0041.FFF8 SRAM (SRAM) Parity checked 0x2010.0000 to 0x2010.3FFF 0x2010.0000 to 0x2010.7FFF 0x2010.0000 to 0x2010.7FFF Un-checked 0x2020.0000 to 0x2020.3FFF 0x2020.0000 to 0x2020.7FFF 0x2020.0000 to 0x2020.7FFF Parity code 0x2030.0000 to 0x2030.3FFF 0x2030.0000 to 0x2030.7FFF 0x2030.0000 to 0x2030.7FFF Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF Flash ECC Corrected 0x4100.0000 to 0x4100.8000 0x4100.0000 to 0x4101.0000 0x4100.0000 to 0x4102.0000 Flash ECC Uncorrected 0x4140.0000 to 0x4140.8000 0x4140.0000 to 0x4141.0000 0x4140.0000 to 0x4142.0000 Flash ECC code 0x4180.0000 to 0x4180.8000 0x4180.0000 to 0x4181.0000 0x4180.0000 to 0x4182.0000 Configuration NVM(NONMAIN) ECC Corrected 512 bytes 0x41C0.0000 to 0x41C0.0200 512 bytes 0x41C0.0000 to 0x41C0.0200 512 bytes 0x41C0.0000 to 0x41C0.0200 Configuration NVM(NONMAIN) ECC Uncorrected 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 Configuration NVM(NONMAIN) ECC code 0x41C2.0000 to 0x41C2.0200 0x41C2.0000 to 0x41C2.0200 0x41C2.0000 to 0x41C2.0200 FACTORY Corrected 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 FACTORY Uncorrected 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 FACTORY ECC code 0x41C6.0000 to 0x41C6.0080 0x41C6.0000 to 0x41C6.0080 0x41C6.0000 to 0x41C6.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 8-4. Memory Organization (continued) MEMORY REGION SUBREGION MSPM0G3505 MSPM0G3506 MSPM0G3507 System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF (1) First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program/erase cycles.
8.7.2 Peripheral File Map
Table 8-5 lists the available peripherals and the register base address for each. Table 8-5. Peripherals Summary Peripheral Name Base Address Size COMP0 0x40008000 0x2000 COMP1 0x4000A000 0x2000 COMP2 0x4000C000 0x2000 DAC_OUT 0x40018000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 WWDT1 0x40082000 0x2000 TIMG0 0x40084000 0x2000 TIMG8 0x40090000 0x2000 RTC 0x40094000 0x2000 GPIO0 0x400A0000 0x2000 GPIO1 0x400A2000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART2 0x40102000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 MATHACL 0x40410000 0x2000 WUC 0x40424000 0x1000 IOMUX 0x40428000 0x2000 DMA 0x4042A000 0x2000 CRC 0x40440000 0x2000 AES 0x40442000 0x2000 TRNG 0x40444000 0x2000 SPI0 0x40468000 0x2000 SPI1 0x4046A000 0x2000 UART3 0x40500000 0x2000 CAN-FD 0x40508000 0x8000 ADC0 0x40000000 0x1000 ADC1 0x40002000 0x1000 MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 8-5. Peripherals Summary (continued) Peripheral Name Base Address Size ADC0(1) 0x40556000 0x1000 ADC1(1) 0x40558000 0x1000 TIMA0 0x40860000 0x2000 TIMA1 0x40862000 0x2000 TIMG6 0x40868000 0x2000 TIMG7 0x4086A000 0x2000 TIMG12 0x40870000 0x2000 (1) Aliased region of ADC0 and ADC1 memory-mapped registers www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
8.7.3 Peripheral Interrupt Vector
Table 8-6 shows the IRQ number and the interrupt group number for each peripherals in this device. Table 8-6. Interrupt Vector Number PERIPHERAL NAME NVIC IRQ GROUP IIDX WWDT0 0 0 WWDT1 0 1 DEBUGSS 0 2 NVMNW 0 3 EVENT SUB PORT0 0 4 EVENT SUB PORT1 0 5 SYSCTL 0 6 GPIO0 1 0 GPIO1 1 1 COMP0 1 2 COMP1 1 3 COMP2 1 4 TRNG 1 5 TIMG8 2 - UART3 3 - ADC0 4 - ADC1 5 - CAN-FD 6 - DAC_OUT 7 - SPI0 9 - SPI1 10 - UART1 13 - UART2 14 - UART0 15 - TIMG0 16 - TIMG6 17 - TIMA0 18 - TIMA1 19 - TIMG7 20 - TIMG12 21 - I2C0 24 - I2C1 25 - AES 28 - RTC 30 - DMA 31 -
8.8 Flash Memory
A single bank of non-volatile flash memory is provided for storing executable program code and application data. Key features of the flash include:
- Hardware ECC protection (encode and decode) with single bit error correction and double-bit error detection
- In-circuit program and erase operations supported across the entire recommended supply range MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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- Small 1KB sector sizes (minimum erase resolution of 1KB)
- Up to 100,000 program/erase cycles on the lower 32KB of the flash memory, with up to 10,000 program/ erase cycles on the remaining flash memory (devices with 32KB support 100,000 cycles on the entire flash memory) For a complete description of the flash memory, see the NVM chapter of the technical reference manual.
8.9 SRAM
MSPM0Gxx MCUs include a low power, high performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. MSPM0Gxx MCUs also provides up to 32KB of SRAM with hardware parity. SRAM memory can be used for storing volatile information such as the call stack, heap, global data, and code. The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes and is lost in shutdown mode. A write protection mechanism is provided to allow the application to prevent unintended modifications to the SRAM memory. Write protection is useful when placing executable code into SRAM as it provides a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption.
8.10 GPIO
The general purpose input/output (GPIO) peripheral provides the user with a means to write data out and read data in to and from the device pins. Through the use of the Port A and Port B GPIO peripherals, these devices support up to 60 GPIO pins. The key features of the GPIO module include:
- 0 wait state MMR access from CPU
- Set/Clear/Toggle multiple bits without the need of a read-modify-write construct in software
- GPIOs with "Standard with Wake" drive functionality able to wake the device from SHUTDOWN mode
- "FastWake" feature enables low-power wakeup from STOP and STANDBY modes for any GPIO port
- User controlled input filtering For more details, see the GPIO chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.11 IOMUX
The IOMUX peripheral enables IO pad configuration and controls digital data flow to and from the device pins. The key features of the IOMUX include:
- IO Pad configuration registers allow for programmable drive strength, speed, pullup-down, and more
- Digital pin muxing allows for multiple peripheral signals to be routed to the same IO pad
- Pin functions and capabilities are user-configured using the PINCM register For more details, see the IOMUX chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.12 ADC
Both 12-bit analog-to-digital converter (ADC) modules in these devices, ADC0 and ADC1, support fast 12-bit conversions with single-ended inputs and simultaneous sampling operation. ADC features include:
- 12-bit output resolution at 4Msps with greater than 11.1 ENOB
- HW averaging enables 14-bit effective resolution at 250ksps
- Up to 17 total external input channels with individual result storage registers
- Internal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with OPA, DAC, etc.)
- Software selectable reference: www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
– Configurable internal reference voltage of 1.4V and 2.5V (requires decoupling capacitor on VREF+/- pins) – MCU supply voltage (VDD) – External reference supplied to the ADC through the VREF+/- pins
- Operates in RUN, SLEEP, and STOP modes Table 8-7. ADC Channel Mapping CHANNEL[0:7] SIGNAL NAME(2) CHANNEL[8:15] SIGNAL NAME(1) (2) ADC0 ADC1 ADC0 ADC1
1 A0_1 A1_1 9 - -
2 A0_2 A1_2 10 - -
3 A0_3 A1_3 11 Temperature Sensor -
4 A0_4 A1_4 12 A0_12 Temperature Sensor
5 A0_5 A1_5 13 OPA0 output OPA1 output
6 A0_6 A1_6 14 GPAMP output GPAMP output
7 A0_7 A1_7 15 Supply/Battery
(1) Italicized signal names are purely internal to the SoC. These signals are used for internal peripheral interconnections. (2) For more information about device analog connections please refer to Section 8.30 (3) Note that each channel 8 of each ADC can be sampled by the opposite ADC. (4) When DAC_OUT is used, A1_0 cannot be used to sample external signals. Avoid using external circuitry on the PA15 pin when using DAC_OUT. For more details, see the ADC chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.13 Temperature Sensor
The temperature sensor provides a voltage output that changes linearly with device temperature. The temperature sensor output is internally connected to one of ADC input channels to enable a temperature-to- digital conversion. A unit-specific single-point calibration value for the temperature sensor is provided in the factory constants memory region. This calibration value represents the ADC conversion result (in ADC code format) corresponding to the temperature sensor being measured in 12-bit mode with VDD = 3.3V at the factory trim temperature (TSTRIM). The ADC and VREF configuration for the above measurement is as the following: RES=0 (12-bit mode), VRSEL=0h (VDD), ADC t Sample=12.5µs. This calibration value can be used with the temperature sensor temperature coefficient (TS c) to estimate the device temperature. See the temperature sensor section of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for guidance on estimating the device temperature with the factory trim value.
8.14 VREF
The shared voltage reference module (VREF) in these devices contain a configurable voltage reference buffer which allows users to supply a stable reference to on-board analog peripherals. It also supports bringing in an external reference for applications where higher accuracy is required. VREF features include:
- 1.4V and 2.5V user-selectable internal references
- Internal reference supports full speed ADC operation
- Support for bringing in an external reference on VREF+/- device pins
- Requires a decoupling capacitor placed on VREF+/- pins for proper operation. See VREF specification section for more details For more details, see the VREF chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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8.15 COMP
The comparator peripheral in the device compares the voltage levels on two inputs terminals and provides a digital output based on this comparison. It supports the following key features:
- Programmable hysteresis
- Programmable reference voltage: – External reference voltage (VREF IO) – Internal reference voltage (1.4V, 2.5V) – Integrated 8-bit reference DAC, the output can also connect to OPA input terminal internally as an output buffer.
- Configurable operation modes: – High speed mode – Lower power mode
- Programmable output glitch filter delay
- Supports 6 blanking sources . Please refer to CTL2 register in comparator section of TRM
- Support output wake up device from all low power modes
- Output connected to advanced timer fault handling mechanism
- The IPSEL and IMSEL bits in comparator registers can be used to select the comparator channel inputs from device pins or from internal analog modules. Table 8-8. COMP Blanking Source Table CTL2.BLANKSRC VALUE BLANKING SOURCE 1 TIMA0.CC2 2 TIMA0.CC3 3 TIMA1.CC1 4 TIMG12.CC1 5 TIMG6.CC1 6 TIMG7.CC1 Table 8-9. COMP0 Input Channel Selection IPSEL / IMSEL BITS POSITIVE TERMINAL INPUT NEGATIVE TERMINAL INPUT 0x0 COMP0_IN0+ COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x2 COMP0_IN2+ COMP0_IN2- 0x5 DAC_OUT / COMP0_IN3+(1) - 0x6 OPA1 output OPA0 output 0x7 COMP1 positive terminal signal - Table 8-10. COMP1 Input Channel Selection IPSEL / IMSEL BITS POSITIVE TERMINAL INPUT NEGATIVE TERMINAL INPUT 0x0 COMP1_IN0+ COMP1_IN0- 0x1 COMP1_IN1+ COMP1_IN1- 0x2 COMP1_IN2+ COMP1_IN2- 0x5 DAC_OUT / COMP1_IN3+(1) - 0x7 COMP0 positive terminal signal - Table 8-11. COMP2 Input Channel Selection IPSEL / IMSEL BITS POSITIVE TERMINAL INPUT NEGATIVE TERMINAL INPUT 0x0 COMP2_IN0+ COMP2_IN0- 0x1 COMP2_IN1+ COMP2_IN1- (1) The connection to COMP0/1_IN3+ and DAC_OUT connects using the PA15 pin. When connecting DAC_OUT to COMP0/1_IN3+, avoid using external circuitry on the PA15 pin. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
For more information about device analog connections, see Section 8.30. For more details, see the COMP chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.16 DAC
The 12-bit buffered digital-to-analog converter (DAC) in these devices converts a digital input value into an analog voltage to a buffered output channel and it supports the following key features:
- Up to 1-Msps output sampling rate
- 8-bit or 12-bit voltage-output resolution
- Self-calibration option for offset error correction
- Straight binary or twos-complement data format
- Integrated sample time generator for generation of predefined sampling rates
- Integrated FIFO and support DMA operation
- One hardware trigger from event fabric for conversion
- Programmable voltage reference options: – Supply voltage (VDD) – External reference voltage (VREF IO) – Internal reference voltage (1.4V, 2.5V) For more information about device analog connections, see Section 8.30. For more details, see the DAC chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.17 OPA
The zero-drift op amps (OPAs) in these devices, OPA0 and OPA1, are chopper stabilized operational amplifiers with rail-to-rail input/output and a programmable gain stage feedback loop. The OPA peripherals support the following key features:
- Software-selectable zero-drift chopper stabilization for improved accuracy and drift performance
- Factory trimming to remove offset error
- Burnout current source (BCS) integrated to monitor sensor health
- Programmable gain amplifier (PGA) up to 32x The OPA features configurable input muxes P-MUX, N-MUX, and M-MUX to support various analog signal chain amplifier configurations that include general purpose, inverting, noninverting, unity gain, cascade, noninverting cascade, difference, and more. The following tables list the input channel mapping for each OPA. Table 8-12. OPA0 Input Channel Mapping PSEL P-MUX INPUTS NSEL N-MUX INPUTS MSEL M-MUX INPUTS 0x0 Open 0x0 Open 0x0 Open 0x1 OPA0_IN0+ 0x1 OPA0_IN0- 0x1 OPA0_IN1- 0x2 OPA0_IN1+ 0x2 OPA0_IN1- 0x2 GND 0x3 DAC_OUT / OPA0_IN2+(1) 0x3 OPA1_RBOT 0x3 DAC_OUT / OPA0_IN2+(1) 0x4 DAC8.0_OUT 0x4 RTAP 0x4 OPA1_RTOP 0x5 VREF 0x5 RTOP 0x6 OPA1_RTOP 0x7 GPAMP Output 0x8 GROUND Table 8-13. OPA1 Input Channel Mapping PSEL P-MUX INPUTS NSEL N-MUX INPUTS MSEL M-MUX INPUTS 0x0 Open 0x0 Open 0x0 Open 0x1 OPA1_IN0+ 0x1 OPA1_IN0- 0x1 OPA1_IN1- MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 8-13. OPA1 Input Channel Mapping (continued) PSEL P-MUX INPUTS NSEL N-MUX INPUTS MSEL M-MUX INPUTS 0x2 OPA1_IN1+ 0x2 OPA1_IN1- 0x2 GND 0x3 DAC_OUT / OPA1_IN2+(1) 0x3 OPA0_RBOT 0x3 DAC_OUT / OPA1_IN2+(1) 0x4 DAC8.1_OUT 0x4 RTAP 0x4 OPA0_RTOP 0x5 VREF 0x5 RTOP 0x6 OPA0_RTOP 0x7 GPAMP Output 0x8 GROUND (1) The connection to OPA and DAC_OUT connects using the PA15 pin. When connecting DAC_OUT to OPA, avoid using external circuitry on the PA15 pin. For more information about device analog connections, see Section 8.30 For more details, see the OPA chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual.
8.18 GPAMP
The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features:
- Software selectable chopper stabilization
- Rail-to-rail input and output
- Programmable internal unity gain feedback loop For more details, see the ADC chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.19 TRNG
The true random number generator (TRNG) utilizes an internal circuit to generate 32-bit random numbers. The TRNG is intended to be used as a source to a deterministic random number generator (DRNG) to build a FIPS-140-2 compliant system. Key features of the TRNG include:
- Generation of 32-bit random numbers
- A new 32-bit number may be generated every 32 × 4 = 128 TRNG clock cycles
- Built-in health tests
- Available in RUN and SLEEP modes For more details, see the TRNG chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.20 AES
The advanced encryption standard (AES) accelerator offloads AES (FIPS PUB 197) encryption and decryption operations from the CPU. Key features include:
- Support for 128-bit and 256-bit encryption keys
- On-the-fly key expansion
- Offline key generation for decryption
- Shadow register for storing the initial key for all key lengths
- DMA support for ECB, CBC, OFB, and CFB cipher modes
- AES ready interrupt generation
- Available in RUN and SLEEP modes For more details, see the AES chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
8.21 CRC
The cyclical redundancy check (CRC) module provides a signature for an input data sequence. Key features of the CRC module include:
- Support for 16-bit CRC based on CRC16-CCITT
- Support for 32-bit CRC based on CRC32-ISO3309
- Support for bit reversal For more details, see the CRC chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.22 MATHACL
The math accelerator (MATHACL) is a collection of hardware accelerated 32-bit math functions to improve system computational throughput. The MATHACL offloads mathematical calculations performed by the CPU to improve efficiency and CoreMark performance. The following hardware functions are available in the MATHACL:
- Sine/Cosine (SINCOS)
- Arc tangent (ATAN2)
- Square root (SQRT)
- Division (DIV)
- Multiply with 32-bit result (MPY32)
- Square with 32-bit result (SQUARE32)
- Multiply with 64-bit result (MPY64)
- Square with 64-bit result (SQUARE64)
- Multiply-accumulate (MAC)
- Square-accumulate (SAC) For more details, see the MATHACL chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.23 UART
The UART peripherals (UART0, UART1, UART2, and UART3) provide the following key features:
- Standard asynchronous communication bits for start, stop, and parity
- Fully programmable serial interface – 5, 6, 7 or 8 data bits – Even, odd, stick, or no-parity bit generation and detection – 1 or 2 stop bit generation – Line-break detection – Glitch filter on the input signals – Programmable baud rate generation with oversampling by 16, 8 or 3 – Local Interconnect Network (LIN) mode support
- Separated transmit and receive FIFOs support DAM data transfer
- Support transmit and receive loopback mode operation
- See Table 8-14 for detail information on supported protocols Table 8-14. UART Features UART Features UART0 (Extend) UART1 and 2 (Main) UART3 (Main) Active in Stop and Standby Mode Yes Yes - Separate transmit and receive FIFOs Yes Yes Yes Support hardware flow control Yes Yes Yes Support 9-bit configuration Yes Yes Yes Support LIN mode Yes - - Support DALI Yes - - MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 8-14. UART Features (continued) UART Features UART0 (Extend) UART1 and 2 (Main) UART3 (Main) Support IrDA Yes - - Support ISO7816 Smart Card Yes - - Support Manchester coding Yes - - For more details, see the UART chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.24 I2C
The inter-integrated circuit interface (I 2C) peripherals in these devices provide bidirectional data transfer with other I2C devices on the bus and support the following key features:
- 7-bit and 10-bit addressing mode with multiple 7-bit target addresses
- Multiple-controller transmitter or receiver mode
- Target receiver or transmitter mode with configurable clock stretching
- Support Standard-mode (Sm), with a bit rate up to 100 kbit/s
- Support Fast-mode (Fm), with a bit rate up to 400 kbit/s
- Support Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s – Supported on open drain IOs (ODIO) and high-drive (HDIO) IOs only
- Separated transmit and receive FIFOs support DMA data transfer
- Support SMBus 3.0 with PEC, ARP, timeout detection and host support
- Wakeup from low power mode on address match
- Support analog and digital glitch filter for input signal glitch suppression
- 8-entry transmit and receive FIFOs For more details, see the I2C chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.25 SPI
The serial peripheral interface (SPI) peripherals in these devices support the following key features:
- Support ULPCLK/2 bit rate and up to 32Mbits/s in both controller and peripheral mode 1
- Configurable as a controller or a peripheral
- Configurable chip select for both controller and peripheral
- Programmable clock prescaler and bit rate
- Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode)
- Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU performance
- Transmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transfer
- Supports TI mode, Motorola mode and National Microwire format For more details, see the SPI chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.26 CAN-FD
The controller area network (CAN) controller enables communication with a CAN2.0A, CAN2.0B, or CAN-FD bus and is compliant to ISO 11898-1:2015 standard supporting up to 5Mbit/s bit rate. Key features of the CAN-FD peripheral include:
- Full support for 64-byte CAN-FD frames
- Dedicated 1KB message SRAM with ECC
- Configurable transmit FIFO, transmit queue and event FIFO (up to 32 elements)
- Up to 32 dedicated transmit buffers and 64 dedicated receive buffers 1 Only SPI signals on HSIO pins support data rate > 16 Mbits/s; see the Pin Diagrams section for HSIO pins. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
- Two configurable receive FIFOs (up to 64 elements each)
- Up to 128 filter elements
- Two interrupt lines
- Power-down and wake-up support
- Timestamp counter For more details, see the CAN-FD chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.27 WWDT
The windowed watchdog timer (WWDT) can be used to supervise the operation of the device, specifically code execution. The WWDT can be used to generate a reset or an interrupt if the application software does not successfully reset the watchdog within a specified window of time. Key features of the WWDT include:
- 25-bit counter
- Programmable clock divider
- Eight software selectable watchdog timer periods
- Eight software selectable window sizes
- Support for stopping the WWDT automatically when entering a sleep mode
- Interval timer mode for applications which do not require watchdog functionality For more details, see the WWDT chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual.
8.28 RTC
The real-time clock (RTC) operates off of a 32kHz input clock source (typically a low frequency crystal) and provides a time base to the application with multiple options for interrupts to the CPU. Key features of the RTC include:
- Counters for seconds, minutes, hours, day of the week, day of the month, month, and year
- Binary or BCD format
- Leap-year handling
- One customizable alarm interrupt based on minute, hour, day of the week, and day of the month
- Interval alarm interrupt to wake every minute, every hour, at midnight, or at noon
- Interval alarm interrupt providing periodic wake-up at 4096, 2048, 1024, 512, 256, or 128 Hz
- Interval alarm interrupt providing periodic wake-up at 64, 32, 16, 8, 4, 2, 1, and 0.5 Hz
- Calibration for crystal offset error (up to +/- 240ppm)
- Compensation for temperature drift (up to +/- 240ppm)
- RTC clock output to pin for calibration For more details, see the RTC chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual.
8.29 Timers (TIMx)
The timer peripherals in these devices support the following key features, for specific configuration see Table 8-15: Specific features for the general-purpose timer (TIMGx) include:
- 16-bit up, down, up-down or down-up counter, with repeat-reload mode
- 32-bit up, down, up-down or down-up counter, with repeat-reload mode
- Selectable and configurable clock source
- 8-bit programmable prescaler to divide the counter clock frequency
- Two independent channels for – Output compare – Input capture – PWM output – One-shot mode MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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- CC register available in TIMG7 and TIMG12
- Shadow register for load available in TIMG7
- Support quadrature encoder interface (QEI) for positioning and movement sensing available in TIMG8
- Support synchronization and cross trigger among different TIMx instances in the same power domain
- Support interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capability
- Cross trigger event logic for Hall sensor inputs Specific features for the advanced timer (TIMAx) include:
- 16-bit down or up-down counter, with repeat-reload mode
- Selectable and configurable clock source
- 8-bit programmable prescaler to divide the counter clock frequency
- Repeat counter to generate an interrupt or event only after a given number of cycles of the counter
- Up to four independent channels for – Output compare – Input capture – PWM output – One-shot mode
- Shadow register for load and CC register available in both TIMA0 and TIMA1
- Complementary output PWM
- Asymmetric PWM with programmable dead band insertion
- Fault handling mechanism to ensure the output signals in a safe user-defined state when a fault condition is encountered
- Support synchronization and cross trigger among different TIMx instances in the same power domain
- Support interrupt and DMA trigger generation and cross peripherals (such as ADC) trigger capability
- Two additional capture/compare channels for internal events Table 8-15. TIMx Configurations TIMER NAME POWER DOMAIN RESOLUTION PRESCALE R REPEAT COUNTER CAPTURE / COMPARE CHANNELS PHASE LOAD SHADOW LOAD SHADOW CC DEADBAND FAULT QEI TIMG0 PD0 16-bit 8-bit – 2 – – – – – – TIMG6 PD1 16-bit 8-bit – 2 – – – – – – TIMG7 PD1 16-bit 8-bit – 2 – Yes Yes – – – TIMG8 PD0 16-bit 8-bit – 2 – – – – – Yes TIMG12 PD1 32-bit – – 2 – – Yes – – – TIMA0 PD1 16-bit 8-bit 8-bit 4 Yes Yes Yes Yes Yes – TIMA1 PD1 16-bit 8-bit 8-bit 2 Yes Yes Yes Yes Yes – Table 8-16. TIMx Cross Trigger Map (PD1) TSEL.ETSEL Selection TIMA0 TIMA1 TIMG6 TIMG7 TIMG12 6 to 15 Reserved
16 Event Subscriber Port 0
17 Event Subscriber Port 1
Table 8-17. TIMx Cross Trigger Map (PD0) TSEL.ETSEL Selection TIMG0 TIMG8 0 TIMG0.TRIG0 TIMG0.TRIG0 1 TIMG8.TRIG0 TIMG8.TRIG0 www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 8-17. TIMx Cross Trigger Map (PD0) (continued) TSEL.ETSEL Selection TIMG0 TIMG8 2 to 15 Reserved For more details, see the TIMx chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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8.30 Device Analog Connections
Figure 8-1 shows the internal analog connection of the device. OPA0 OPA0_IN1- OPA0_OUT OPA0_IN0+ OPA0_IN0-
2 RTOPRBOT
DAC_OUT / OPA0_IN2+ VDDA Burnout current source
5 Internal signal
DAC_OUT / OPA0_IN2+ DAC8.0_OUT OPA1_RBOT VREF+ 5 OPA1 OPA1_IN1- OPA1_OUT OPA1_IN0- RTOPRBOT RTAP VDDA Burnout current source Internal signal to ADC1 and COMP0 OPA0_RBOT ADC0 0:7 A0_0:A0_7 A1_7 Temp Sense A0_12 OPA0 RTOP GPAMP Output GPAMP GPAMP_IN+ GPAMP_IN- Internal signal to ADC0, ADC1, OPA0, and OPA1 GPAMP_OUT 15Supply/Battery Monitor ADC1 1:7 A1_1:A1_7 A0_7 Temp Sense OPA1 RTOP GPAMP Output 15Supply/Battery Monitor 6OPA1_RTOP GPAMP_OUT 7 OPA0_IN1+ OPA1_IN0+ DAC_OUT / OPA1_IN2+ DAC8.1_OUT VREF+ 5 6OPA0_RTOP GPAMP_OUT 7 OPA1_IN1+ 4OPA1_RTOP DAC_OUT / OPA1_IN2+ OPA0_RTOP COMP
0 COMP0_OUT
DAC_OUT / COMP0_IN3+ 5 6OPA1_RTOP COMP1 positive terminal 7 Reference Generator 8-bit DAC8.0 OPA0+ COMP0 Ref COMP0_IN0+ COMP0_IN1+ COMP0_IN2+ Temp sensor output OPA0_RTOP COMP0_IN0- COMP0_IN1- COMP0_IN2- COMP
1 COMP1_OUT
DAC_OUT / COMP1_IN3+ 5 COMP0 positive terminal 7 Reference Generator 8-bit DAC8.1 OPA1+ COMP1 Ref COMP1_IN0+ COMP1_IN1+ COMP1_IN2+ COMP1_IN0- COMP1_IN1- COMP1_IN2- COMP
2 COMP2_OUT
8-bit DAC8.2 COMP2 Ref COMP0_IN0+ COMP0_IN1+ COMP0_IN0- COMP0_IN1- Comparators Op-amps ADC GPAMP DAC 12bit Buffered DAC DAC_OUT COMP0+ COMP1+ 0A1_0 / DAC_OUT 8GROUND 8GROUND Figure 8-1. Device Analog Connection Note Enabling DAC_OUT connects to PA15 therefore it is not recommended to have any external signal on PA15 when using DAC_OUT. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
8.31 Input/Output Diagrams
The IOMUX manages the selection of which peripheral function is to be used on a digital IO. It also provides the controls for the output driver, input path, and the wake-up logic for wakeup from SHUTDOWN mode. For more information, refer to the IOMUX section of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. The mixed-signal IO pin slice diagram for a full featured IO pin is shown in Figure 8-2. Not all pins will have analog functions, wake-up logic, drive strength control, and pullup or pulldown resistors available. See the device-specific data sheet for detailed information on what features are supported for a specific pin. RPULLUP VDDIO PC RPULLDOWN VSS HYSTEN INENA Unassigned Peripheral 01 Peripheral 15 Unassigned Peripheral 01 Peripheral 15 PF SHUTDOWN Wakeup WCOMP VSS VDDIO DRV Glitch Filter WUEN Wake to PMCU IO pin SHUTDOWN D Q EN D Q EN D Q EN S Q R WAKESTATE Input Logic Output Logic PIPU PIPD To analog peripheral function(s) D Q EN D Q EN D Q EN D Q EN D Q EN SHUTDOWN Latches Pullup enable Pulldown enable INV INV PMOS NMOS DIN DOUT Unassigned Peripheral 01 Peripheral 15 Hi-ZD Q EN Hi-Z Output Mux Output Mux Input Mux Driver Logic Drive strength NMOS Control PMOS Control S R RELEASE Q RSTN RSTN PF != 0 PC 5V tolerant open drain IO (ODIO) does not have PMOS control and pull-up resistor Figure 8-2. Superset Input/Output Diagram MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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8.32 Serial Wire Debug Interface
A serial wire debug (SWD) two-wire interface is provided via an Arm compatible serial wire debug port (SW- DP) to enable access to multiple debug functions within the device. For a complete description of the debug functionality offered on MSPM0 devices, see the debug chapter of the technical reference manual. Table 8-18. Serial Wire Debug Pin Requirements and Functions DEVICE SIGNAL DIRECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data
8.33 Bootstrap Loader (BSL)
The bootstrap loader (BSL) enables configuration of the device as well as programming of the device memory through a UART or I2C serial interface. Access to the device memory and configuration through the BSL is protected by a 256-bit user-defined password, and it is possible to completely disable the BSL in the device configuration, if desired. The BSL is enabled by default from TI to support use of the BSL for production programming. A minimum of two pins are required to use the BSL: the BSLRX and BSLTX signals (for UART), or the BSLSCL and BSLSDA signals (for I 2C). Additionally, one or two additional pins (BSL_invoke and NRST) may be used for controlled invocation of the bootloader by an external host. If enabled, the BSL may be invoked (started) in the following ways:
- The BSL is invoked during the boot process if the BSL_invoke pin state matches the defined BSL_invoke logic level. If the device fast boot mode is enabled, this invocation check is skipped. An external host can force the device into the BSL by asserting the invoke condition and applying a reset pulse to the NRST pin to trigger a BOOTRST, after which the device will verify the invoke condition during the reboot process and start the BSL if the invoke condition matches the expected logic level.
- The BSL is automatically invoked during the boot process if the reset vector and stack pointer are left unprogrammed. As a result, a blank device from TI will invoke the BSL during the boot process without any need to provide a hardware invoke condition on the BSL_invoke pin. This enables production programming using just the serial interface signals.
- The BSL may be invoked at runtime from application software by issuing a SYSRST with BSL entry command. Table 8-19. BSL Pin Requirements and Functions DEVICE SIGNAL CONNECTION BSL FUNCTION BSLRX Required for UART UART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSDA Required for I2C I2C BSL data signal (SDA) BSL_invoke Optional Active-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) For a complete description of the BSL functionality and command set, see the MSPM0 Bootloader User's Guide.
8.34 Device Factory Constants
All devices include a memory-mapped FACTORY region which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. Please refer to Factory Constants chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for more information. www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Table 8-20. DEVICEID DEVICEID address is 0x41C4.0004, PARTNUM is bit 12 to 27, MANUFACTURER is bit 1 to 11. Device PARTNUM MANUFACTURER MSPM0G3505 0xBB88 0x17 MSPM0G3506 0xBB88 0x17 MSPM0G3507 0xBB88 0x17 Table 8-21. USERID USERID address is 0x41C4.0008, PART is bit 0 to 15, VARIANT is bit 16 to 23 Device PART VARIANT Device PART VARIANT M0G3507QPMRQ1 0x34E0 0x26 M0G3506QRHBRQ1 0xEE12 0xFC M0G3507QRGZRQ1 0x34E0 0xC5 M0G3506QRGERQ1 0xEE12 0xD8 M0G3507QSPTRQ1 0x34E0 0xE3 M0G3506QDGS28RQ1 0xEE12 0x71 M0G3507QRHBRQ1 0x34E0 0xAC M0G3505QPMRQ1 0x704E 0x7B M0G3507QRGERQ1 0x34E0 0xB1 M0G3505QRGZRQ1 0x704E 0xC9 M0G3507QDGS28RQ1 0x34E0 0xEA M0G3505QPTRQ1 0x704E 0x9C M0G3506QPMRQ1 0xEE12 0x7B M0G3505QRHBRQ1 0x704E 0x26 M0G3506QRGZRQ1 0xEE12 0xD2 M0G3505QRGERQ1 0x704E 0x3C M0G3506QPTRQ1 0xEE12 0x5A M0G3505QDGS28RQ1 0x704E 0x4C
8.35 Identification
Revision and Device Identification The hardware revision and device identification values are stored in the memory-mapped FACTORY region, refer to Device Factory Constants section, which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. Refer to Factory Constants chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for more information. The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 10.4) MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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9 Applications, Implementation, and Layout
9.1 Typical Application
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1.1 Schematic
TI recommends connecting a combination of a 10-µF and a 0.1-µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing these capacitors as close as possible to the supply pins that they decouple (within a few millimeters) to achieve a minimal loop area. The 10-µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance can be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time. The NRST reset pin must be pulled up to VDD (supply level) for the device to release from RESET state and start the boot process. TI recommends connecting an external 47-k Ω pullup resistor with a 10-nF pulldown capacitor for most applications, enabling the NRST pin to be controlled by another device or a debug probe. The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-k Ω with 0.1% tolerance resistor with a temperature coefficient (TCR) of 25ppm/C or better populated between the ROSC pin and VSS. This resistor establishes a reference current to stabilize the SYSOSC frequency through a correction loop. This resistor is required if the FCL feature is used for higher accuracy, and it is not required if the SYSOSC FCL is not enabled. When the FCL mode is not used, the PA2 pin can be used as a digital input/output pin. A 0.47-µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the VCORE pin. For the 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high for I2C and UART functions, as the open drain IO only implement a low-side NMOS driver and no high-side PMOS driver. The 5-V-tolerant open drain IOs are fail-safe and can have a voltage present even if VDD is not supplied. 0.1 F10 F 1.62 - 3.6 V ROSC 100 k ±0.1% ±25ppm 10nF NRST 0.47 F VDD VSS VCORE NRST MSPM0 MCU 47 k SWDIO SWCLK Debug interface 5V-tolerant open drain pins Pull-up resistors are required for output high PA0 PA1 Debug tool PU PU 1.62 - 5.5 V PA2/ROSC The NRST pullup resistor and capacitor are optional, but NRST must be pulled high to VDD for the device to start. Figure 9-1. Basic Application Schematic www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.
10.1 Getting Started and Next Steps
For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help with development, visit the Texas Instruments Arm Cortex-M0+ MCUs page.
10.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices and support tools. . Each MSP MCU commercial family member has one of two prefixes: MSP or X. These prefixes represent evolutionary stages of product development from engineering prototypes (X) through fully qualified production devices (MSP). X – Experimental device that is not necessarily representative of the final device's electrical specifications MSP – Fully qualified production device X devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device name. M0 G 350 7 Q RHB R Q1 MCU Platform Product Family Device Subfamily Flash Memory Temperature range Package Type Distribution Format Qualified for Automotive Figure 10-1. Device Nomenclature Table 10-1. Device Nomenclature Processor Family MSP = Mixed-signal processor X= Experimental silicon MCU Platform M0 = Arm based 32-bit M0+ Product Family G = 80-MHz frequency Device Subfamily 350 = CAN-FD, 2x ADC, 2x OPA, 3x COMP Flash Memory 5 = 32KB 6 = 64KB 7 = 128KB Temperature Range Q = –40°C to 125°C, AEC-Q100 qualified Package Type See the Device Comparison section and https://www.ti.com/packaging MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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Table 10-1. Device Nomenclature (continued) Distribution Format R = Large reel For orderable part numbers of MSP devices in different package types, see the Package Option Addendum of this document, ti.com, or contact your TI sales representative.
10.3 Tools and Software
Design Kits and Evaluation Modules MSPM0 LaunchPad (LP) Boards: LP-MSPM0G3507 Empowers you to immediately start developing on the industry’s best integrated analog and most cost-optimized general purpose MSPM0 MCU family. Exposes all device pins and functionality; includes some built-in circuitry, out-of-box software demos, and on-board XDS110 debug probe for programming/debugging/ EnergyTrace. The LP ecosystem includes dozens of BoosterPack stackable plug-in modules to extend functionality. Embedded Software MSPM0 Software Development Kit (SDK) Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. Software Development Tools TI Developer Zone Start your evaluation and development on a web browser without any installation. Cloud tools also have a downloadable, offline version. TI Resource Explorer Online portal to TI SDKs. Accessible in CCS IDE or in TI Cloud Tools. SysConfig Intuitive GUI to configure device and peripherals, resolve system conflicts, generate configuration code, and automate pin mux settings. Accessible in CCS IDE ,in TI Cloud Tools or a standalone version. (offline version) MSP Academy Great starting point for all developers to learn about the MSPM0 MCU Platform with training modules that span a wide range of topics. Part of TIRex. GUI Composer GUIs that simplify evaluation of certain MSPM0 features, such as configuring and monitoring a fully integrated analog signal chain without any code needed. IDE & compiler toolchains Code Composer Studio™ (CCS) Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications. CCS is completely free to use and is available on Eclipse and Theia frameworks. IAR Embedded Workbench® IDE IAR Embedded Workbench for Arm delivers a complete development toolchain for building and debugging embedded applications for MSPM0.The included IAR C/C++ Compiler generates highly optimized code for your application, and the C-SPY Debugger is a fully integrated debugger for source and disassembly level debugging with support for complex code and data breakpoint. Keil® MDK IDE Arm Keil MDK is a complete debugger and C/C++ compiler toolchain for building and debugging embedded applications for MSPM0.Keil MDK includes a fully integrated debugger for source and disassembly level debugging. MDK provides full CMSIS compliance. TI Arm-Clang TI Arm Clang is included in the Code Composer Studio IDE. GNU Arm Embedded Toolchain The MSPM0 SDK supports development using the open-source Arm GNU Toolchain. Arm GCC is supported by Code Composer Studio IDE (CCS). www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The following documents describe the MSPM0 MCUs. Copies of these documents are available on the Internet at www.ti.com. Technical Reference Manual MSPM0 G-Series 80- MHz Microcontrollers Technical Reference Manual This manual describes the modules and peripherals of the MSPM0G family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals can differ in their exact implementation on different devices. Pin functions, internal signal connections, and operational parameters differ from device to device. See the device-specific data sheet for these details.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
LaunchPad™, Code Composer Studio™, and TI E2E™ are trademarks of Texas Instruments. Arm® and Cortex® are registered trademarks of Arm Limited. All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 www.ti.com ADVANCE INFORMATION
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2023 * Initial Release www.ti.com MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1 SLASF88 – OCTOBER 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
www.ti.com 25-Oct-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples XM0G3507QRGERQ1 ACTIVE VQFN RGE 24 3000 TBD Call TI Call TI -40 to 125 Samples XM0G3507QRHBRQ1 ACTIVE VQFN RHB 32 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 25-Oct-2023 OTHER QUALIFIED VERSIONS OF MSPM0G3507-Q1 :
- Catalog : MSPM0G3507 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product Addendum-Page 2
Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4204104/H
www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRHB 32 PLASTIC QUAD FLATPACK - NO LEAD5 x 5, 0.5 mm pitch 4224745/A
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