TPS63900 TI1 | Alldatasheet
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ADVANCE□INFORMATION LX1 LX2 VIN VOUT GND VI 1.8 V to 5.5 V VO 1.8 V to 5.0 V 2.2 µH CFG3 10 µF 22 µFSEL EN CFG2 CFG1 TPS63900 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS63900 SLVSET3A –MARCH 2020–REVISED APRIL 2020 TPS639001.8-Vto5.5-V,400-mA,200-nAQuiescentCurrentBuck-BoostConverter
1 Features
1• Input voltage range: 1.8 V to 5.5 V
- Output voltage range: 1.8 V to 5 V (100-mV steps) – Programmable with external resistors – SEL pin to toggle between two output voltage presets
- > 400-mA output current for VI ≥ 1.8 V, VO = 3.3 V (typical 1.9-A peak switching current limit)
- > 90% Efficiency at 10-µA load current – 200-nA operating quiescent current – 60-nA shutdown current
- Single-mode operation – Eliminates mode transitions between buck, buck-boost and boost operation – Low output ripple – Excellent transient performance
- Safety and robust operation features – Integrated soft start – Programmable input current limit with eight settings (1 mA to 100 mA and unlimited) – Output short-circuit and overtemperature protection
- Tiny solution size – Small 2.2 µH inductor, single 22-µF output capacitor – 10-Pin, 2.5-mm × 2.5-mm, 0.5-mm pitch WSON package
2 Applications
- Smart meters and sensor nodes
- Electronic smart locks
- Medical sensor patches and patient monitors
- Wearable electronics
- Asset tracking
- Industrial IoT (smart sensors) / NB-IoT
3 Description
The TPS63900 device is a high-efficiency synchronous buck-boost converter with an extremely low quiescent current (200 nA typical). The device has 32 user-programmable output voltage settings from 1.8 V to 5 V. A dynamic voltage-scaling feature lets applications switch between two output voltages during operation; for example, to save power by using a lower system supply voltage during standby operation. With its wide supply voltage range and programmable input current limit (1 mA to 10 mA and unlimited), the device is ideal for use with a wide range of primary like 3S Alkaline, 1S Li-MnO2 or 1S Li-SOCl2, and secondary battery types. The high-output current capability supports commonly-used RF standards like sub-1-GHz, BLE, LoRa, wM-Bus, and NB-IoT. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS63900 WSON (10) 2.5 mm × 2.5 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic
ADVANCE□INFORMATION TPS63900 SLVSET3A –MARCH 2020–REVISED APRIL 2020 www.ti.com Product Folder Links: TPS63900 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Table of Contents
11.3 Receiving Notification of Documentation Updates 25
12 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (March 2020) to Revision A Page
ADVANCE□INFORMATION 1EN 10 VIN 2SEL 9 LX1 3CFG1 8 GND 4CFG2 7 LX2 5CFG3 6 VOUT Not to scale Thermal Pad TPS63900 www.ti.com SLVSET3A –MARCH 2020–REVISED APRIL 2020 Product Folder Links: TPS63900 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated
5 Pin Configuration and Functions
NO. NAME 1 EN I Device enable. A high level applied to this pin enables the device and a low level disables it. It must not be left open. 2 SEL I Output voltage select. Selects VO(2) when a high level is applied to this pin. Selects VO(1) when a low level is applied to this pin. It must not be left open. 3 CFG1 I Configuration pin 1. Connect a resistor between this pin and ground to set VO(2) and input current limit, must not be left open. 4 CFG2 I Configuration pin 2. Connect a resistor between this pin and ground to set VO(2) and input current limit. Must not be left open. 5 CFG3 I Configuration pin 3. Connect a resistor between this pin and ground to set VO(1). Must not be left open.
6 VOUT — Output voltage
7 LX2 — Switching node of the boost stage
8 GND — Ground
9 LX1 — Switching node of the buck stage
10 VIN — Supply voltage
— Thermal Pad — Connect this pin to ground for correct operation.
ADVANCE□INFORMATION TPS63900 SLVSET3A –MARCH 2020–REVISED APRIL 2020 www.ti.com Product Folder Links: TPS63900 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal, unless otherwise noted.
6 Specifications
The pre-production samples with XPS63900DSKT orderable part number (top marking: X639) have a silicon issue which causes leakage of around 300 µA in normal operation. This leads to a reduced efficiency at light loads. Quiescent current into VIN measurements on the pre-production silicon parts show 200 nA typical, if VO is forced to 5 V. The root cause of this leakage is understood and will be fixed for production units. All other functions of the converter can be evaluated. Production unit samples will be available in 3Q20. For detailed information, contact bcs_request_fs@list.ti.com.
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)(1) MIN MAX UNIT VI Input voltage (VIN, LX1, LX2, VOUT, EN, CFG1, CFG2, CFG3, SEL)(2) –0.3 5.9 V TJ Operating junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 VCharged-device model (CDM), per JEDEC specification JESD22-C101 or ANSI/ESDA/JEDEC JS-002(2) ±500 (1) Effective capacitance after DC bias effects have been considered.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VI Supply voltage 1.8 5.5 V VO Output voltage 1.8 5.0 V IO Output current (VI ≥ 1.8 V, VO = 3.6 V) 0.4 A CI Input capacitance (VI = 2.5 V to 5 V, VO = 3.3 V, IO = 0.4 A)(1) 5 µF CO Output capacitance (VI = 2.5 V to 5 V, VO = 3.3 V, IO = 0.4 A)(1) 10 µF C(CFG) Capacitance (CFG1, CFG2, CFG3) 10 pF L Inductance 2.2 µH ISAT Inductor saturation current rating Unlimited current setting 2 A ≤100-mA current settings 1 TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C
ADVANCE□INFORMATION TPS63900 www.ti.com SLVSET3A –MARCH 2020–REVISED APRIL 2020 Product Folder Links: TPS63900 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1) TPS63900 (WSON)
10 PINS
RθJA Junction-to-ambient thermal resistance 64.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 62.3 °C/W RθJB Junction-to-board thermal resistance 31.1 °C/W ψJT Junction-to-top characterization parameter 1.6 °C/W ψJB Junction-to-board characterization parameter 31.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 10.0 °C/W
6.5 Electrical Characteristics
Over operating junction temperature range and recommended supply voltage range (unless otherwise noted). Typical values are at VI = 3.0 V, VO = 2.5 V and TJ = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY Quiescent current into VIN V(EN) = 3 V, no load, not switching, "unlimited" current setting 0.2 1 µA Shutdown current into VIN V(EN) = 0 V 60 nA VIT+(UVLO) Positive-going UVLO threshold voltage 1.73 1.75 1.77 V Vhys(UVLO) UVLO threshold voltage hysteresis 90 100 110 mV I/O SIGNALS VIH High-level input voltage (EN, SEL) 1.2 V VIL Low-level input voltage (EN, SEL) 0.4 V Input current (EN, SEL) V(EN), V(SEL) = 1.8 V or 0 V. TJ = 25°C ±1 ±10 nA POWER SWITCH rDS(on) On-state resistance VI = 3 V, VO = 3.6 V, test current = 1 A 110 mΩ Q2 105 Q3 105 Q4 110 CURRENT LIMIT Peak current limit during Startup (Q1) VI = 3.6 V, unlimited current limit setting 0.48 0.83 A Peak current limit (Q1) VI = 1.8 V, VO = 3.6 V, unlimited current limit setting 1.33 2.1 2.47 A VI = 3.6 V, VO = 3.3 V, 100-mA current limit setting 0.15 0.4 0.51 Average input current limit TJ = –40°C to 85°C 1-mA setting 1 mA 2.5-mA setting 2.5 5-mA setting 5 10-mA settting 10 25-mA setting 25 50-mA setting 50 100-mA setting 100 OUTPUT Output voltage DC accuracy IO = 1 mA, CO(eff) = 4 µF, L(eff) = 2.2 µH ±1.8 % CONTROL Internal reference resistor 33 kΩ
are at VI = 3.0 V, VO = 2.5 V and TJ = 25°C (unless otherwise noted).
6.6 Typical Characteristics
Figure 1. Quiescent Current versus Input Voltage Figure 2. Shutdown Current versus Input Voltage
ADVANCE□INFORMATION UVLO Reference Voltage R2D Interface Control BlocktVreft VIN LX2 LX1 EN SEL CFG1 CFG2 CFG3 & Enable (to all blocks) State Machine VOUT tIL(PEAK)t Attenuator Power Stage Input Current Limit Output Voltage GND tNÂ9Ot tIL(VALLEY)t TPS63900 www.ti.com SLVSET3A –MARCH 2020–REVISED APRIL 2020 Product Folder Links: TPS63900 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TPS63900 device is a four-switch synchronous buck-boost converter with a maximum output current of 400 mA. It has a single-mode operation that allows the device to regulate the output voltage to a level above, below, or equal to the input voltage without displaying the mode-switching transients and unpredictable inductor current ripple from which many other buck-boost devices suffer. The switching frequency of the TPS63900 device varies with the operating conditions: it is lowest when IO is low and increases smoothly as IO increases.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Trapezoidal Current Control
Figure 3 shows a simplified block diagram of the power stage of the device. Inductor current is sensed in series with Q1 (the peak current) and Q4 (the valley current).
Figure 6. Inductor Current Waveform when VI < VO (CCM)
- VI is the input voltage
- VO is the output voltage
- tw(A) is the duration of phase A
- tw(B) is the duration of phase B
- tw(C) is the duration of phase C (1) By varying relative duration of each phase, the device can regulate VO to be less than, equal to, or greater than VI.
7.3.2 Device Enable / Disable
- The supply voltage is greater than the positive-going undervoltage lockout (UVLO) threshold.
- The EN pin is high. The device turns off when at least one of the following conditions is true:
- The supply voltage is less than the negative-going UVLO threshold.
- The EN pin is low. A complete state diagram is shown in Figure 16. After the device turns on, the internal reference system starts, then the trimming information and the CFG pins are read out. The device ignores any further changes to the CFG pins during device operation. Figure 7 shows the internal start-up sequence.
Figure 7. Internal Start-Up Sequence
7.3.3 Soft Start
start up behavior below VO = 1.8 V (see Soft Start - Pre-production material for details). and 500 µs elapsed when the input current limit is set to unlimited (see the Input Current Limit section). Afterwards, the output voltage ramps in a series of discrete steps (see Figure 8).
- When VO ≤ 1.8 V, peak current is limited to 500 mA typical for 500 µs.
- When VO > 1.8 V, each step is 100 mV high and has a duration of 125 µs. The total start-up time can be calculated with Equation 2. where
- tr(SS) is the rise time of the output voltage in milliseconds
- VO is the output voltage in volts (2) Figure 8 shows a typical start-up case.
Figure 8. Start-Up Behavior Figure 9 illustrates the start-up step size behavior.
7.3.4 Soft Start - Pre-production material
and 750 µs elapsed. Afterwards, the output voltage ramps in a series of discrete steps (see Figure 8).
- When VO ≤ 1.2 V, peak current is limited to 500 mA typical for 750 µs.
- When VO ≤ 1.8 V, each step is 200 mV high and has a duration of 125 µs.
- When VO > 1.8 V, each step is 100 mV high and has a duration of 125 µs. The total start-up time can be calculated with Equation 3. where
- tr(SS) is the rise time of the output voltage in milliseconds
- VO is the output voltage in volts (3) Figure 12 illustrates the start-up step size behavior.
Figure 12. Typical Soft-Start Ramp Step Size Table 2 shows the typical start-up time for a number of standard output voltages. Table 2. Typical Start-Up Times
2.5 V 2 ms
3.3 V 3 ms
7.3.5 Input Current Limit
- 1 mA
- 2.5 mA
- 5 mA
- 10 mA
- 25 mA
- 50 mA
- 100 mA
- Unlimited
3 CFG1
7.3.6 Dynamic Voltage Scaling
Figure 13. Dynamic Voltage Scaling with High Load Figure 14. Dynamic Voltage Scaling with Light Load
7.3.7 Device Configuration (Resistor-to-Digital Interface)
transfers the setting to an internal configuration register (see Figure 15).
- CFG1 and CFG2 set VO(2) level and the input current limit.
- CFG3 sets VO(1) level. To reduce power consumption, the device reads the value of the resistors connected to the configuration pins during start-up and then disables these pins. Once the device has started to operate, changes to the configuration pins have no effect.
Figure 15. Resistor-to-Digital Interface Block Diagram temperature coefficient of ±200 ppm or better.
resistors— including initial tolerance, temperature drift, and ageing— is less than ±3%. Table 3. Input Current Limit and Output Voltage (SEL = High) Settings
Table 3. Input Current Limit and Output Voltage (SEL = High) Settings (continued) Table 4. Output Voltage (SEL Pin = Low) Settings
1.8 V 0 Ω
2.0 V 511 Ω
Table 4. Output Voltage (SEL Pin = Low)
7.3.8 SEL Pin
The SEL pin selects which configuration bits control the output voltage.
- When SEL = high, the output voltage VO(2) is set.
- When SEL = low, the output voltage VO(1) is set.
7.3.9 Short-Circuit Protection
7.3.9.1 Current Limit Setting = 'Unlimited'
after a delay of td(RESTART).
7.3.9.2 Current Limit Setting = 1 mA to 100 mA
7.3.10 Thermal Shutdown
starts with the soft-start feature (see the Soft Start section) and keeps the previously read CFG pin setting.
7.4 Device Functional Modes
Figure 16. Device Functional Modes
3.3 V, 400 mA
(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%. (2) Capacitance tolerance and DC bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%. (3) Typical application. Other check marks indicate possible filter combinations. (4) Only with input current limit active.
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.2 Typical Application
output capacitor is 22 µF (0603). Figure 17. 3.3 VOUT Typical Application
8.2.1 Design Requirements
Table 5. Matrix of Output Capacitor and Inductor Combinations
ADVANCE□INFORMATION PEAK Iout Vin DI = + η (1 D) 2 L /c180 /c180 /c45 /c180 /c180 f V - V INOUTDuty Cycle Boost D = VOUT TPS63900 SLVSET3A –MARCH 2020–REVISED APRIL 2020 www.ti.com Product Folder Links: TPS63900 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated
8.2.2 Detailed Design Procedure
The first step is the selection of the output filter components. To simplify this process, the Recommended Operating Conditions outlines minimum and maximum values for inductance and capacitance. Tolerance and derating must be taken into account when selecting nominal inductance and capacitance.
8.2.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the TPS63900 device with the WEBENCH® Power Designer. 1. Start by entering your VIN, VOUT and IOUT requirements. 2. Optimize your design for key parameters like efficiency, footprint or cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments. 3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability. 4. In most cases, you will also be able to: – Run electrical simulations to see important waveforms and circuit performance, – Run thermal simulations to understand the thermal performance of your board, – Export your customized schematic and layout into popular CAD formats, – Print PDF reports for the design, and share your design with colleagues. 5. Get more information about WEBENCH tools at www.ti.com/webench.
8.2.2.2 Inductor Selection
The inductor selection is affected by several parameters such as inductor ripple current, output voltage ripple, transition point into Power Save Mode, and efficiency. See Table 6 for typical inductors. For high efficiencies, the inductor must have a low DC resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the lower the core and conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for the inductor in steady state operation is calculated using Equation 6. Only the equation which defines the switch current in boost mode is shown, because this provides the highest value of current and represents the critical current value for selecting the right inductor. (5) (6) where:
- D = Duty Cycle in Boost mode
- f = Converter switching frequency
- L = Inductor value
- η = Estimated converter efficiency (use the number from the efficiency curves or 0.9 as an assumption) NOTE The calculation must be done for the minimum input voltage in boost mode. Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation current of the inductor needed. It is recommended to choose an inductor with a saturation current 20% higher than the value calculated using Equation 6. Possible inductors are listed in Table 6.
Table 6. List of Recommended Inductors (1)
8.2.2.3 Output Capacitor Selection
the VOUT and GND pins of the IC. There is no upper limit for the output capacitance value. Table 7. List of Recommended Capacitors(1)
8.2.2.4 Input Capacitor Selection
the ceramic bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 µF is a typical choice. Table 8. List of Recommended Capacitors(1)
8.2.2.5 Setting The Output Voltage
The output voltage is set with CFGx pins (see the Device Configuration (Resistor-to-Digital Interface) section).
(2) For other output voltages, refer to Table 5 for resistor values.
8.2.3 Application Curves
output capacitor is 22 µF (0603). Table 9. Components for Application Characteristic Curves for VOUT = 3.3 V(1)(2) Table 10. Typical Characteristics Curves
ADVANCE□INFORMATION TPS63900 www.ti.com SLVSET3A –MARCH 2020–REVISED APRIL 2020 Product Folder Links: TPS63900 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated
9 Power Supply Recommendations
The TPS63900 device is designed to operate with input supplies from 1.8 V to 5.5 V. The input supply must be stable and free of noise to achieve the full performance of the device. If the input supply is located more than a few centimeters away from the device, additional bulk capacitance can be required. The input capacitance shown in the application schematics in this data sheet is sufficient for typical applications.
10 Layout
10.1 Layout Guidelines
operation, load regulation problems, increased ripple and noise, and EMI issues.
- Place the input and output capacitors close to the device.
- Minimize the area of the input loop, and use short, wide traces on the top layer to connect the input capacitor to the VIN and GND pins.
- Minimize the area of the output loop, and use short, wide traces on the top layer to connect the output capacitor to the VOUT and GND pins.
- The location of the inductor on the PCB is less important than the location of the input and output capacitors. Place the inductor after the input and output capacitors have been placed close to the device. You can route the traces to the inductor on an inner layer if necessary.
10.2 Layout Example
Figure 28 shows an example of a PCB layout that follows the recommendations of the previous section. Figure 28. PCB Layout Example
ADVANCE□INFORMATION TPS63900 www.ti.com SLVSET3A –MARCH 2020–REVISED APRIL 2020 Product Folder Links: TPS63900 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following: Texas Instruments, TPS63900 EVM User Guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C 10X 0.3 0.2 2 0.1 10X 0.45 0.35 1.2 0.1 8X 0.5
0.8 MAX
0.05 0.00 B 2.6 2.4 A 2.6 2.4 (0.2) TYP WSON - 0.8 mm max heightDSK0010A PLASTIC SMALL OUTLINE - NO LEAD 4218903/A 01/2018 PIN 1 INDEX AREA SEATING PLANE 0.08 C (OPTIONAL) PIN 1 ID
0.1 C A B
0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000 ADVANCE□INFORMATION TPS63900 SLVSET3A –MARCH 2020–REVISED APRIL 2020 www.ti.com Product Folder Links: TPS63900 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
0.07 MAX
(1.2) 8X (0.5) (2.3) 10X (0.25) 10X (0.6) (2) (R0.05) TYP ( 0.2) VIA TYP (0.75) (0.35) WSON - 0.8 mm max heightDSK0010A PLASTIC SMALL OUTLINE - NO LEAD 4218903/A 01/2018 SYMM SYMM LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) ADVANCE□INFORMATION TPS63900 www.ti.com SLVSET3A –MARCH 2020–REVISED APRIL 2020 Product Folder Links: TPS63900 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated
www.ti.com EXAMPLE STENCIL DESIGN 10X (0.25) 10X (0.6) 8X (0.5) (0.89) (1.13) (2.3) (R0.05) TYP WSON - 0.8 mm max heightDSK0010A PLASTIC SMALL OUTLINE - NO LEAD 4218903/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. BASED ON 0.125 mm THICK STENCIL SOLDER PASTE EXAMPLE EXPOSED PAD 11 84% PRINTED SOLDER COVERAGE BY AREA SCALE:20X SYMM 5 6 SYMM METAL TYP ADVANCE□INFORMATION TPS63900 SLVSET3A –MARCH 2020–REVISED APRIL 2020 www.ti.com Product Folder Links: TPS63900 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated
www.ti.com 30-Apr-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS63900DSKR PREVIEW SON DSK 10 3000 TBD Call TI Call TI -40 to 85 TPS63900DSKT PREVIEW SON DSK 10 250 TBD Call TI Call TI -40 to 85 XPS63900DSKT ACTIVE SON DSK 10 250 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DSK 10 2.5 x 2.5 mm, 0.5 mm pitch WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4225304/A
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