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High Voltage, 1.2 MHz/600 kHz, 800 mA, Low Quiescent Current Buck Regulator Data Sheet ADP2370/ADP2371 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other ri ghts of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
FEATURES
Input voltage range: 3.2 V to 15 V, output current: 800 mA Quiescent current < 14 µA in power saving mode (PSM) >90% efficiency Force PWM pin (SYNC), 600 kHz/1.2 MHz frequency pin (FSEL) and adjustable option 100% duty cycle capability Initial accuracy: ±1% Low shutdown current: <1.2 µA Quick output discharge (QOD) option Synchronizable to an external clock 8-lead, 0.75 mm × 3 mm × 3 mm LFCSP (QFN) package Supported by ADIsimPower design tool
APPLICATIONS
Portable and battery-powered equipment Automatic meter readers (WSN) Point of sales and transaction processing instruments Medical instruments Medium format display tablets and pads TYPICAL APPLICATION CIRCUIT ADP2370/ ADP2371 FSEL EN POWER GOOD VOUT = 3.3V VIN = 6V CIN 10µF COUT 10µF AGND (EXPOSED PAD) VIN SYNC ON OFF 1.2MHz 600kHz SW PG PGND FB 09531-001 Figure 1. GENERAL DESCRIPTION The ADP2370/ADP2371 are high efficiency, low quiescent current, 800 mA buck (step-down) dc-to-dc converters in small 8-lead, 3 mm × 3 mm LFCSP (QFN) packages. The total solution requires only three tiny external components. The buck regulator uses a proprietary high speed current mode, constant frequency PWM control scheme for excellent stability and transient response. The need for an external rectifier is elimi- nated by using a high efficiency synchronous rectifier architecture. To ensure the longest battery life in portable applications, the ADP2370/ADP2371 employ a power saving variable frequency mode that reduces the switching frequency under light load conditions. The ADP2370/ADP2371 operate from input voltages of 3.2 V to 15 V allowing the use of multiple alkaline/NiMH, lithium cells, or other standard power sources. The ADP2370/ADP2371 offer multiple options for setting the operational frequency. The ADP2370/ADP2371 can be synchro- nized to a 600 kHz to 1.2 MHz external clock or it can be forced to operate at 600 kHz or 1.2 MHz via the FSEL pin. The ADP2370/ ADP2371 can be forced to operate in PWM mode (FPWM) when noise considerations are more important than efficiency. A power-good output is available to indicate when the output voltage is below 92% of its nominal value. The ADP2371 is identical to the ADP2370 except that the ADP2371 includes the addition of an integrated switched resistor, quick output discharge function (QOD) that auto- matically discharges the output when the device is disabled. Both devices include an internal power switch and a synchronous rectifier for minimal external part count and high efficiency. The ADP2370/ADP2371 also include internal soft start and internal compensation for ease of use. During a logic controlled shutdown, the input is disconnected from the output and the regulator draws less than 1.2 μA from the input source. Other key features include undervoltage lockout to prevent deep battery discharge and soft start to prevent input overcurrent at startup. Short-circuit protection and thermal over- load protection circuits prevent damage under adverse conditions. The ADP2370/ADP2371 each use one 0805 capacitor, one 1206 capacitor, and one 4 mm × 4 mm inductor. The total solution size is about 53 mm 2 resulting in a very small footprint solution to meet a variety of portable applications.
ADP2370/ADP2371 Data Sheet Rev. A | Page 2 of 32 TABLE OF CONTENTS
REVISION HISTORY
5/12—Rev. 0 to Rev. A Changed Voltage Range for SW to PGND and Ground Plane 4/12—Revision 0: Initial Version
Data Sheet ADP2370/ADP2371 Rev. A | Page 3 of 32 SPECIFICATIONS VIN = VOUT + 1 V or 3.2 V, whichever is greater, EN = VIN, IOUT = 100 mA, CIN = 10 μF, COUT = 10 µF, TA = 25°C for typical specifications, TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SUPPLY Input Voltage Range VIN 3.2 15 V Quiescent Current IQ-PSM FSEL = VIN, SYNC = 0 V, no load, device not switching 13.5 μA IQ-PWM FSEL = VIN, SYNC = VIN, no load, device not switching 725 μA ISW-PWM FSEL = VIN, SYNC = VIN, no load, device switching 5.7 mA Shutdown Current ISHUT EN = GND, TJ = −40°C to +85°C 1.2 3.5 μA FIXED OUTPUT Output Current IOUT 800 mA Fixed Output Accuracy VOUT Initial set point, IOUT = 250 mA, TJ = 25°C −1 +1 % IOUT = 250 mA −1.5 +1.5 % No load to full load, PWM mode −3 +3 % ADJUSTABLE OUTPUT Feedback Voltage VFB 0.8 V Feedback Voltage Accuracy VFB-TOL Initial set point, IOUT = 250 mA, TJ = 25°C −1 +1 % Output Voltage Range VOUT-ADJ No load to full load 0.8 14 V FIXED AND ADJUSTABLE OUTPUT Load Regulation ∆VOUT/∆IOUT No load to full load 0.125 %/A Line Regulation ∆VOUT/∆VIN IOUT = 250 mA 0.01 %/V Efficiency EFF IOUT = 250 mA, VIN = 7.2 V, VOUT = 3.3 V 92 % Overcurrent Frequency Foldback Threshold Rising OCFOLDBACK-RISE % of VOUT, VOUT rising 50 % Falling OCFOLDBACK-FAL L % of VOUT, VOUT falling 37.5 % PSM Threshold PSMTHRESHOLD VIN = 7.2 V, VOUT = 3.3 V 170 mA Feedback Pin Input Current Fixed IFB-FIXED Fixed output voltage model 2.5 μA Adjustable IFB-ADJUST Adjustable output voltage model 10 nA Minimum On Time ON-TIMEMIN VIN < 5.5 V 65 100 ns VIN > 5.5 V 40 60 ns Soft Start Time SSTIME When EN rises from 0 V to VIN, and VOUT = 0.9 × VOUT 350 μs Active Pull-Down Resistance (ADP2371) RPULL-DOWN 260 400 Ω POWER SWITCH P-Channel On Resistance RDSON-P VIN > 5.5 V, IOUT = 400 mA 400 mΩ VIN < 5.5 V, IOUT = 400 mA 500 mΩ N-Channel On Resistance RDSON-N VIN > 5.5 V, IOUT = 400 mA 280 mΩ VIN < 5.5 V, IOUT = 400 mA 400 mΩ Current Limit P-Channel ILIM-P Peak inductor current 1200 1300 mA N-Channel ILIM-N Peak inductor current 500 550 mA Leakage Current ILEAK-SW P-Channel 0.01 1 μA N-Channel 0.01 1 μA OSCILLATOR Oscillator Frequency fOSC FSEL = VIN, 3.2 V ≤ VIN ≤ 15 V 1.0 1.2 1.4 MHz FSEL = 0 V, 3.2 V ≤ VIN ≤ 15 V 500 600 700 kHz
ADP2370/ADP2371 Data Sheet Rev. A | Page 4 of 32 Parameter Symbol Test Conditions/Comments Min Typ Max Unit Frequency Synchronization Range fSYNC_RANGE FSEL = 0 V, 3.2 V ≤ VIN ≤ 15 V 400 800 kHz FSEL = VIN, 3.2 V ≤ VIN ≤ 15 V 0.8 1.6 MHz Synchronization Threshold High SYNCHIGH 3.2 V ≤ VIN ≤ 15 V 1.2 V Low SYNCLOW 3.2 V ≤ VIN ≤ 15 V 0.4 V Hysteresis SYNCHYS 3.2 V ≤ VIN ≤ 15 V 200 mV Typical Sync Duty Cycle Range SYNCDUTY VIN (1.2 MHz), 3.2 V ≤ VIN ≤ 5 V, FSEL = VIN 20 55 % VIN (1.2 MHz), 5 V ≤ VIN ≤ 15 V, FSEL = VIN 20 70 % SYNC Pin Leakage Current SYNCLKG SYNC = 0 V or SYNC = VIN 0.05 1 μA FSEL Threshold 3.2 V ≤ VIN ≤ 15 V High FESLHIGH 1 V Low FSELLOW 0.4 V Hysteresis FSELHYS 125 mV FSEL Pin Leakage Current FSELLKG FSEL = 0 V or FSEL = VIN 0.04 1 μA POWER GOOD (PG PIN) PG Threshold 3.2 V ≤ VIN ≤ 15 V Rising PGRISE 92 95 % Falling PGFAL L 82.5 87 % Hysteresis PGHYS 5 % PG Output Low PGLOW Pull-up current < 1 mA 0.3 V PG Delay Rising PGDELAYRISE VOUT crossing PG rising threshold, pull-up current < 1 mA 20 μs Falling PGDELAYF ALL VOUT crossing PG falling threshold, pull-up current < 1 mA 0.5 μs PG Leakage PGLKG 0.04 1 μA UNDERVOLTAGE LOCKOUT (UVLO) Input Voltage Rising UVLORISE 3.19 V Input Voltage Falling UVLOFAL L 2.80 V Hysteresis UVLOHYS 190 mV ENABLE INPUT STANDBY (EN PIN) 3.2 V ≤ VIN ≤ 15 V EN Input Logic V High ENSTBY-HIGH 1 Low ENSTBY-LOW 0.4 V Hysteresis ENSTBY-HYS 125 mV ENABLE INPUT PRECISION (EN PIN) 3.2 V ≤ VIN ≤ 15 V EN Input Logic High ENHIGH 1.135 1.2 1.26 V Low ENLOW 1.045 1.1 1.155 V Hysteresis ENHYS 100 mV EN Input Leakage Current IEN-LKG EN = VIN or GND 0.05 1 µA EN Input Delay Time TIEN-DLY For VOUT = 0 V to 0.1 × VOUT when EN rises from
0 V to VIN
70 μs THERMAL SHUTDOWN 3.2 V ≤ VIN ≤ 15 V Thermal Shutdown Threshold TSSD TJ rising 150 °C Thermal Shutdown Hysteresis TSSD-HYS 15 °C
Data Sheet ADP2370/ADP2371 Rev. A | Page 5 of 32 RECOMMENDED SPECIFICATIONS: CAPACITORS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit MINIMUM INPUT and OUTPUT CAPACITANCE1 CMIN TA = −40°C to +125°C 6.5 10 µF CAPACITOR ESR RESR TA = −40°C to +125°C 1 10 mΩ 1 The minimum input and output capacitance should be greater than 7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any buck.
The specified values of θJA are based on a 4-layer, 4 in. × 3 in. the Lead Frame Chip Scale Package (LFCSP). ronmental Conditions—Junction-to-Board. device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
4 SYNC
1 VIN
- THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE ENHANCES
2 FSEL
8 PGND
Figure 2. Pin Configuration Table 5. Pin Function Descriptions 2 FSEL Frequency Select. High = 1.2 MHz, low = 600 kHz. 3 EN Enable. Enable input with precision thresholds. PWM mode when it is held high. SYNC held low forces automatic PWM/PSM operation. 5 FB Feedback. This pin provides feedback from the output. 6 PG Power Good. PG is an open-drain output. 7 SW Switch. This pin serves as the connection from the power MOSFETs to the inductor. plane on the circuit board for proper operation.
Figure 71. Functional Block Diagram applications, the ADP2370/ADP2371 has a power saving mode. descriptions of the ADP2370/ADP2371 features. choosing an appropriate inductor value. comparator monitors the peak inductor current via the SW node.
ADP2370/ADP2371 Data Sheet Rev. A | Page 22 of 32 FEATURES DESCRIPTIONS PRECISION ENABLE The enable circuit of the ADP2370/ADP2371 minimizes the input current during shutdown and simultaneously provides an accurate enable threshold. When the enable input voltage is below 400 mV , the regulators are in shutdown mode and the supply current is typically 1.2 μA. As the enable input voltage rises above the standby enable threshold of 1.0 V , the internal bias currents and voltages are activated, turning on the precision enable circuitry. This allows the precision enable circuitry to detect accurately when the EN pin voltage exceeds the precision enable rising threshold of 1.2 V. FORCED PWM OR PWM/PSM SELECTION Connecting the SYNC pin to a voltage greater than 1.2 V forces the device to operate permanently in the PWM mode. This means that the ADP2370/ADP2371 continue to operate at a fixed fre- quency even when the output current is less than the PWM/PSM threshold. In PWM mode, the efficiency is lower compared to the PSM mode during light loads. The low-side NMOS remains on when the output current drops to less than zero thereby preventing the device from entering discontinuous conduction (DCC) mode. It is possible to switch from FPWM mode to the power-save mode during operation by pulling the SYNC pin low. The flexible configuration of the SYNC pin during operation of the device allows for efficient power management. Connecting the SYNC pin to a voltage less than 0.4 V allows the part to operate in either PWM or PSM modes, depending on the output current. Whenever the average output current goes below the PWM/PSM threshold, the ADP2370/ADP2371 enter PSM mode operation. During PSM mode the part operates with reduced switching frequency and with a minimal quiescent cur- rent to maintain high efficiency. The low-side NMOS turns off when the output current reaches zero, causing the part to operate in DCC mode. QUICK OUTPUT DISCHARGE (QOD) FUNCTION The ADP2371 includes an output discharge resistor that forces the output voltage to zero when the buck is disabled. This ensures that the output of the buck is always in a well-defined state, whether or not it is enabled. The ADP2370 does not include this output discharge function. SHORT-CIRCUIT PROTECTION The ADP2370/ADP2371 include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below 0.3 V , indicating the possibility of a hard short at the output, the switching frequency is reduced to 1/4 of the internal oscillator frequency. The reduction in the switching frequency gives more time for the inductor to dis- charge, preventing a runaway of output current. UNDERVOLTAGE LOCKOUT To protect against battery discharge, an undervoltage lockout (UVLO) circuit is incorporated into the ADP2370/ADP2371. When the input voltage drops below the UVLO threshold, the ADP2370/ADP2371 shuts down, and both the power switch and synchronous rectifier turn off. Once the input voltage rises above the UVLO threshold, the soft start period is initiated and the device is enabled. THERMAL PROTECTION In the event that the junction temperature on either the ADP2370 or ADP2371 rises above 150°C, the thermal shutdown protec- tion circuit turns off the regulator. Extreme junction temperature can be the result of high current operation, poor circuit board design, and/or high ambient temperature. A 20°C hysteresis is included in the protection circuit so that when a thermal shut- down occurs, the device does not return to operation until the on-chip temperature drops below 130°C. When exiting a thermal shutdown, soft start is initiated. SOFT START The ADP2370/ADP2371 have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high imped- ance power source is connected to the input of the converter. Typical soft start time is 350 μs. The ADP2370/ADP2371 are also capable of starting up into a precharged output capacitor. If soft start is invoked when the output capacitor charge is greater than zero, the device delays the start of switching until the internal soft start ramp reaches the corresponding FB voltage. This fea- ture prevents discharging the output capacitor at the beginning of soft start. CURRENT LIMIT The ADP2370/ADP2371 have protection circuitry that limits the direction and amount of current to 1200 mA that flows through the power switch and synchronous rectifier, cycle by cycle. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load. A negative current limit is provided by the ADP2370/ADP2371 to prevent an excessive reverse inductor current when the switching section sinks current from the load in forced continuous con- duction mode. Under negative current-limit conditions, both the high-side and low-side switches are disabled.
Data Sheet ADP2370/ADP2371 Rev. A | Page 25 of 32 APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL ADP2370/ADP2371 are supported by the ADIsimPower™ design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized for a specific design goal. The tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and parts count taking into consideration the operating conditions and limita- tions of the IC and all real external components. For more information about, and to obtain ADIsimPower design tools, visit www.analog.com/ADIsimPower. Users can also request an unpopulated board through the ADIsimPower tool. EXTERNAL COMPONENT SELECTION Table 6 and Table 7 list external component selections for the ADP2370/ADP2371 application circuit shown in Figure 82. The selection of components is dependent on the input voltage, output voltage, and load current requirements. Additionally, trade-offs among performance parameters, such as efficiency and transient response, are made by varying the choice of external components. SELECTING THE INDUCTOR The high frequency switching of the ADP2370/ADP2371 allows for the use of small surface-mount power inductors. The inductor value affects the transition from PWM to PSM, efficiency, output ripple, and current-limit values. Use the following equation to cal- culate the ideal inductance, which is derived from the inductor current slope compensation, for a given output voltage and switching frequency: SW OUT f VL × ×= 478 . 0 2 . 1 The ripple current is calculated as follows: IN OUT SW OUT L V V L f VI 1 where: fSW is the switching frequency in MHz (1.2 MHz typical). L is the inductor value in μH. The dc resistance (DCR) value of the selected inductor affects efficiency; however, a decrease in this value typically means an increase in root mean square (rms) losses in the core and skin. A minimum requirement of the dc current rating of the inductor is for it to be equal to the maximum load current plus half of the inductor current ripple, as shown by the following equation: )2() ( L MAXLOADPK II I ∆+= OUTPUT CAPACITOR Output capacitance is required to minimize the voltage overshoot, voltage undershoot, and the ripple voltage present on the output. Capacitors with low equivalent series resistance (ESR) values produce the lowest output ripple; therefore, use capacitors such as the X5R dielectric. Do not use Y5V and Z5U capacitors. Y5V and Z5U capacitors are unsuitable choices because of their large capacitance variation over temperature and their dc bias voltage changes. Because ESR is important, select the capacitor using the following equation: L RIPPLE COUT I VESR Δ≤ where: ESRCOUT is the ESR of the chosen capacitor. VRIPPLE is the peak-to-peak output voltage ripple. Use the following equations to determine the output capacitance: RIPPLESW IN OUT V L f RIPPLESW L OUT V f IC × × ∆≥ 8 Increasing the output capacitor value has no effect on stability and may reduce output ripple and enhance load transient response. When choosing the output capacitor value, it is important to account for the loss of capacitance due to output voltage dc bias. INPUT CAPACITOR An input capacitor is required to reduce input voltage ripple, input ripple current, and source impedance. Place the input capacitor as close as possible to the VIN pin. A low ESR X7R- or X5R-type capacitor is highly recommended to minimize the input voltage ripple. Use the following equation to determine the rms input current: IN OUTINOUT MAXLOADCIN V V V VI I )( ) ( IN OUTINOUT MAXLOAD V V V VIrmsI )( ) ( ADJUSTABLE OUTPUT VOLTAGE PROGRAMMING The ADP2370/ADP2371 feature an adjustable output voltage range from 0.8 V to 12 V . The output voltage is set by the ratio of two external resistors, R2 and R3, as shown in Figure 83. The device servos the output to maintain the voltage at the FB pin at 0.8 V , referenced to ground; the current in R2 is then equal to 0.8 V/R3 plus the FB pin bias current. The bias current of the FB pin, 10 nA at 25°C, flows through R2 into the FB pin. The output voltage is calculated using the equation VOUT = 0.8 V(1 + R2/R3) + (FBI-BIAS)(R2)
FB pin bias current of 10 nA at 25°C. sections, as well as Table 6 for more information. Efficiency is defined as the ratio of output power to input power. battery life in portable applications. perature and increases when the input voltage is less than 5.5 V. losses relate to the magnetic permeability of the core material. because of its low core losses and low EMI. gate, and then from the gate to ground. CGATE_P is the gate capacitance of the internal high-side switch. CGATE_N is the gate capacitance of the internal low-side switch. fSW is the switching frequency. twice for each switching cycle. tR is the rise time of the SW node. tF is the fall time of the SW node. The typical value for the rise and fall times, tR and tF, is 2 ns. Figure 82. Typical Application, 1.2 MHz, Fixed Output
Figure 83. Typical Application, 600 kHz, Adjustable Output Table 6. Inductors Table 7. 10 μF Capacitors
0.05 MAX
0.02 NOM
0.80 MAX
Figure 93. 8-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the property of their respective owners.