Power Management

XFL4020-102ME

International Rectifier

3A Highly Integrated SupIRBuck Single-Input Voltage, Synchronous Buck Regulator

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1 www.irf.com © 2012 International Rectifier August 1, 2013 3A Highly Integrated SupIRBuck® Single-Input Voltage, Synchronous Buck Regulator FEATURES DESCRIPTION  Single input voltage range from 5V to 21V  Wide Input voltage range from 1.0V to 21V with external VCC bias voltage  Output voltage from 0.6V to 0.86% of PVin  Enhanced line/load regulation with feedforward  Programmable switching frequency up to 1.5MHz  Three user selectable soft-start time options  Thermally compensated current limit with robust hiccup mode over current protection  Synchronization to an external clock  Precise reference voltage (0.6V+/-0.6%)  Open-drain PGood indication  Output over voltage protection  Enable Input with Under-Voltage Lockout (UVLO)  V CC Under-Voltage Lockout (UVLO)  Enhanced Pre-bias start-up  Integrated MOSFET drivers and Bootstrap Diode  Thermal shut-down  -40°C to 125°C operating junction temperature  3.5mm x 3.5mm PQFN package  Lead-free, Halogen-free and RoHS6 Compliant The IR3823 SupIRBuck ® is a 3A easy-to-use, fully integrated and highly efficient synchronous Buck regulator intended for Point-Of-Load (POL) applications. The IR3823 features programmable switching frequency from 300kHz to 1.5MHz, three selectable soft-start time options, and smooth synchronization to an external clock. The IR3823 uses voltage mode control employing a proprietary PWM modulator, allowing high control bandwidth and fast loop response with less output capacitors. The other important functions include thermally compensated over current protection, output over voltage protection and thermal shut-down, etc. The IR3823 is offered in a small 3.5mm x 3.5mm PQFN package with excellent thermal performance.

APPLICATIONS

 Computing Applications  Set Top Box Applications  Storage Applications  Data Center Applications  Telecom Applications  Distributed Point of Load Power Architectures

ORDERING INFORMATION

Base Part Number Package Type Standard Pack Orderable Part Number Form Quantity IR3823 PQFN 3.5 mm x 3.5 mm Tape and Reel 750 IR3823MTR1PBF IR3823 PQFN 3.5 mm x 3.5 mm Tape and Reel 4000 IR3823MTRPBF PBF – Lead Free TR/TR1 – Tape and Reel M – PQFN Package

3 www.irf.com © 2012 International Rectifier August 1, 2013 BLOCK DIAGRAM Fb Rt/Sync SW PGnd Enable VCC OC TSD HDin UVcc UVEN HDrv LDrv Vin SSOK 0.6V VREF SEQ POR POR UVcc Gnd OC OV OV Vin SS_Select Fb Vcc/ LDO_Out5.1V Internal LDO UVcc THERMAL SHUT DOWN FAULT CONTROL + E/A Comp VREF + CONTROL LOGIC 0.15V SOFT START UVEN POR OVER VOLTAGE FAULT POR VREF INTL_SS POR GATE DRIVE PVin LDin Boot VCCPORFAULT Over Current Protection PGood Figure 4: Simplified Block Diagram

4 www.irf.com © 2012 International Rectifier August 1, 2013 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 Fb Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. 2 SS_Select Soft start selection pin. Three user selectable soft start time is available: 1.5ms (SS_Select=Vcc), 3ms (SS_Select=Float), 6ms (SS_Select=Gnd) 3 Comp Output of the error amplifier. The loop compensation network should be connected between Comp and Fb pin. 4,9,13, 16 Gnd Analog ground for the intern al reference and the control circuitry.

5 Rt/Sync

Multi-function pin to set the switching frequency. The internal oscillator frequency is set with a resistor between this pin and Gnd. Or synchronization to an external clock by connecting this pin to the external clock signal through a diode. 6 PGood Open-drain power good indication pin. Conn ect a pull-up resistor from this pin to Vcc. 7 Vin Input of the Internal LDO. A 1.0µFceramic capacitor should be connected between this pin and PGnd. If an external Vcc voltage is used, this pin should be shorted to Vcc pin. 8 Vcc/LDO_Out Output of the internal LDO and optional input of an external biased supply voltage. A minimum 2.2µF ceramic capacitor is recommended between this pin and PGnd. 10 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system power ground plane. 11 SW Switch node. Connect this pin to the output inductor. 12 PVin Power stage input. 14 Boot Supply voltage for the high-side driver. A 100nF ceramic capacitor should be connected between this pin and SW pin. 15 Enable Enable pin to turn on/off the device. Connect this pin to PVin pin through a resistor divider to implement the input voltage UVLO.

5 www.irf.com © 2012 International Rectifier August 1, 2013 ABSOLUTE MAXIMUM RATINGS Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin, Vin to PGnd (Note 3) -0.3V to 25V Vcc/LDO_Out to PGnd (Note 3) -0.3V to 8V (Note 1) Boot to PGnd (Note 3) -0.3V to 33V SW to PGnd (Note 3) -0.3V to 25V (DC), -4V to 25V (AC, 100ns) Boot to SW -0.3V to VCC + 0.3V (Note 2) PGood, SS_Select to Gnd (Note 3) -0.3V to VCC + 0.3V (Note 2) Other Input/Output Pins to Gnd (Note 3) -0.3V to +3.9V PGnd to Gnd -0.3V to +0.3V THERMAL INFORMATION Junction to Ambient Thermal Resistance ƟjA 37.4 °C/W (Note 4) Junction to PCB Thermal Resistance Ɵj-PCB 10.1 °C/W Junction to Case Top Thermal Resistance Ɵj-CTop 120 °C/W Storage Temperature Range -55°C to 150°C Junction Temperature Range -40°C to 150°C Note 1: Vcc must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C Note 2: Must not exceed 8V Note 3: PGnd pin and Gnd pin are connected together. Note 4: ƟjA is for the test in still air with IRDC3823 evaluation board. The IRDC3823 uses a 4‐layer 2.6” x 2.2” FR4 PCB board. Each layer uses 2 oz. copper.

6 www.irf.com © 2012 International Rectifier August 1, 2013 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL MIN MAX UNITS Input Voltage Range with External Vcc (Note 5, Note 7) PVin 1.0 21 V Input Voltage Range with Internal LDO (Note 6, Note 7) V in, PVin 5.5 21 Supply Voltage Range (Note 6) VCC 4.5 7.5 Supply Voltage Range (Note 6) Boot to SW 4.5 7.5 Output Voltage Range V0 0.6 0.86 x PVin Output Current Range I 0 0 3 A Switching Frequency FS 300 1500 kHz Operating Junction Temperature T J -40 125 °C Note 5: Vin is connected to Vcc to bypass the internal LDO. Note 6: Vin is connected to PVin. For single‐rail applications with PVin=Vin= 4.5V‐5.5V, please refer to the application information in the section of Internal LDO and the section of Over Current Protection. Note 7: Maximum SW node voltage should not exceed 25V.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these s pecifications apply over, 5.5V < V in = PV in < 21V, 0°C < T J < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Stage Power Losses P LOSS PVin= Vin = 12V, Vo = 1.2V, Io = 3A, Fs = 1000kHz, L = 1.0uH, Note 8 0.6 W Top Switch RDS(ON) R DS(on)-T VBOOT -Vsw=5.1V,Io = 3A, Tj = 25°C 40 52 mΩ Bottom Switch RDS(ON) R DS(on)-B V cc = 5.1V, Io = 3A, Tj = 25°C 26 34 Bootstrap Diode Forward Voltage VD I(Boot) = 10mA 180 260 470 mV SW Leakage Current ISW VSW = 0V, Enable = 0V, VFB=1V 1 µA VSW = 0V, Enable = High, VFB=1V 1 µA Dead Band Time T D Note 8 12.5 ns Supply Current Vin Supply Current (standby) Iin(Standby) EN = Low, No Switching Vin=21V, PVin=0V 200 µA Vin Supply Current (dynamic) Iin(Dyn) EN = High, FSW =1000kHz, Vin = PVin = 16V 10 12.5 mA

7 www.irf.com © 2012 International Rectifier August 1, 2013 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these s pecifications apply over, 5.5V < V in = PV in < 21V, 0°C < T J < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC/LDO_Out Output Voltage Vcc Vin(min) = 5.5V, Io = 0-25mA CLOAD = 2.2uF 4.75 5.1 5.4 V LDO Dropout Voltage Vcc_drop Vin=4.7V, Io=15mA, CLOAD=2.2uF 0.4 V Short Circuit Current I short V in=7.3V, PVin=Float, Vcc=0V 70 mA Oscillator Rt Voltage V Rt 1.0 V Frequency Range F s Rt = 80.6kΩ 270 300 330 kHz Rt = 23.2kΩ 900 1000 1100 Rt = 15kΩ 1350 1500 1650 Ramp Amplitude V ramp Vin = 5.5V, Vin slew rate max = 1V/µs, Note 8 0.825 Vp-p Vin = 12V, Vin slew rate max = 1V/µs, Note 8 1.80 Vin = 21V, Vin slew rate max = 1V/µs, Note 8 3.15 Vin=Vcc=5V, For external Vcc operation, Note 8 0.75 Ramp Offset Note 8 0.16 V Minimum Pulse Width T min(ctrl) Note 8 60 ns Maximum Duty Cycle D max F s = 300kHz, Vin =PVin= 12V 86 % Fixed Off Time T off Note 8 200 250 ns Sync Frequency Range F sync 270 1650 kHz Sync Pulse Duration T sync 100 200 ns Sync Level Threshold High 3.0 V Low 0.6 V Error Amplifier Input Bias Current (VFB) I FB(E/A) -1 +1 µA Output Sink Current I sink(E/A) 0.4 0.85 1.2 mA Output Source Current I source(E/A) 4 7.5 11 mA Slew Rate SR Note 8 7 12 20 V/µs Gain-Bandwidth Product GBWP Note 8 20 30 40 MHz

8 www.irf.com © 2012 International Rectifier August 1, 2013 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these s pecifications apply over, 5.5V < V in = PV in < 21V, 0°C < T J < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Error Amplifier (Continued) DC Gain Gain Note 8 100 110 120 dB Maximum Output Voltage V max(E/A) 1.7 2.0 2.3 V Minimum Output Voltage V min(E/A) 100 mV Reference Voltage (VREF) Feedback Voltage V FB 0.6 V Accuracy Soft Start Soft Start Ramp Rate SS_Select=VCC 0.34 0.4 0.46 mV/µs SS_Select=Float 0.16 0.2 0.24 SS_Select=Gnd 0.085 0.1 0.115 SS_Select Input Bias Current SS_Select=Gnd 40 80 uA Power Good Power Good Turn on Threshold VPG (on) VFB rising 85 90 95 % V REF Power Good Lower Turn off Threshold VPG(lower) VFB falling 80 85 90 % V REF Power Good Turn on Delay TPG (ON)_D V FB rising, see VPG(on) 2.56 ms Power Good Upper Turn off Threshold VPG(upper) VFB rising 115 120 125 % V REF PGood Comparator Delay VFB < VPG(lower) or VFB > VPG(upper) 1 2 3.5 µs PGood Voltage Low PG(voltage) IPGood = -5mA 0.5 V Under-Voltage Lockout Vcc-Start Threshold V CC UVLO Start Vcc rising trip Level 3.9 4.1 4.3 V Vcc-Stop Threshold V CC UVLO Stop Vcc falling trip Level 3.6 3.8 4.0 V Enable-Start-Threshold Enable UVLO Start ramping up 1.14 1.2 1.26 V Enable-Stop-Threshold Enable UVLO Stop ramping down 0.95 1 1.05 Enable Leakage Current I EN_LK Enable = 3.3V 1 µA

9 www.irf.com © 2012 International Rectifier August 1, 2013 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these s pecifications apply over, 5.5V < V in = PV in < 21V, 0°C < T J < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Over-Voltage Protection OVP Trip Threshold OVP_V th V FB rising 115 120 125 % V REF OVP Comparator Delay T OVP_D 1 2 3.5 µs Over-Current Protection Current Limit I LIMIT T j = 25°C, VCC=5.1V 3.6 4.5 5.4 A Hiccup Blanking Time T BLK_Hiccup SS_Select = Vcc, Note 8 10 ms SS_Select = Float, Note 8 20 SS_Select = Gnd, Note 8 40 Over-Temperature Protection Thermal Shutdown Threshold Note 8 145 Hysteresis Note 8 20 Note 8: Guaranteed by design, but not tested in production. Note 9: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.

10 www.irf.com © 2012 International Rectifier August 1, 2013 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin=12V, VCC= Internal LDO, IO = 0A-3A, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N DCR (mΩ) SIZE (mm)

11 www.irf.com © 2012 International Rectifier August 1, 2013 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vin=VCC= External 5V, IO = 0A-3A, FS = 1000 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N DCR (mΩ) SIZE (mm)

12 www.irf.com © 2012 International Rectifier August 1, 2013 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin = VCC = 5V, IO = 0A-3A, FS = 1000 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N DCR (mΩ) SIZE (mm)

DESCRIPTION

The IR3823 SupIRBuck ® is a 3A easy-to-use, fully integrated and highly efficient synchronous Buck regulator intended for Point-Of-Load (POL) applications. It includes two IR HEXFETs with low R DS(on). The bottom FET has an integrated monolithic schottky diode in place of a conventional body diode. The IR3823 provides precisely regulated output voltage programmed via two external resistors from 0.6V to 0.86×V in. It uses voltage mode control employing a proprietary PWM modulator with input voltage feedforward. That provides excellent noise immunity, easy loop compensation design, and good line transient response. The IR3823 has an internal Low Dropout (LDO) Regulator, allowing single supply operation without resorting to an external bias supply voltage. To further improve the light load efficiency, the internal LDO can be bypassed by using an external bias supply. This mode allows the input bus voltage range extended down to 1.0V. The IR3823 features programmable switching frequency from 300kHz to 1.5MHz, three selectable soft-start time, and smooth synchronization to an external clock. The other important functions include thermally compensated ov er current protection, output over voltage protection, pre-bias start-up, enable with input voltage monitoring, PGood output and thermal shut-down. VOLTAGE LOOP COMPESNATION DESIGN The IR3823 uses PWM voltage mode control. The output voltage of the POL, sensed by a resistor divider, is fed into an internal Error Amplifier (E/A). The output of the E/R is then compared to an internal ramp voltage to determine the pulse width of the gate signal for the control FET. The amplitude of the ramp voltage is proportional to V in so that the bandwidth of the voltage loop remains almost constant for different input voltages. This feature is called input voltage feedfoward. It allows the feedback loop design independent of the input voltage. Please refer to the next section for more information. A RC network has to be connected between the FB pin and the COMP pin to form a feedback compensator. The goal of the compensator design is to achieve a high control bandwidth with a phase margin of 45° or above. The high control bandwidth is beneficial for the loop dynamic response, which helps to reduce the number of output capacitors, the PCB size and the cost. A phase margin of 45° or higher is desired to ensure the syst em stability. For most applications, a gain margin of -10dB or higher is preferred to accommodate component variations and to eliminate jittering/noise. The proprietary PWM modulator in IR3823 significantly reduces the PWM jittering, allowing the control bandwidth in the range of 1/10 th to 1/5th of the switching frequency. Two types of compensators are commonly used: Type II (PI) and Type III (PID), as shown in Figure 5. The selection of the compensation type is dependent on the ESR of the output capacitors. Electrolytic capacitors have relatively higher ESR. If the ESR pole is located at the frequency lower than the cross-over frequency, F C, the ESR pole will help to boost the phase margin. Thus a type II compensator can be used. For the output capacitors with lower ESR such as ceramic capacitors, type III compensation is often desired. (a) (b) Figure 5: Loop Compensator (a) Type II, (b) Type III

17 www.irf.com © 2012 International Rectifier August 1, 2013 Table 1 lists the compensation selection for different types of output capacitors. For more detailed design guideline of voltage loop compensation, please refer to the application note AN-1162, “ Compensation Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier ”. SupBuck design tool is also available at www.irf.com providing the reference design based on user’s design requirements. TABLE 1 RECOMMENDED COMPENSATION TYPE COMPENSATOR LOCATION OF CROSS-OVER FREQUENCY TYPE OF OUTPUT CAPACITORS Type II (PI) F LC<FESR<F0<FS/2 Electrolytic, POS-CAP, SP- CAP Type III-A (PID) F LC<F0<FESR<FS/2 POS-CAP, SP- CAP Type III-B (PID) F LC<F0<FS/2<FESR Ceramic FLC is the resonant frequency of the output LC filter. It is often referred to as double pole. oo LC CL F FESR is the ESR zero of the output capacitor. o ESR CESRF  2 F0 is the cross-over frequency of the closed voltage loop and FS is the switching frequency. INPUT VOLTAGE FEEDFORWARD Input voltage feedforward is an important feature, because it can keep the converter stable and preserve its load transient performance when V in varies in a large range. In IR3823, feedforward function is enabled when V in pin is connected to PVin pin and V in>5.5V. In this case, the internal low dropout (LDO) regulator is used. The PWM ramp amplitude (V ramp) is proportionally changed with V in to maintain the ratio V in/Vramp almost constant throughout V in variation range (as shown in Figure 6). Thus, the control loop bandwidth and phase margin can be maintained constant. Feed-forward function can also minimize impact on output voltage from fast V in change. The maximum V in slew rate is within 1V/µs. If an external bias voltage is used as V cc, V in pin should be connected to V cc/LDO_out pin instead of PVin pin. Then the feedforward function is disabled. The control loop compensation might need to be adjusted. Figure 6: Timing Diagram for Input Feedforward UNDER-VOLTAGE LOCKOUT AND POR The Under-Voltage Lockout (UVLO) circuit monitors the voltage of V CC/LDO_Output pin and the Enable pin. It assures that the MOSFET driver outputs remain off whenever either of these two signals is below the set thresholds. Normal operation resumes once both V CC/LDO_Output and En voltages rise above their thresholds. The POR (Power On Ready) signal is generated when all these signals reach the valid logic level (see system block diagram). When the POR is asserted, the soft start sequence starts (see soft start section). ENABLE/EXTERNAL PVIN MONITOR The IR3823 has an Enable function providing another level of flexibility for start-up. The Enable pin has a precise threshold, which is internally monitored by Under-Voltage Lockout (UVLO) circuit. If the voltage at Enable pin is below its UVLO threshold, both high-side and low-side FETs are off. When Enable pin is below its UVLO, Over-Voltage Protection (OVP) is disabled, and PGood stays low.

20 www.irf.com © 2012 International Rectifier August 1, 2013 The output starts in an asynchronous fashion and keeps the synchronous MOSFET (Sync FET) off until the first gate signal for control MOSFET (Ctrl FET) is generated. Figure 14 shows a typical Pre- Bias condition at start up. The gate signal of the control FET is determined by the loop compensator. The sync FET always starts with a narrow pulse width (12.5% of a switching period) and gradually increases its duty cycle with a step of 12.5% until it reaches the steady state value. The number of these startup pulses for each step is 16 and it’s internally programmed. Figure 15 show s the series of 16x8 startup pulses. It should be noted that during pre-bias start up, PGood is not active until the first gate signal for control FET is generated. Please refer to Power Good Section for more information. Figure 14: Pre-Bias start-up

16 End of

12.5% 25% 87.5% 16 ... ... ... ... Figure 15: Pre-Bias startup pulses SHUTDOWN IR3823 can be shut down by pulling the Enable pin below its 1.0V threshold. Both the high side and the low side drivers will be pulled low. OPERATING FREQUENCY The switching frequency can be programmed between 300kHz – 1200kHz by connecting an external resistor from Rt pin to Gnd. Rt can be calculated as follows. 953.0 19954  ts RF Where FS is in kHz, and Rt is in kΩ. Table 3 shows the different oscillator frequency and its corresponding Rt for easy reference. Table 3 Switching Frequency vs. Rt Rt (kΩ) FS (kHz) 80.6 300 60.4 400 48.7 500 39.2 600 34 700 29.4 800 26.1 900 23.2 1000 21 1100 19.1 1200 17.4 1300 16.2 1400 15 1500 OVER CURRENT PROTECTION The over current (OC) prot ection is performed by sensing current through the R DS(on) of the Synchronous MOSFET. This method enhances the converter’s efficiency, reduces cost by eliminating a current sense resistor and any layout related noise issues. The current limit is pre-set internally and is compensated according to the IC temperature. So at different ambient temperature, the over-current trip threshold remains almost constant. Detailed operation of OCP is explained as follows. Over Current Protection circuit senses the inductor current flowing through the Synchronous MOSFET closer to the valley point. OCP circuit samples this current for 40nsec typically after the rising edge of the PWM set pulse, which has a width of 12.5% of the switching period. The PWM pulse starts at the falling edge of the PWM set pulse. This makes valley current sense more robust as current is sensed close to the bottom of the inductor downward slope where transient and switching noise are lower and helps to prevent false tripping due to noise and transient. An OC condition is detected if the load current exceeds the threshold, the converter enters

24 www.irf.com © 2012 International Rectifier August 1, 2013 DESIGN EXAMPLE The following example is a typical application for IR3823. The application circuit is shown in Figure 26. PV in = Vin = 12V (±10%) Vo = 1.2V Io = 3A Peak-to-Peak Ripple Voltage = ±1% of Vo ∆Vo = ± 4% of Vo (for 30% Load Transient) Fs = 1MHz EXTERNAL PVIN MONITOR (INPUT UVLO) As explained in the section of Enable/External PV in monitor, the input voltage, PVin, can be monitored by connecting the Enable pin to PV in through a set of resistor divider. When PV in exceeds the desired voltage level such that the voltage at the Enable pin exceeds the Enable threshold, 1.2V, the IR3823 is turned on. The implementation of this function is shown in Figure 7. For a typical Enable threshold of V EN = 1.2 V 2.1 (min)  ENin VRR RPV ENin EN VPV VRR  (min) For the minimum input voltage PVin (min) = 9.2V, select R1=49.9kΩ, and R2=7.5kΩ. SWITCHING FREQUENCY For FS = 1MHz, select Rt = 23.2 kΩ, from Table 3. OUTPUT VOLTAGE SETTING Output voltage is set by the reference voltage and the external voltage divider connected to the FB pin. The FB pin is the inverting input of the error amplifier, which is internally referenced to 0.6V. The divider ratio is set to provide 0.6V at the FB pin when the output is at its desired value. The output voltage is defined by using the following equation: )1( F F REFo R RVV  RF1 and R F2 are the feedback resistor divider, as shown in Figure 23. For the selection of RF1 and RF2, please see feedback compensation section. Figure 23: The output voltage is programmed through a set of feedback resistor divider BOOTSTRAP CAPACITOR SELECTION To drive the Control FET, it is necessary to supply a gate voltage at least 4V greater than the voltage at the SW pin, which is connected to the source of the Control FET. This is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor, C1, as shown in Figure 24. The operation of the circuit is as follows: When the sync FET is turned on, the capacitor node connected to SW is pulled low. V CC starts to charge C1 through the internal bootstrap didoe. The voltage, V c, across the bootstrap capacitor C1 can be calculated as DCCC VVV  where V D is the forward voltage drop of the bootstrap diode. When the control FET turns on in the next cycle, the SW node voltage rises to the bus voltage, PV in. The voltage at the Boot pin becomes: DCCinBOOT VVPVV 

25 www.irf.com © 2012 International Rectifier August 1, 2013 A good quality ceramic capacitor of 0.1 μF with voltage rating of at least 25V is recommended for most applications. Figure 24: Bootstrap circuit to generate the supply voltage for the high-side driver voltage INPUT CAPACITOR SELECTION Good quality input capacitors are necessary to minimize the input ripple voltage and to supply the switch current during the on-time. The input capacitors should be selected based on the RMS value of the input ripple current and requirement of the input ripple voltage. The RMS value of the input ripple current can be calculated as follows: )1( DDII oRMS  Where D is the duty cycle and I o is the output current. For Io=6A and D=0.1, IRMS= 0.9A The input voltage ripple is t he result of the charging of the input capacitors and the voltage induced by ESR and ESL of the input capacitors. Ceramic capacitors are recommended due to their high ripple current capabilities. They also feature low ESR and ESL at higher frequency which enables better efficiency. For this application, it is suggested to use two 10μF/25V ceramic capacitors, C3216X5R1E106M, from TDK. In addition, although not mandatory, a 1x100uF, 25V SMD capacitor EEE-1EA101XP from Panasonic may also be used as a bulk capacitor and is recommended if the input power supply is not located close to the converter. INDUCTOR SELECTION The inductor is selected based on output power, operating frequency and effi ciency requirements. A low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor ( ∆i). The optimum point is usually found between 20% and 50% ripple of the output current. The saturation current of the inductor is desired to be higher than the over current limit plus the inductor ripple current. An inducto r with soft-saturation characteristic is recommended. For the buck converter, t he inductor value for the desired operating ripple current can be determined using the following relation: t iLVPV L oin  max max ; sF Dt  sLin o oin FiV max max )( Where: PVinmax = Maximum input voltage V0 = Output Voltage ∆iLmax = Maximum Inductor Peak-to-Peak Ripple Current Fs = Switching Frequency ∆t = On time D = Duty Cycle Select ∆iLmax ≈ 36%×I o, then the output inductor is calculated to be 1.0 μH. Select L=1.0 μH, XFL4020- 102ME, from Coilcraft which provides a compact, low profile inductor suitable for this application. OUTPUT CAPACITOR SELECTION Output capacitors are usually selected to meet two specific requirements: (1 ) Output ripple voltage and

26 www.irf.com © 2012 International Rectifier August 1, 2013 (2) load transient response. The load transient response is also greatly affected by the control bandwidth. So it is common practice to select the output capacitors to meet the requirements of the output ripple voltage first, and then design the control bandwidth to meet the transient load response. For some cases, even with the highest allowable control bandwidth, the resulting load transient response still cannot meet the requirement. The number of output capacitors then need to be increased. The voltage ripple is attributed by the ripple current charging the output capacitors, and the voltage drop due to the Equivalent Series Resistance (ESR) and the Equivalent Series Inductance (ESL). Following lists the respective peak-to-peak ripple voltages: ESLL VPVV ESRiV FC iV oin ESLo LESRo so L Co    max)( max Where ∆iLmax is maximum inductor peak-to-peak ripple current. Good quality ceramic capacitors are recommended due to their low ESR, ESL and the small package size. It should be noted that the capacitance of ceramic capacitors are usually de-rated with the DC and AC biased voltage. It is important to use the de- rated capacitance value for the calculation of output ripple voltage as well as the voltage loop compensation design. The de-rated capacitance value may be obtained from the manufacturer’s datasheets. In this case, one 22uF ceramic capacitors, C2012X5R0J226M, from TDK are used to achieve ±12mV peak-to-peak ripple voltage requirement. The de-rated capacitance value with 1.2VDC bias and 10mVAC voltage is around 18uF each. FEEDBACK COMPENSATION For this design, the resonant frequency of the output LC filter, F LC, is kHz5.37 10181100.12   oo LC CL F The equivalent ESR zero of the output capacitors, FESR, is. kHz109.2 10181032    o ESR CESRF Designing crossover frequency at 1/5 th of switching frequency gives F0=200 kHz. According to Table 1, Ty pe III B compensation is selected for FLC<F0<FS/2<FESR. Type III compensator is shown below for easy reference. Figure 25: Type III compensation and its asymptotic gain plot

27 www.irf.com © 2012 International Rectifier August 1, 2013 As can be seen from Figure 25, Type III compensator contains two zeros and three poles. They can be calculated as follows. The zeros are: CC Z CRF   )(2 133 FFF Z The poles are: 01 PF FF P CRF   CC P CRF   Please note that the order of the zeros and poles do not necessarily follow the location shown in Figure 25. It can vary with the design preference. To archive the sufficient phase boost near the cross- over frequency, it is desired to place one zero and one pole as follows: kHz3570sin1 70sin110200sin1 sin1 3 0     FFZ kHz113470sin1 70sin110200sin1 sin1 3 0     FFP To compensate the phase lag of the pole at the origin and to provide extra phase boost, the other zero can be placed at one half of the first zero, i.e. 1/F Z = 17.5 kHz. The third pole is usually placed at one half of the switching frequency to damp the switching noise. The selected compensation parameters are: RF1=4.02kΩ, R F2=4.02kΩ, R F3=127Ω, C F3=2200pF, RC1=1.0kΩ, C C1=4.7nF, C C2=56pF. The resulting zeros and poles are listed in Table 4. Please note that one of high-frequency poles has been moved to 2843 kHz to increase the phase margin. Table 4 Zeros and Poles of the Voltage Loop Compensator Zeros Poles 34 kHz 17 kHz 0 570 kHz 2843 kHz

28 www.irf.com © 2012 International Rectifier July 18, 2013 APPLICATION DIAGRAM Figure 26: Single Rail 3A POL Application Circuit: PVin=Vin=12V, Vo=1.2V, Io=3A, fsw=1MHz SUGGESTED BILL OF MATERIALS QTY PART REFERENCE VALUE DESCRIPTION MANUFACTURER PART NUMBER

2 C in 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M

3 C7, C12, C24 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B

1 C11 56pF 0603, 50V, NP0, 5% TDK C1608C0G1H560J080AA

1 C out 22uF 0805, 6.3V, X5R, 20% TDK C2012X5R0J226M

1 C8 2200pF 0603,50V,X7R Murata GRM188R71H222KA01B

1 C23 2.2uF 0603, 16V, X5R, 20% TDK C1608X5R1C225M

1 C26 4700pF 0603, 50V 10% X7R Murata GRM188R71H472KA01D

1 C32 1.0uF 0603, 25V, X5R, 10% Murata GRM188R61E105KA12D 1 R1 1.0k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1001V 2 R2, R3 4.02k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4021V

1 R4 127 Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1270V

1 R9 23.2k Thick Film, 0603,1/10W Panasonic ERJ-3EKF2322V 2 R17, R18 49.9k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V 1 R19 7.5k Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF7501V 1 L 1.0uH SMD, 4.0mmx4.0mmx2.1mm, 10.8mΩ Coilcraft XFL4020-102ME 1 U1 IR3823 3A POL, PQFN 3.5mm x3.5mm IR IR3823

33 www.irf.com © 2012 International Rectifier August 1, 2013 TYPICAL OPERATING WAVEFORMS Vin = 12V, V0 = 1.2V, I0 = 0-3A, Unless otherwise Specified, SS_Select = Float. Room Temperature, No Air Flow Figure 40: Thermal Image of the board at 3A load, IR3823=45°C, Inductor=41.3°C

37 www.irf.com © 2012 International Rectifier August 1, 2013 PCB METAL AND COMPONENT PLACEMENT Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck ® Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132) Figure 45: PCB Metal Pad Spacing (all dimensions in mm) * Contact International Rectifier to receive an electronic PCB Library file in your preferred format

38 www.irf.com © 2012 International Rectifier August 1, 2013 SOLDER RESIST IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined (NSMD) or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip. Figure 46: Solder Resist

39 www.irf.com © 2012 International Rectifier August 1, 2013 STENCIL DESIGN Stencils for PQFN can be used with thicknesses of 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be adjusted for stencils of other thicknesses. Figure 47: Stencil Pad Spacing (all dimensions in mm)

PACKAGE INFORMATION

41 www.irf.com © 2012 International Rectifier August 1, 2013 ENVIRONMENTAL QUALIFICATIONS Qualification Level Industrial Moisture Sensitivity Level 3.5mm x 3.5mm PQFN JEDEC Level 2 @ 260°C ESD Machine Model (JESD22-A115A) Class B 200V to <400V Human Body Model (JESD22-A114F) Class 2 2000V to <4000V Charged Device Model (JESD22-C101D) Class III 500V to ≤1000V RoHS6 Compliant Yes † Qualification standards can be found at International Rectifier web site: http://www.irf.com †† Exceptions to AEC-Q101 requirements are noted in the qualification report. Data and specifications subject to change without notice. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com

Product Information

XFL4020-102ME specifications and overview.

Summary

3A Highly Integrated SupIRBuck Single-Input Voltage, Synchronous Buck Regulator

Description

3A Highly Integrated SupIRBuck Single-Input Voltage, Synchronous Buck Regulator

Source title XFL4020-102ME Datasheet(PDF) - International Rectifier

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