XCM1820IRTER

PCM1820 TI | Alldatasheet

Document overview

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Technical content

PCM182x Stereo Channel, 32-Bit, 192-kHz, Burr-BrownTM Audio ADC

1 Features

• Stereo high-performance ADC: – 2-channel analog microphones or line-in
• ADC line and microphone differential input performance: – PCM1820 dynamic range:
• 123-dB, dynamic range enhancer enabled
• 113-dB, dynamic range enhancer disabled – PCM1821 dynamic range: 106 dB – THD+N: –98 dB
• ADC differential 2-V RMS full-scale input
• ADC sample rate (f S) = 8 kHz to 192 kHz
• Hardware pin control configurations
• Linear-phase or low-latency filter selection
• Flexible audio serial data interface: – Master or slave interface selection – 32-bits, 2-channel TDM – 32-bits, 2-channel I 2S
• Automatic power-down upon loss of audio clocks
• Integrated high-performance audio PLL
• Single-supply operation: 3.3 V
• I/O-supply operation: 3.3 V or 1.8 V
• Power consumption for 3.3-V AVDD supply: – TBD mW/channel at 16-kHz sample rate – TBD mW/channel at 48-kHz sample rate

2 Applications

• Smart speakers
• DVD recorders and players
• AV receivers
• Video conference systems
• IP network cameras

3 Description

The PCM182x is a high-performance, Burr-Brown™ audio analog-to-digital converter (ADC) that supports simultaneous sampling of up to two analog channels. The device supports differential line and microphone inputs with a 2-V RMS full-scale signal. The device integrates a phase-locked loop (PLL), a DC removal high-pass filter (HPF), and supports sample rates up to 192 kHz. The device supports time-division multiplexing (TDM) or I 2S audio formats, selectable with the hardware pin level. Additionally, the PCM182x supports master and slave mode selection for the audio bus interface operation. These integrated high-performance features, along with the ability to be powered from a single supply of 3.3 V, make the device an excellent choice for cost- sensitive, space-constrained audio systems in far-field microphone recording applications. The PCM182x is specified from –40°C to +125°C, and is offered in a 20-pin WQFN package. Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) PCM182x WQFN (20) 3.00 mm × 3.00 mm with 0.5-mm pitch (1) For all available packages, see the package option addendum at the end of the data sheet. ADC Channel-1 Digital Decimation Filters with High Pass Filter (HPF) Audio Serial Interface (TDM, I2S) BCLK FSYNC SDOUT IN1M IN1P FMT0 M/SZ IN2M IN2P MD0 ADC Channel-2 Regulators, Current Bias and Voltage Reference AVSS AVDD IOVDD DREG VREF Thermal Pad (VSS) AREG Clock and Timing Controller with Integrated PLLMD1 Simplified Block Diagram www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 1 Product Folder Links: PCM1820 PCM1821 PCM1820, PCM1821 SBASA61 – DECEMBER 2020 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

7.7 Switching Characteristics: TDM, I2S or LJ

12.1 Receiving Notification of Documentation Updates..34

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES December 2020 * Initial Release PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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5 Device Comparison Table

FEATURE PCM1821 PCM1820 TLV320ADC3120 TLV320ADC5120 TLV320ADC6120 Control interface Pin control I2C Digital audio serial interface TDM or I2S TDM or I2S or left-justified (LJ) Audio analog channel 2 Digital microphone channel Not available 4 Programmable MICBIAS voltage NA Yes Dynamic range (DRE disabled) 106 dB 113 dB 106 dB 108 dB 113 dB Dynamic range (DRE enabled) Not available 123 dB Not available 120 dB 123 dB ADC SNR with DRE N/A 123 dB N/A 120 dB 123 dB CMRR TBD TBD TBD TBD TBD Input impedance 10 kΩ 2.5 kΩ 2.5 kΩ 10 kΩ 20 kΩ Compatibility Pin-to-pin, package, drop-in replacements of each other Pin-to-pin, package, and control registers compatible; drop-in replacements of each other Package WQFN (RTE), 20-pin, 3.00 mm × 3.00 mm (0.5-mm pitch) www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: PCM1820 PCM1821

6 Pin Configuration and Functions

18 VREF7BCLK

17 AREG8FSYNC

Thermal Pad (VSS) VSS20VSS

10 VSS

Figure 6-1. RTW Package, 24-Pin WQFN With Exposed Thermal Pad, Top View Table 6-1. Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN1P Analog input Analog input 1P pin. 2 IN1M Analog input Analog input 1M pin. 3 IN2P Analog input Analog input 2P pin. 4 IN2M Analog input Analog input 2M pin. 5 VSS Analog Supply Short this pin directly to the board ground plane. 6 SDOUT Digital output Audio serial data interface bus output. 7 BCLK Digital I/O Audio serial data interface bus bit clock. 8 FSYNC Digital I/O Audio serial data interface bus frame synchronization signal. 9 IOVDD Digital supply Digital I/O power supply (1.8 V or 3.3 V, nominal). 10 VSS Analog supply Short this pin directly to the board ground plane. 11 MD1 Digital input Device configuration mode select 1 pin. 12 MD0 Digital input Device configuration mode select 0 pin. 13 MSZ Digital input Audio interface bus master or slave select pin. 14 DREG Digital supply Digital regulator output voltage for digital core supply (1.5 V, nominal). 15 VSS Analog supply Short this pin directly to the board ground plane. 16 AVDD Analog supply Analog power (3.3 V, nominal). 17 AREG Analog supply Analog on-chip regulator output voltage for analog supply (1.8 V, nominal). 18 VREF Analog Analog reference voltage filter output. 19 FMT0 Digital input Audio interface format select pin referred to AVDD supply. 20 VSS Analog supply Short this pin directly to the board ground plane. Thermal Pad (VSS) Ground supply Thermal pad shorted to internal device ground. Short thermal pad directly to board ground plane. PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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7 Specifications

7.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage AVDD to AVSS –0.3 3.9 VAREG to AVSS –0.3 2.0 IOVDD to VSS (thermal pad) –0.3 3.9 Ground voltage differences AVSS to VSS (thermal pad) –0.3 0.3 V Analog input voltage Analog input pins voltage to AVSS –0.3 AVDD + 0.3 V Digital input voltage Digital input pins voltage to VSS (thermal pad) –0.3 IOVDD + 0.3 V Temperature Operating ambient, TA –40 125 °CJunction, TJ –40 150 Storage, Tstg –65 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

AVDD, AREG(1) Analog supply voltage AVDD to AVSS (AREG is generated using onchip regulator) - AVDD 3.3-V operation 3.0 3.3 3.6 V IOVDD IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation 3.0 3.3 3.6 V IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation 1.65 1.8 1.95 INPUTS Analog input pins and FMT0 voltage to VSS 0 AVDD V Digital input pins voltage(except FMT0) to VSS (thermal pad) 0 IOVDD V TEMPERATURE TA Operating ambient temperature –40 125 °C OTHERS Digital input pin used as MCLK input clock frequency 36.864 MHz CL Digital output load capacitance 20 50 pF (1) AVSS and VSS (thermal pad): all ground pins must be tied together and must not differ in voltage by more than 0.2 V. www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: PCM1820 PCM1821

7.4 Thermal Information

THERMAL METRIC(1) PCM182x UNITRTE (WQFN)

20 PINS

RθJA -High K Junction-to-ambient thermal resistance 55.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 33.1 °C/W RθJB Junction-to-board thermal resistance 23.4 °C/W ψJT Junction-to-top characterization parameter 0.6 °C/W ψJB Junction-to-board characterization parameter 23.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 16.7 °C/W (1) For more information about traditional and new thermal metrics, see the spra953 application report.

7.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC CONFIGURATION AC input impedance (PCM1820) Input pins INxP or INxM 2.5 kΩ AC input impedance (PCM1821) 10 kΩ PCM1820: ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION Differential input full- scale AC signal voltage AC-coupled input 2 VRMS SNR Signal-to-noise ratio, A- weighted(1) (2) IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = – 36 dB, DRE_MAXGAIN = 24 dB) 115 122 dB IN1 differential input selected and AC signal shorted to ground, DRE disabled 106 112 DR Dynamic range, A- weighted(2) IN1 differential input selected and –60-dB full- scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB) 123 dB IN1 differential input selected and –60-dB full- scale AC signal input, DRE disabled 113 THD+N Total harmonic distortion(2) (3) IN1 differential input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB) –98 –80 dB IN1 differential input selected and –1-dB full-scale AC signal input, DRE disabled –98 PCM1821: ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION Differential input full- scale AC signal voltage AC-coupled input 2 VRMS SNR Signal-to-noise ratio, A- weighted(1) (2) IN1 differential input selected and AC signal shorted to ground TBD 106 dB DR Dynamic range, A- weighted(1) (2) IN1 differential input selected and –60-dB full- scale AC signal input 106 dB IN1 differential input selected and –1-dB full-scale AC signal input –98 ADC OTHER PARAMETERS Output data sample rate 7.35 192 kHz PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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7.5 Electrical Characteristics (continued)

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output data sample word length 32 Bits Interchannel isolation –1-dB full-scale AC-signal input to non measurement channel –124 dB Interchannel gain mismatch –6-dB full-scale AC-signal input 0.1 dB Gain drift across temperature range 15°C to 35°C –4.4 ppm/°C Interchannel phase mismatch 1-kHz sinusoidal signal 0.02 Degrees Phase drift 1-kHz sinusoidal signal, across temperature range 15°C to 35°C 0.0005 Degrees/° C PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 102 dB CMRR Common-mode rejection ratio Differential microphone input selected, 100-mVPP, 1-kHz signal on both pins and measure level at output 60 dB DIGITAL I/O VIL Low-level digital input logic voltage threshold All digital pins except FMT0, IOVDD 1.8-V operation –0.3 0.30 × IOVDD V All digital pins except FMT0, IOVDD 3.3-V operation –0.3 0.8 FMT0 Pin –0.3 0.8 V VIH High-level digital input logic voltage threshold All digital pins except FMT0, IOVDD 1.8-V operation 0.7 × IOVDD IOVDD + 0.3 V All digital pins except FMT0, IOVDD 3.3-V operation 2.1 IOVDD + 0.3 FMT0 Pin 2.1 AVDD + 0.3 V VOL Low-level digital output voltage All digital pins, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V All digital pins, IOL = –2 mA, IOVDD 3.3-V operation 0.4 VOH High-level digital output voltage All digital pins, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V All digital pins, IOH = 2 mA, IOVDD 3.3-V operation 2.4 IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA IIL Input logic-low leakage for digital inputs All digital pins, input = 0 V –5 0.1 5 µA CIN Input capacitance for digital inputs All digital pins 5 pF RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ TYPICAL SUPPLY CURRENT CONSUMPTION IAVDD Current consumption with all Clocks Disabled AVDD = 3.3 V, internal AREG TBD µAIIOVDD All external clocks stopped, IOVDD = 3.3 V TBD IIOVDD All external clocks stopped, IOVDD = 1.8 V TBD www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: PCM1820 PCM1821

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IAVDD Current consumption with ADC 2-channel operating at fS 16-kHz, BCLK = 256 × fS and DRE disable AVDD = 3.3 V, internal AREG TBD mAIIOVDD IOVDD = 3.3 V TBD IIOVDD IOVDD = 1.8 V TBD IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, BCLK = 256 × fS and DRE disable AVDD = 3.3 V, internal AREG TBD mAIIOVDD IOVDD = 3.3 V TBD IIOVDD IOVDD = 1.8 V TBD IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, BCLK = 256 × fS and DRE enable AVDD = 3.3 V, internal AREG TBD mAIIOVDD IOVDD = 3.3 V TBD IIOVDD IOVDD = 1.8 V TBD (1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A- weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. (2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. (3) For best distortion performance, use input AC-coupling capacitors with low-voltage-coefficient. PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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7.6 Timing Requirements: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram MIN NOM MAX UNIT t(BCLK) BCLK period 40 ns tH(BCLK) BCLK high pulse duration (1) 18 ns tL(BCLK) BCLK low pulse duration (1) 18 ns tSU(FSYNC) FSYNC setup time 8 ns tHLD(FSYNC) FSYNC hold time 8 ns tr(BCLK) BCLK rise time 10% - 90% rise time 10 ns tf(BCLK) BCLK fall time 90% - 10% fall time 10 ns (1) The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

7.7 Switching Characteristics: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(SDOUT-BCLK) BCLK to SDOUT delay 50% of BCLK to 50% of SDOUT 18 ns td(SDOUT-FSYNC) FSYNC to SDOUT delay in TDM or LJ mode (for MSB data with TX_OFFSET = 0) 50% of FSYNC to 50% of SDOUT 18 ns f(BCLK) BCLK output clock frequency: master mode (1) 24.576 MHz tH(BCLK) BCLK high pulse duration: master mode 14 ns tL(BCLK) BCLK low pulse duration: master mode 14 ns td(FSYNC) BCLK to FSYNC delay: master mode 50% of BCLK to 50% of FSYNC 18 ns tr(BCLK) BCLK rise time: master mode 10% - 90% rise time 8 ns tf(BCLK) BCLK fall time: master mode 90% - 10% fall time 8 ns (1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data. www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: PCM1820 PCM1821

7.8 Typical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter Input Amplitude (dB) THD+N (dBFS) -130 -115 -100 -85 -70 -55 -40 -25 -10 0 -130 -120 -110 -100 -90 -80 -70 -60 THD+D001 Channel-1 Channel-2 Figure 7-1. PCM1820: THD+N vs Input Amplitude With DRE Enabled Input Amplitude (dB) THD+N (dBFS) -130 -115 -100 -85 -70 -55 -40 -25 -10 0 -130 -120 -110 -100 -90 -80 -70 -60 THD+D002 Channel-1 Channel-2 Figure 7-2. PCM1820: THD+N vs Input Amplitude With DRE Disabled Frequency (Hz) THD+N (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -130 -120 -110 -100 -90 -80 -70 -60 FreqD003 Channel-1 : DRE enabled Channel-2 : DRE enabled Figure 7-3. PCM1820: THD+N vs Input Frequency With a –60-dBr Input Frequency (Hz) THD+N (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -130 -120 -110 -100 -90 -80 -70 -60 D004 Channel-1 : DRE enabled Channel-2 : DRE enabled Figure 7-4. PCM1820: THD+N vs Input Frequency With a –60-dBr Input Frequency (Hz) THD+N (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -130 -120 -110 -100 -90 -80 -70 -60 D005 Channel-1 Channel-2 Figure 7-5. PCM1820: THD+N vs Input Frequency With a –1-dBr Input Frequency (Hz) Output Amplitude (dBFS) 20 30 50 70 100 200300 500 1000 2000 5000 10000 20000 100000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 FreqD006 Channel-1 Channel-2 Figure 7-6. PCM1820: Frequency Response With a –12-dBr Input PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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7.8 Typical Characteristics (continued)

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter Frequency (Hz) PSRR (dB) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -130 -120 -110 -100 -90 -80 -70 -60 D007 Channel-1 Channel-2 Figure 7-7. PCM1820: Power-Supply Rejection Ratio vs Ripple Frequency With a 100-mVPP Amplitude Frequency (Hz) Output Amplitude (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 D008 Channel-1 : DRE enabled Channel-2 : DRE enabled Figure 7-8. PCM1820: FFT With Idle Input and DRE Enabled Frequency (Hz) Output Amplitude (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 D009 Channel-1 : DRE disabled Channel-2 : DRE disabled Figure 7-9. PCM1820: FFT With Idle Input and DRE Disabled Frequency (Hz) Output Amplitude (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 D010 Channel-1 : DRE enabled Channel-2 : DRE enabled Figure 7-10. PCM1820: FFT With a –60-dBr Input and DRE Enabled Frequency (Hz) Output Amplitude (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 D011 Channel-1 : DRE disabled Channel-2 : DRE disabled Figure 7-11. PCM1820: FFT With a –60-dBr Input and DRE Disabled Frequency (Hz) Output Amplitude (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 D012 Channel-1 Channel-2 Figure 7-12. PCM1820: FFT With a –1-dBr Input www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: PCM1820 PCM1821

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter Input Amplitude (dB) THD+N (dBFS) -130 -115 -100 -85 -70 -55 -40 -25 -10 0 -130 -120 -110 -100 -90 -80 -70 -60 THD+D001 Channel-1 Channel-2 Figure 7-13. PCM1821: THD+N vs Input Amplitude Frequency (Hz) THD+N (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -130 -120 -110 -100 -90 -80 -70 -60 D002 Channel-1 Channel-2 Figure 7-14. PCM1821: THD+N vs Input Frequency With a –60-dBr Input Frequency (Hz) THD+N (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -130 -120 -110 -100 -90 -80 -70 -60 D003 Channel-1 Channel-2 Figure 7-15. PCM1821: THD+N vs Input Frequency With a –1-dBr Input Frequency (Hz) Output Amplitude (dBFS) 20 30 50 70 100 200300 500 1000 2000 5000 10000 20000 100000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 FreqD004 Channel-1 Channel-2 Figure 7-16. PCM1821: Frequency Response With a –12-dBr Input Frequency (Hz) PSRR (dB) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -130 -120 -110 -100 -90 -80 -70 -60 D005 Channel-1 Channel-2 Figure 7-17. PCM1821: Power-Supply Rejection Ratio vs Ripple Frequency With a 100-mVPP Amplitude Frequency (Hz) Output Amplitude (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 D006 Channel-1 Channel-2 Figure 7-18. PCM1821: FFT With Idle Input and DRE Disabled PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, DRE_LVL = –36 dB, channel gain = 0 dB, and linear phase decimation filter (unless otherwise noted); all performance measurements are done with a 20-kHz, low-pass filter, and an A-weighted filter Frequency (Hz) Output Amplitude (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 D007 Channel-1 Channel-2 Figure 7-19. PCM1821: FFT With a –60-dBr Input and DRE Enabled Frequency (Hz) Output Amplitude (dBFS) 20 30 4050 70 100 200 300 500 1000 2000 5000 10000 20000 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 D008 Channel-1 Channel-2 Figure 7-20. PCM1821: FFT With a –1-dBr Input www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: PCM1820 PCM1821

8 Detailed Description

8.1 Overview

The PCM182x is a high-performance, low-power, stereo-channel, audio analog-to-digital converter (ADC) with flexible audio interface control options. This device is intended for applications in voice-activated systems, AV receivers, tv and blu-ray players, professional microphones, audio conferencing, portable computing, communication, and entertainment applications. The high dynamic range of the device enables far-field audio recording with high fidelity. This device integrates a host of features that reduces cost, board space, and power consumption in space-constrained, battery-powered, consumer, home, and industrial applications. The device features are controlled through hardware by pulling pins high or low with resistors or a controller general-purpose inut/output (GPIO). The PCM182x also supports a power-down and reset function by means of halting the system clock. The PCM182x consists of the following blocks and features:

• Stereo-channel, multibit, high-performance delta-sigma (ΔΣ) ADC
• Differential audio inputs with a 2-V RMS full-scale signal
• Hardware pin control operation to select the device features
• Audio bus serial interface master or slave select option
• Audio bus serial interface format select option
• Slave mode supports the audio bus serial interface up to 192 kHz sampling
• Slave mode supports a dynamic range enhancer (DRE) with 123-dB dynamic range for the PCM1820
• Slave mode supports decimation filters with linear-phase or low-latency filter selection
• Master mode operation supported using a system clock of 256 × f S or 512 × fS
• Power-down function by means of halting the audio clocks
• Integrated high-pass filter (HPF) that removes the DC component of the input signal
• Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
• Integrated digital and analog voltage regulators to support single-supply, 3.3-V operation

8.2 Functional Block Diagram

Filter (HPF) Audio Serial Interface (TDM, I2S) BCLK FSYNC SDOUT IN1M IN1P FMT0 M/SZ IN2M IN2P MD0 ADC Channel-2 Regulators, Current Bias and Voltage Reference AVSS AVDD IOVDD DREG VREF Thermal Pad (VSS) AREG Clock and Timing Controller with Integrated PLLMD1 PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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8.3 Feature Description

8.3.1 Hardware Control

The device supports simple hardware-pin-controlled options to select a specific mode of operation and audio interface for a given system. The MSZ, MD0, MD1, and FMT0 pins allow the device to be controlled by either pullup or pulldown resistors.

8.3.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the PCM182x on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for the I 2S, and the pin-selectable master-slave configurability for bus clock lines. The device supports an audio bus master or slave mode of operation using the hardware pin MSZ. In slave mode, FSYNC and BCLK work as input pins whereas in master mode, FSYNC and BCLK work as output pins generated by the device. Table 8-1 shows the master and slave mode selection using the MSZ pin. Table 8-1. Master and Slave Mode Selection MSZ MASTER AND SLAVE SELECTION Low Slave mode of operation High Master ode of operation The bus protocol TDM or I 2S format can be selected by using the FMT0 pin. As shown in Table 8-2, these modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data format, with an output channel data word-length of 32 bits. Table 8-2. Audio Serial Interface Format FMT0 AUDIO SERIAL INTERFACE FORMAT Low 2-channel output with inter IC sound (I2S) mode High 2-channel output with time division multiplexing (TDM) mode

8.3.2.1 Time Division Multiplexed Audio (TDM) Interface

In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK. Figure 8-1 to Figure 8-4 illustrate the protocol timing for TDM operation with various configurations. 2 1 0N-1 N-2 N-1 N-2 N-3 2 1 0 N-1 N-2 N-3 2 1 0 Ch1 (Word Length : 32) Ch2 (Word Length : 32) Ch3 to Ch4 (Word Length : 32) 2 1 0N-1 N-2 Ch1 (Word Length : 32) FSYNC BCLK SDOUT nth Sample (n+1)th Sample Figure 8-1. TDM Mode Protocol Timing (FMT0 = LOW) In Slave Mode 2 1 0N-1 N-2 N-1 N-2 N-3 2 1 0 Ch1 (Word Length : 32) Ch2 (Word Length : 32) 2 1 0N-1 N-2 Ch1 (Word Length : 32) BCLK SDOUT nth Sample (n+1)th Sample FSYNC Figure 8-2. TDM Mode Protocol Timing (FMT0 = HIGH) In Slave Mode www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: PCM1820 PCM1821

2 1 0 N-1 N-2 N-3 2 1 0 N-1 N-2 N-3 1 0 Ch1 (Word Length : 32) Ch2 (Word Length : 32) Ch3 to Ch4 (Word Length : 32) 2 1 0 Ch1 (Word Length : 32) FSYNC BCLK SDOUT nth Sample ( 128 BCLK Cycles) (n+1)th Sample

0 N-1 N-2 N-3 N-1 N-2 N-3

Figure 8-3. TDM Mode Protocol Timing (FMT0 = LOW) In Master Mode 2 1 0 N-1 N-2 N-3 1 0 Ch1 (Word Length : 32) Ch2 (Word Length : 32) FSYNC BCLK SDOUT nth Sample (64 BCLK Cycles) (n+1)th Sample (64 BCLK Cycles) 0 2 1 0 N-1 N-2 N-3 1 N-10 Ch1 (Word Length : 32) Ch2 (Word Length : 32) N-1 N-2 N-3 N-1 N-2 N-3 Figure 8-4. TDM Mode Protocol Timing (FMT0 = HIGH) In Master Mode For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels times the 32-bits word length of the output channel data. The device transmits a zero data value on SDOUT for the extra unused bit clock cycles. The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well.

8.3.2.2 Inter IC Sound (I2S) Interface

The standard I2S protocol is defined for only two channels: left and right. In I 2S mode, the MSB of the left slot 0 is transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. The MSB of the right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. In master mode, FSYNC is transmitted on the rising edge of BCLK. Figure 8-5 and Figure 8-6 show the protocol timing for I 2S operation in slave and master mode of operation. 1 0N-1 N-2 1 0N-1 N-2 BCLK SDOUT nth Sample (n+1)th Sample 1 0N-1 FSYNC N-2 Left (Ch1) Slot-0 (Word Length : 32) Right (Ch2) Slot-0 (Word Length : 32) Left (Ch1) Slot-0 (Word Length : 32) Figure 8-5. I2S Mode Protocol Timing in Slave Mode 1 0N-1 N-2 BCLK SDOUT nth Sample (64 BCLK Cycles) (n+1) th Sample (64 BCLK Cycles) 1 0N-1 FSYNC N-21 0 1 0N-1 N-2 1 0N-1 N-2 Left (Ch1) Slot-0 (Word Length : 32) Right (Ch2) Slot-0 (Word Length : 32) Left (Ch1) Slot-0 (Word Length : 32) Right (Ch2) Slot-0 (Word Length : 32) Figure 8-6. I2S Protocol Timing In Master Mode PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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For proper operation of the audio bus in I 2S mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the 32-bits word length of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the 32-bits data word length. Similarly, the FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the 32- bits data word length. The device transmit zero data value on SDOUT for the extra unused bit clock cycles.

8.3.3 Phase-Locked Loop (PLL) and Clock Generation

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the ADC modulator and digital filter engine, as well as other control blocks. In slave mode of operation, the device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 8-3 and Table 8-4 list the supported FSYNC and BCLK frequencies. Table 8-3. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies BCLK TO FSYNC RATIO BCLK (MHz) FSYNC (8 kHz) FSYNC (16 kHz) FSYNC (24 kHz) FSYNC (32 kHz) FSYNC (48 kHz) FSYNC (96 kHz) FSYNC (192 kHz) Table 8-4. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies BCLK TO FSYNC RATIO BCLK (MHz) FSYNC (7.35 kHz) FSYNC (14.7 kHz) FSYNC (22.05 kHz) FSYNC (29.4 kHz) FSYNC (44.1 kHz) FSYNC (88.2 kHz) FSYNC (176.4 kHz) In the master mode of operation, the device uses the MD1 pin (as the system clock, MCLK) as the reference input clock source with a supported system clock frequency option of either 256 × f S or 512 × f S as configured using the MD0 pin. Master mode supports f S rates of 44.1 kHz and 48 kHz. Table 8-5 shows the system clock selection for the master mode using the MD0 pin. www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: PCM1820 PCM1821

Table 8-5. System Clock Selection for the Master Mode MD0 SYSTEM CLOCK SELECTION (Valid for Master Mode Only) LOW System clock with frequency 256 × fS connected to the MD1 pin as MCLK HIGH System clock with frequency 512 × fS connected to the MD1 pin as MCLK See Table 8-7 and Table 8-20 for the MD0 and MD1 pin function in the slave mode of operation.

8.3.4 Input Channel Configurations

The device consists of two pairs of analog input pins (INxP and INxM) as differential inputs for the recording channel. The device supports simultaneous recording of up to two channels using the high-performance stereo ADC. The input source for the analog pins can be from electret condenser analog microphones, micro electrical- mechanical system (MEMS) analog microphones, or line-in (auxiliary) inputs from the system board. The voice or audio signal inputs must be capacitively coupled (AC-coupled) to the device and, for best distortion performance, use the low-voltage coefficient capacitors for AC coupling. The typical input impedance for the PCM1820 is 2.5 k Ω for the INxP or INxM pins and 10 k Ω for the PCM1821. The value of the coupling capacitor in AC-coupled mode must be chosen so that the high-pass filter formed by the coupling capacitor and the input impedance do not affect the signal content. Before proper recording can begin, this coupling capacitor must be charged up to the common-mode voltage at power-up. To enable quick charging, the device has a quick charge scheme to speed up the charging of the coupling capacitor at power-up. The default value of the quick-charge timing is set for a coupling capacitor up to 1 µF.

8.3.5 Reference Voltage

All audio data converters require a DC reference voltage. The PCM182x achieves low-noise performance by internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap circuit with high PSRR performance. This audio converter reference voltage must be filtered externally using a minimum 1-µF capacitor connected from the VREF pin to analog ground (AVSS). The value of this reference voltage, VREF, is set to 2.75 V, which in turn supports a 2-V RMS differential full-scale input to the device. The required minimum AVDD voltage for this VREF voltage is 3 V. Do not connect any external load to a VREF pin.

8.3.6 Signal-Chain Processing

The PCM182x signal chain is comprised of very-low-noise, high-performance, and low-power analog blocks and highly flexible and programmable digital processing blocks. The high performance and flexibility combined with a compact package makes the PCM182x optimized for a variety of end-equipments and applications that require multichannel audio capture. Figure 8-7 shows a conceptual block diagram for the PCM1820 that highlights the various building blocks used in the signal chain, and how the blocks interact in the signal chain. The PCM1821 does not support DRE. DRE Amplifier ADC Configurable Decimation Filters HPFDRE INP INM Output Channel Data to Audio Bus Figure 8-7. Signal-Chain Processing Flowchart The front-end dynamic range enhancer (DRE) gain amplifier in the PCM1820 is very low noise, with a 123-dB dynamic range performance. Along with a low-noise and low-distortion, multibit, delta-sigma ADC, the front-end DRE gain amplifier enables the PCM1820 to record a far-field audio signal with very high fidelity, both in quiet and loud environments. Moreover, the ADC architecture has inherent antialias filtering with a high rejection of out-of-band frequency noise around multiple modulator frequency components. Therefore, the device prevents noise from aliasing into the audio band during ADC sampling. Further on in the signal chain, an integrated, high- performance multistage digital decimation filter sharply cuts off any out-of-band frequency noise with high stop- band attenuation. The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal to be recorded by using a 176.4-kHz (or higher) sample rate. PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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8.3.6.1 Digital High-Pass Filter

To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data, the device supports a fixed high-pass filter (HPF) with –3-dB cut-off frequency of 0.00025 × f S. The HPF is not a channel-independent filter but is globally applicable for all the ADC channels. This HPF is constructed using the first-order infinite impulse response (IIR) filter, and is efficient enough to filter out possible DC components of the signal. Table 8-6 shows the fixed –3-dB cutoff frequency value. Figure 8-8 shows a frequency response plot for the HPF filter. Table 8-6. HPF Cutoff Frequency Value -3-dB CUTOFF FREQUENCY VALUE -3-dB CUTTOFF FREQUENCY AT 16 kHz SAMPLE RATE -3-dB CUTTOFF FREQUENCY AT 48 kHz SAMPLE RATE 0.00025 × fS 4 Hz 12 Hz Normalized Frequency (1/fS) Magnitude (dB) -24 -21 -18 -15 -12 DPlo HPF -3 dB Cutoff = 0.00025 u fS Figure 8-8. HPF Filter Frequency Response Plot www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: PCM1820 PCM1821

8.3.6.2 Configurable Digital Decimation Filters

The device record channel includes a high dynamic range, built-in digital decimation filter to process the oversampled data from the multibit delta-sigma ( ΔΣ) modulator to generate digital data at the same Nyquist sampling rate as the FSYNC rate. The decimation filter can be chosen from two different types only in slave mode, depending on the required frequency response, group delay, and phase linearity requirements for the target application. The selection of the decimation filter option can be done by the MD0 pin. Table 8-7 shows the decimation filter mode selection for the record channel. Table 8-7. Decimation Filter Mode Selection for the Record Channel MD0 DECIMATION FILTER MODE SELECTION (Supported Only in Slave Mode) LOW Linear phase filters are used for the decimation in slave mode. For master mode, the device always use linear phase filters for the decimation. HIGH Low latency filters are used for the decimation in slave mode. For master mode, the device always use linear phase filters for the decimation.

8.3.6.2.1 Linear Phase Filters

The linear phase decimation filters are the default filters set by the device and can be used for all applications that require a perfect linear phase with zero-phase deviation within the pass-band specification of the filter. The filter performance specifications and various plots for all supported output sampling rates are listed in this section. Figure 8-9 and Figure 8-10 respectively show the magnitude response and the pass-band ripple for a decimation filter with a sampling rate of 8 kHz or 7.35 kHz. Table 8-8 lists the specifications for a decimation filter with an 8-kHz or 7.35-kHz sampling rate. Normalized Frequency (1/fS) Magnitude (dB) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 D001 Figure 8-9. Linear Phase Decimation Filter Magnitude Response Normalized Frequency (1/fS) Magnitude (dB) -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 D001 Figure 8-10. Linear Phase Decimation Filter Pass- Band Ripple Table 8-8. Linear Phase Decimation Filter Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pass-band ripple Frequency range is 0 to 0.454 × fS –0.05 0.05 dB Stop-band attenuation Frequency range is 0.58 × fS to 4 × fS 72.7 dB Frequency range is 4 × fS onwards 81.2 Group delay or latency Frequency range is 0 to 0.454 × fS 17.1 1/fS PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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Figure 8-15 and Figure 8-16 respectively show the magnitude response and the pass-band ripple for a decimation filter with a sampling rate of 32 kHz or 29.4 kHz. Table 8-11 lists the specifications for a decimation filter with an 32-kHz or 29.4-kHz sampling rate. Normalized Frequency (1/fS) Magnitude (dB) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 D001 Figure 8-15. Linear Phase Decimation Filter Magnitude Response Normalized Frequency (1/fS) Magnitude (dB) -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 D001 Figure 8-16. Linear Phase Decimation Filter Pass- Band Ripple Table 8-11. Linear Phase Decimation Filter Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pass-band ripple Frequency range is 0 to 0.454 × fS –0.05 0.05 dB Stop-band attenuation Frequency range is 0.58 × fS to 4 × fS 73.7 dB Frequency range is 4 × fS onwards 107.2 Group delay or latency Frequency range is 0 to 0.454 × fS 16.9 1/fS Figure 8-17 and Figure 8-18 respectively show the magnitude response and the pass-band ripple for a decimation filter with a sampling rate of 48 kHz or 44.1 kHz. Table 8-12 lists the specifications for a decimation filter with an 48-kHz or 44.1-kHz sampling rate. Normalized Frequency (1/fS) Magnitude (dB) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 D001 Figure 8-17. Linear Phase Decimation Filter Magnitude Response Normalized Frequency (1/fS) Magnitude (dB) -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 D001 Figure 8-18. Linear Phase Decimation Filter Pass- Band Ripple Table 8-12. Linear Phase Decimation Filter Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pass-band ripple Frequency range is 0 to 0.454 × fS –0.05 0.05 dB Stop-band attenuation Frequency range is 0.58 × fS to 4 × fS 73.8 dB Frequency range is 4 × fS onwards 98.1 Group delay or latency Frequency range is 0 to 0.454 × fS 17.1 1/fS PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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8.3.6.2.2 Low-Latency Filters

For applications where low latency with minimal phase deviation (within the audio band) is critical, the low- latency decimation filters on the PCM182x can be used. The device supports these filters with a group delay of approximately seven samples with an almost linear phase response within the 0.365 × f S frequency band. This section provides the filter performance specifications and various plots for all supported output sampling rates for the low-latency filters. Figure 8-23 shows the magnitude response and Figure 8-24 shows the pass-band ripple and phase deviation for a decimation filter with a sampling rate of 16 kHz or 14.7 kHz. Table 8-15 lists the specifications for a decimation filter with a 16-kHz or 14.7-kHz sampling rate. Normalized Frequency (1/fS) Magnitude (dB) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 D002 Figure 8-23. Low-Latency Decimation Filter Magnitude Response Normalized Frequency (1/fS) Magnitude (dB) Phase Deviation from Linear (Degree) -0.5 -0.5 -0.4 -0.4 -0.3 -0.3 -0.2 -0.2 -0.1 -0.1 0 0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 D002 Pass-Band Ripple Phase Deviation Figure 8-24. Low-Latency Decimation Filter Pass- Band Ripple and Phase Deviation Table 8-15. Low-Latency Decimation Filter Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pass-band ripple Frequency range is 0 to 0.451 × fS –0.05 0.05 dB Stop-band attenuation Frequency range is 0.61 × fS onwards 87.3 dB Group delay or latency Frequency range is 0 to 0.363 × fS 7.6 1/fS Group delay deviation Frequency range is 0 to 0.363 × fS –0.022 0.022 1/fS Phase deviation Frequency range is 0 to 0.363 × fS –0.21 0.25 Degrees PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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Table 8-17. Low-Latency Decimation Filter Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pass-band ripple Frequency range is 0 to 0.457 × fS –0.04 0.04 dB Stop-band attenuation Frequency range is 0.6 × fS onwards 88.3 dB Group delay or latency Frequency range is 0 to 0.368 × fS 8.7 1/fS Group delay deviation Frequency range is 0 to 0.368 × fS –0.026 0.026 1/fS Phase deviation Frequency range is 0 to 0.368 × fS –0.26 0.31 Degrees Figure 8-29 shows the magnitude response and Figure 8-30 shows the pass-band ripple and phase deviation for a decimation filter with a sampling rate of 48 kHz or 44.1 kHz. Table 8-18 lists the specifications for a decimation filter with a 48-kHz or 44.1-kHz sampling rate. Normalized Frequency (1/fS) Magnitude (dB) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 D002 Figure 8-29. Low-Latency Decimation Filter Magnitude Response Normalized Frequency (1/fS) Magnitude (dB) Phase Deviation from Linear (Degree) -0.5 -0.5 -0.4 -0.4 -0.3 -0.3 -0.2 -0.2 -0.1 -0.1 0 0 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 D002 Pass-Band Ripple Phase Deviation Figure 8-30. Low-Latency Decimation Filter Pass- Band Ripple and Phase Deviation Table 8-18. Low-Latency Decimation Filter Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Pass-band ripple Frequency range is 0 to 0.452 × fS –0.015 0.015 dB Stop-band attenuation Frequency range is 0.6 × fS onwards 86.4 dB Group delay or latency Frequency range is 0 to 0.365 × fS 7.7 1/fS Group delay deviation Frequency range is 0 to 0.365 × fS –0.027 0.027 1/fS Phase deviation Frequency range is 0 to 0.365 × fS –0.25 0.30 Degrees PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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8.3.7 Dynamic Range Enhancer (DRE)

The device integrates an ultra-low noise front-end DRE gain amplifier with 123-dB dynamic range performance with a low-noise, low-distortion, multibit delta-sigma (ΔΣ) ADC with a 113-dB dynamic range. The dynamic range enhancer (DRE) is a digitally assisted algorithm to boost the overall channel performance. The DRE monitors the incoming signal amplitude and accordingly adjusts the internal DRE amplifier gain automatically. The DRE achieves a complete-channel dynamic range as high as 123 dB. At a system level, the DRE scheme enables far- field, high-fidelity recording of audio signals in very quiet environments and low-distortion recording in loud environments. The DRE can be enabled only in slave mode by driving the MD1 pin high. Table 8-20 shows the DRE selection for the record channel. Additionally, this feature is only supported in the PCM1820 and not in the PCM1821. Table 8-20. DRE Selection for the Record Channel MD1 DRE SELECTION (Supported Only in Slave Mode) Low The DRE is disabled in slave mode. For master mode, the DRE is always disabled. High The DRE is enabled with DRE_LVL = –36 dB and DRE_MAXGAIN = 24 dB in slave mode. For master mode, the DRE is always disabled. This algorithm is implemented with very low latency and all signal chain blocks are designed to minimize any audible artifacts that may occur resulting from dynamic gain modulation. The target signal threshold level (DRE_LVL), at which the DRE is triggered, is fixed to the –36-dB input signal level. The DRE gain range can be dynamically modulated by using DRE_MAXGAIN, which is fixed to 24 dB to maximize the benefit of the DRE in real-world applications and to minimize any audible artifacts. Enabling the DRE for processing increases the power consumption of the device because of increased signal processing. Therefore, disable the DRE for low-power critical applications. Furthermore, the DRE is not supported for output sample rates greater than 48 kHz.

8.4 Device Functional Modes

8.4.1 Active Mode

The device wakes up in active mode when AVDD and IOVDD are available. Configure all hardware control pins (MSZ, MD0, MD1, and FMT0 ) for the device desired mode of operation before enabling clocks for the device. In active mode, when the audio clocks are available, the device automatically powers up all ADC channels and starts transmitting data over the audio serial interface. If the clocks are stopped, then the device auto powers down the ADC channels. PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The PCM182x is a multichannel, high-performance audio analog-to-digital converter (ADC) that supports output sample rates of up to 192 kHz. The device supports up to two analog microphones for simultaneous recording applications. The PCM182x configuration is supported using various hardware pin control options. The device supports a highly flexible, audio serial interface (TDM and I 2S) to transmit audio data seamlessly in the system across devices.

9.2 Typical Application

Figure 9-1 shows a typical configuration of the PCM182x for an application using stereo analog microelectrical- mechanical system (MEMS) microphones for simultaneous recording operation with a time-division multiplexing (TDM) audio data slave interface. For best distortion performance, use input AC-coupling capacitors with a low- voltage coefficient. 3.3 V (3.0 V to 3.6 V) OR 1.8 V (1.65 V to 1.95 V) 3.3 V (3.0 V to 3.6 V) PCM1820/PCM1821 IN1P IN1M GND GND VSS VREF GND AREG 0.1 F GND F AVDD F DREG F GND 0.1 F IN2P IN2M Host Processor IOVDD GND Thermal Pad (VSS) GND SDOUT BCLK FSYNC F AMIC1 OUTP OUTM VDD VSS AMIC2 OUTP OUTM VDD VSS GND LOW/HIGH Pin Selector MD0 FMT0 MSZ MD1 Figure 9-1. Two-Channel Analog Microphone Recording Diagram for 3.3-V AVDD Operation www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: PCM1820 PCM1821

9.2.1 Design Requirements

Table 9-1 lists the design parameters for this application. Table 9-1. Design Parameters KEY PARAMETER SPECIFICATION: 3.3-V AVDD OPERATION AVDD 3.3 V AVDD supply current consumption TBD mA (PLL on, two-channel recording, fS = 48 kHz) IOVDD 1.8 V or 3.3 V

9.2.2 Detailed Design Procedure

This section describes the necessary steps to configure the PCM182x for this specific application. The following steps provide a sequence of steps that must be executed in the time between powering the device up and reading data from the device or transitioning from one mode to another mode of operation. 1. Apply power to the device: a. Power-up the IOVDD and AVDD power supplies b. The device now goes into low-power mode 2. Configure the pins for correct configuration: a. Connect the MSZ, FMT0, MD0, and MD1 pin voltages for the desired configuration b. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio See the Phase-Locked Loop (PLL) and Clock Generation section for supported sample rates and the BCLK to FSYNC ratio c. The device recording data are now sent to the host processor via the audio serial data bus 3. Stop the clocks to stop recording of data at any time PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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9.2.3 Application Curves

Measurements are done on the EVM by feeding the device analog input signal using audio precision and with a 3.3-V AVDD supply. Figure 9-2. FFT With a –60-dBr Input With DRE Enabled Figure 9-3. THD+N vs Input Amplitude With DRE Enabled Figure 9-4. FFT With a –60-dBr Input With DRE Disabled Figure 9-5. THD+N vs Input Amplitude With DRE Disabled www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: PCM1820 PCM1821

10 Power Supply Recommendations

The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, do not provide any clocks until the IOVDD and AVDD supply voltage settles to a stable and supported operating voltage range. Provide the clocks (FSYNC and BCLK) only when all hardware control pins (MSZ, MD0, MD1, FMT0, and FMT1) are driven to the voltage level for the device desired mode of operation. For the supply power-up requirement, t1 and t2 must be at least 100 µs. For the supply power-down requirement, t3 and t 4 must be at least 10 ms. This timing (as shown in Figure 10-1) allows the device to ramp down the volume on the record data, power down the analog and digital blocks, and put the device into hardware shutdown mode. AVDD IOVDD ASI Clocks Figure 10-1. Power-Supply Sequencing Requirement Timing Diagram Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a power-up event is at least 100 ms. PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

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11 Layout

11.1 Layout Guidelines

Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in the context of a specific PCB design. However, the following guidelines can optimize the device performance:

• Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, which is the area directly under the device, to the ground planes. This connection helps dissipate heat from the device.
• The decoupling capacitors for the power supplies must be placed close to the device pins.
• Route the analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing digital and analog signals to prevent undesirable crosstalk.
• The device internal voltage references must be filtered using external capacitors. Place the filter capacitors near the VREF pin for optimal performance.
• Directly short the VREF external capacitor ground terminal to the AVSS pin without using any vias for this connection trace.
• Use ground planes to provide the lowest impedance for power and signal current between the device and the decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and all device grounds must be connected directly to that area.

11.2 Layout Example

Figure 11-1. Example Layout www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: PCM1820 PCM1821

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

Burr-Brown™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

34 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: PCM1820 PCM1821

www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: PCM1820 PCM1821

PCM1820, PCM1821 SBASA61 – DECEMBER 2020 www.ti.com ADVANCE INFORMATION

36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: PCM1820 PCM1821

www.ti.com PCM1820, PCM1821 SBASA61 – DECEMBER 2020 ADVANCE INFORMATION Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: PCM1820 PCM1821

www.ti.com 11-Jan-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples XCM1820IRTER ACTIVE WQFN RTE 20 3000 RoHS (In work) & Green (In work) Call TI Call TI -40 to 125 XCM1821IRTER ACTIVE WQFN RTE 20 3000 RoHS (In work) & Green (In work) Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 11-Jan-2021 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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