XC9850 IDT | Alldatasheet

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Technical content

Features

  • 8 LVCMOS outputs for processor and other circuitry
  • 2 differential LVDS outputs for Rapid I/O interface
  • Crystal oscillator or external reference input
  • 25 or 33 MHz Input reference frequency
  • Selectable output frequencies include = 200, 166, 133,125, 111, 100, 83, 66, 50, 33 or 16 MHz
  • Buffered reference clock output
  • Rapid I/O (LVDS) Output = 500, 250 or 125 MHz
  • Low cycle-to-cycle and period jitter
  • 100-lead PBGA package
  • 100-lead Pb-free Package Available
  • 3.3V supply with 3.3V or 2.5V output LVCMOS drive
  • Supports computing, networking, telecommunications applications
  • Ambient temperature range –40°C to +85°C Functional Description The XC9850 uses either a 25 or 33 MHz reference frequency to generate 8 LVCMOS output clocks, of which, the frequency is selectable from 16 MHz to 200 MHz. The reference is applied to the input of a PLL and multiplied to 2 GHz. Output dividers, divide this frequency by 10, 12, 15, 16, 18, 20, 24, 30, 40, 60 or 120 to produce output frequencies of 200, 166, 133, 125, 111, 100, 83 66 50 33 or 16 MHz. The single-ended LVCMOS outputs are divided into two banks of 4 low skew outputs each, for use in driving a microprocessor or microcontroller clock input as well as other system components. The 2 GHz PLL output frequency is also divided to produce a 125, 250 or 500 MHz clock output for Rapid I/O applications such as found on the PowerQUICC III communications processor. The input reference, either crystal or external input is also buffered to a separate output that my be used as the clock source for a Gigabit Ethernet PHY if desired. The reference clock may be provided by either an external clock input of 25 MHz or 33 MHz. An internal oscillator requiring a 25 MHz crystal for frequency control may also be used. The external clock source my be applied to either of two clock inputs and selected via the CLK_SEL control input. Both single ended LVCMOS and differential LVPECL inputs are available. The crystal oscillator or external clock input is selected via the input pin of REF_SEL. Other than the crystal, no external components are required for crystal oscillator operation. The REF_33MHz configuration pins is used to select between a 33 and 25 MHz input frequency. The XC9850 is packaged in a 100 lead MAPBGA package to optimize both performance and board density. MICROPROCESSOR CLOCK GENERATOR SCALE 2:1 VF SUFFIX VM SUFFIX (Pb-FREE)

100 MAPBGA PACKAGE

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... DATA SHEET XC9850 IDT™ Clock Generator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc XC9850 Clock Generator for PowerQUICC III

Figure 1. XC9850 Logic Diagram Table 1. Pin Configurations

  1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)
  2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)

2000 MHz

Freescale Semiconductor, Inc.

Table 2. Function Table Table 3. Output Configurations (Banks A & B)

  1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)

Table 4. Output Configurations (Bank C) Freescale Semiconductor, Inc.

Table 5. Absolute Maximum Ratings1

  1. Absolute maximum continuous ratings ar e those maximum values beyond which damage to the device may occur. Exposure to these conditions
  2. V DDx references power supply pin associated with specific output pin.

Table 6. General Specifications Table 7. DC Characteristics (TA = –40°C to 85°C) Freescale Semiconductor, Inc.

Table 8. LVDS DC Characteristics (TA = –40°C to 85°C)

  1. V PP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.

Table 9. LVPECL DC Characteristics (TA = –40°C to 85°C)1

  1. AC characteristics are design targets and pending characterization.
  2. V PP is the minimum differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
  3. V CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range

Table 10. LVCMOS I/O DC Characteristics (TA = –40°C to 85°C)

  1. Inputs have pull-down resistors affecting the input current.

Freescale Semiconductor, Inc.

Figure 4. XC9850 AC Test Reference (LVDS Outputs) Figure 5. XC9850 AC Test Reference (LVCMOS Outputs) Table 11. AC Characteristics (VDD = 3.3 V ± 5%, VDDOA = 3.3 V ± 5%,VDDOB = 3.3 V ± 5%, TA= –40°C to +85°C)1 2

  1. AC characteristics are design targets and pending characterization.
  2. AC characteristics apply for parallel output termination of 50 Ω to VTT.
  3. In bypass mode, the XC9850 divides the input reference clock.
  4. The input reference frequency must match the VCO lo ck range divided by the total feedback divider ratio: fref = (fVCO ÷ M) ⋅ N.

Freescale Semiconductor, Inc.

Table 12. XC9850 Pin Diagram (Top View) Table 13. XC9850 Pin List Freescale Semiconductor, Inc.

TIMING SOLUTIONS 9 MOTOROLA OUTLINE DIMENSIONSOUTLINE DIMENSIONS CASE 1462-01 ISSUE O DATE 11/26/02 A1 INDEX AREA B C 0.2 TOP VIEW A1 INDEX AREA 109874321 A B C D E F G H J K BOTTOM VIEW BM0.25 C A M0.10 A 100X 0.55 0.45 0.5 0.5 9X 1 K SIDE VIEW A 0.35 A 0.12 A 100X 0.43 (1.18)1.7 MAX ROTATED 90˚ CLOCKWISE DETAIL K SEATING PLANE 0.29 NOTES: ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. DATUM A, SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGING. VF SUFFIX

100 MAP PBGA PACKAGE

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... XC9850 Clock Generator for PowerQUICC III NETCOM IDT™ Clock Generator for PowerQUICC III Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc XC9850

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX Corporate Headquarters Integrated Device Technology, Inc.

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San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G

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