MPC7445 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Semiconductor Technical Data The MPC7455 and MPC7445 are implementations of the PowerPC™ microprocessor family of reduced instruction set computer (RISC) microprocessors. This document is primarily concerned with the MPC7455; however, unless otherwise noted, all information here also applies to the MPC7445. This document describes pertinent electrical and physical characteristics of the MPC7455. For functional characteristics of the processor, refer to the MPC7450 RISC Microprocessor Family User’ s Manual . To locate any published updates for this document, refer to the website at http://www.freescale.com. 1O v e r v i e w The MPC7455 is the third implementation of the fourth generation (G4) microprocessors from Freescale. The MPC7455 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7455 consists of a processor core, a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high-bandwidth interface. The MPC7445 is identical to the MPC7455 except it does not support the L3 cache interface. Figure 1 shows a block diagram of the MPC7455. MPC7455EC Rev. 4.1, 02/2005
Contents
- Comparison with the MPC7400, MPC7410, MPC7455 RISC Microprocessor Hardware Specifications
2 Freescale Semiconductor
Figure 1. MPC7455 Block Diagram
- Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor x ÷ FPSCRFPSCR PA +x÷ Instruction Unit Instruction Queue (12-Word) 96-Bit (3 Instructions) Reservation Integer 128-Bit (4 Instructions) 32-Bit Floating- Point Unit 64-Bit Reservation Load/Store Unit (EA Calculation) Finished 32-Bit Completion Unit Completion Queue (16-Entry) Tag s 32-Kbyte D Cache L3 Cache Controller System Bus Interface 36-Bit Address Bus 64-Bit Data Bus 18-Bit 64-Bit Data Integer Stations (2) Reservation Station Reservation Stations (2) FPR File
16 Rename
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1 Freescale Semiconductor 3
Features
The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other system resources. The L3 interface su pports 1 or 2 Mbytes of external SRAM for L3 cache data. Note that the MPC7455 is footprint-compatible with the MPC7450 and MPC7451, and the MPC7445 is footprint-compatible with the MPC7441. 2F e a t u r e s This section summarizes features of the MPC7455 implementation of the PowerPC architecture. Major features of the MPC7455 are as follows: High-performance, superscalar microprocessor — As many as four instructions can be fetched from the instruction cache at a time — As many as three instructions can be dispatched to the issue queues at a time — As many as 12 instructions can be in the instruction queue (IQ) — As many as 16 instructions can be at some stage of execution simultaneously — Single-cycle execution for most instructions — One instruction per clock cycle throughput for most instructions — Seven-stage pipeline control Eleven independent execution units and three register files — Branch processing unit (BPU) features static and dynamic branch prediction – 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. – 2048-entry branch history table (BHT) with two bits per entry for four levels of prediction—not-taken, strongly not-taken, taken, and strongly taken – Up to three outstanding speculative branches – Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream. – Eight-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) instructions — Four integer units (IUs) that share 32 GPRs for integer operands – Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions – IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions — Five-stage FPU and a 32-entry FPR file – Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations – Supports non-IEEE mode for time-critical operations – Hardware support for denormalized numbers
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
4 Freescale Semiconductor
– Thirty-two 64-bit FPRs for single- or double-precision operands — Four vector units and 32-entry vector register file (VRs) – Vector permute unit (VPU) – Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add instructions (vaddsbs, vaddshs, and vaddsws, for example) – Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions ( vmhaddshs, vmhraddshs, and vmladduhm, for example) – Vector floating-point unit (VFPU) — Three-stage load/store unit (LSU) – Supports integer, floating-point, and vector instruction load/store traffic – Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations – Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle throughput – Four-cycle FPR load latency (single, double) with one-cycle throughput – No additional delay for misaligned access within double-word boundary – Dedicated adder calculates effective addresses (EAs) – Supports store gathering – Performs alignment, normalization, and precision conversion for floating-point data – Executes cache control and TLB instructions – Performs alignment, zero padding, and sign extension for integer data – Supports hits under misses (multiple outstanding misses) – Supports both big- and little-endian modes, including misaligned little-endian accesses Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: — Instructions can be dispatched only from the three lowest IQ entries—IQ0, IQ1, and IQ2 — A maximum of three instructions can be dispatched to the issue queues per clock cycle — Space must be available in the CQ for an instruction to dispatch (this includes instructions that are assigned a space in the CQ but not in an issue queue) Rename buffers — 16 GPR rename buffers — 16 FPR rename buffers — 16 VR rename buffers Dispatch unit — Decode/dispatch stage fully decodes each instruction Completion unit — The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending. — Guarantees sequential programming model (precise exception model) — Monitors all dispatched instructions and retires them in order — Tracks unresolved branches and flushes instructions after a mispredicted branch
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1 Freescale Semiconductor 5 — Retires as many as three instructions per clock cycle Separate on-chip L1 instruction and data caches (Harvard architecture) — 32-Kbyte, eight-way set-associative instruction and data caches — Pseudo least-recently-used (PLRU) replacement algorithm — 32-byte (eight-word) L1 cache block — Physically indexed/physical tags — Cache write-back or write-through operation programmable on a per-page or per-block basis — Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle — Caches can be disabled in software — Caches can be locked in software — MESI data cache coherency maintained in hardware — Separate copy of data cache tags for efficient snooping — Parity support on cache and tags — No snooping of instruction cache except for icbi instruction — Data cache supports AltiVec LRU and transient instructions — Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding. Level 2 (L2) cache interface — On-chip, 256-Kbyte, eight-way set-associative unified instruction and data cache — Fully pipelined to provide 32 bytes per clock cycle to the L1 caches — A total nine-cycle load latency for an L1 data cache miss that hits in L2 — PLRU replacement algorithm — Cache write-back or write-through operation programmable on a per-page or per-block basis — 64-byte, two-sectored line size — Parity support on cache Level 3 (L3) cache interface (not implemented on MPC7445) — Provides critical double-word forwarding to the requesting unit — Internal L3 cache controller and tags — External data SRAMs — Support for 1- and 2-Mbyte L3 caches — Cache write-back or write-through operation programmable on a per-page or per-block basis — 64-byte (1M) or 128-byte (2M) sectored line size — Private memory capability for half (1-Mbyte minimum) or all of the L3 SRAM space — Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined synchronous Burst SRAMs, and pipelined (register-register) late write synchronous Burst SRAMs — Supports parity on cache and tags — Configurable core-to-L3 frequency divisors — 64-bit external L3 data bus sustains 64 bits per L3 clock cycle
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
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Separate memory management units (MMUs) for instructions and data — 52-bit virtual address; 32- or 36-bit physical address — Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments — Memory programmable as write-back/write-through, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis — Separate IBATs and DBATs (eight each) also defined as SPRs — Separate instruction and data translation lookaside buffers (TLBs) – Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm – TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is performed in hardware or by system software) Efficient data flow — Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits — The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs — L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache — As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data cache and L2/L3 bus — As many as 16 out-of-order transactions can be present on the MPX bus — Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed). — Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data cache — Separate additional queues for efficient buffering of outbound data (such as castouts and write through stores) from the L1 data cache and L2 cache Multiprocessing support features include the following: — Hardware-enforced, MESI cache coherency protocols for data cache — Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations Power and thermal management — 1.3-V processor core — The following three power-saving modes are available to the system: – Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ /QACK processor-system handshake protocol. – Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled. – Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed on exiting the deep sleep state. — Thermal management facility provides software-controllable thermal management. Thermal management is performed through the use of three supervisor-level registers and an MPC7455-specific thermal management exception. — Instruction cache throttling provides control of instruction fetching to limit power consumption
3 Comparison with the MPC7400, MPC7410, MPC7450,
Table 1. Microarchitecture Comparison
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Table 1. Microarchitecture Comparison (continued)
4 General Parameters
2.5 V ± 5% DC, or
1.5 V ± 5% DC (L3 interface only)
- Numbers in parentheses are for 2:1 SRAM.
- Not implemented on MPC7445 or MPC7441.
- Private memory feature not implemented on MPC7400.
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5 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7455.
5.1 DC Electrical Characteristics
Table 2. Absolute Maximum Ratings 1
- Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only,
reliability or cause permanent damage to the device.
- Caution: Vin must not exceed OV
DD or GVDD by more than 0.3 V at any time including during power-on reset.
- Caution: OVDD/GVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
- Caution: VDD/AVDD must not exceed OVDD/GVDD by more than 1.0 V during normal operation; this limit may be
exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
- Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
- BVSEL must be set to 0, such that the bus is in 1.8 V mode.
- BVSEL must be set to HRESET
or 1, such that the bus is in 2.5 V mode.
- L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5 V mode.
- L3VSEL must be set to 0, such that the bus is in 1.8 V mode.
or 1, such that the bus is in 2.5 V mode.
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Table 4 provides the recommended operating conditions for the MPC7455. Table 4. Recommended Operating Conditions 1
- These are the recommended and tested operating conditions. Proper device operation outside of these conditions
- This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the
voltage at the AVDD pin which may be reduced from V DD by the filter.
Table 5 provides the package thermal characteristics for the MPC7455. Table 6 provides the DC electrical characteristics for the MPC7455. Table 5. Package Thermal Characteristics 6
- Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
- Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
- Per JEDEC JESD51-6 with the board horizontal.
- Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method
- Refer to Section 9.8, “Thermal Management Information,” for more details about thermal management.
Table 6. DC Electrical Specifications At recommended operating conditions. See Table 4.
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Table 7 provides the power consumption for the MPC7455.
- Nominal voltages; see T able 4 for recommended operating conditions.
- For processor bus signals, the reference is OV DD while GVDD is the reference for the L3 bus signals.
- Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
- Capacitance is periodically sampled rather than 100% tested.
- The leakage is measured for nominal OV
direction (for example, both OV DD and VDD vary by either +5% or –5%).
- Applicable to L3 bus interface only.
Table 7. Power Consumption for MPC7455
733 MHz 867 MHz 933 MHz 1 GHz
Table 6. DC Electrical Specifications (continued) At recommended operating conditions. See Table 4.
5.2 AC Electrical Characteristics
5.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
- These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OVDD
power. Worst case power consumption for AVDD < 3 mW.
- Maximum power is measured at nominal V DD (see T able 4) while running an entirely cache-resident, contrived
sequence of instructions which keep the execution units, with or without AltiVec, maximally busy.
- Typical power is an average value measured at the nominal recommended VDD (see Table 4) and 65°C in a system
while running a typical code sequence.
- Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode.
As a result, power consumption for this mode is not tested. Table 8. Clock AC Timing Specifications At recommended operating conditions. See Table 4. Table 7. Power Consumption for MPC7455 (continued)
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Figure 3 provides the SYSCLK input timing diagram. Figure 3. SYSCLK Input Timing Diagram
- Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK
for valid PLL_CFG[0:4] settings.
- Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.
- Timing is guaranteed by design and characterization.
- This represents total input jitter—short term and long term combined—and is guaranteed by design.
- Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
- The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter. Table 8. Clock AC Timing Specifications (continued) At recommended operating conditions. See Table 4.
5.2.2 Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7455 as defined in Figure 4 and Figure 5. Table 9. Processor Bus AC Timing Specifications 1 At recommended operating conditions. See Table 4.
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Figure 4 provides the AC test load for the MPC7455. Figure 4. AC Test Load
- All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
- The symbology used for timing specifications herein follows the pattern of t
inputs) and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
- tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
- According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high
high-impedance behavior is guaranteed by design.
- Guaranteed by design and not tested.
- According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
hold timing is tested for the signal asserted. The high-impedance behavior is guaranteed by design.
- According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Timing
tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core-to-bus (PLL configurations).
- BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These paramenters
inputs must remain stable after the second sample. See Figure 5 for sample timing. Table 9. Processor Bus AC Timing Specifications 1 (continued) At recommended operating conditions. See Table 4.
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5.2.3 L3 Clock AC Specifications
output AC timing specifications as defined in Figure 7. trace length, and may be greater or less than the value given in Table 10. information are tested at core-to-L3 divisors which result in L3 frequencies at 200 MHz or less. Table 10. L3_CLK Output AC Timing Specifications At recommended operating conditions. See Table 4.
- The maximum L3 clock frequency will be system dependent. See Section 5.2.3, “L3 Clock AC Specifications,” for
an explanation that this maximum frequency is not functionally tested at speed by Freescale.
- The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
- Maximum possible skew between L3_CLK0 and L3_CLK1. Th is parameter is critical to the address and control
signals which are common to both SRAM chips in the L3.
- Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for
SRAM part by these pairs of signals.
- Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3
The L3_CLK timing diagram is shown in Figure 7. Figure 7. L3_CLK_OUT Output Timing Diagram
5.2.4 L3 Bus AC Specifications
appropriately for each type of SRAM. Following are some observations about the chip-to-SRAM interface. be altered in order to intentionally skew the timing and provide additional setup or hold time margin. For a 1-Mbyte L3, use address bits 16:0 (bit 0 is LSB). No pull-up resistors are required for the L3 interface. test load for the L3 interface. Figure 8. AC Test Load for the L3 Interface
22 Freescale Semiconductor
while L3DATA[0:15], L3DP[0:1], and L3_ECHO_CLK[0] form a closely coupled group of inputs. unpredictable behavior. For more information, see the MPC7450 RISC Microprocessor Family User’ s Manual.
5.2.4.1 L3 Bus AC Specifications for DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 9. across the printed-wiring board. defined in the L3CR register. Table 11. Sample Points Calculation Parameters
- This specification describes a logical offset between the internal clock edge used to launch the L3 address and
and, thus, is specified here.
- This specification is the delay from a rising or falling edge on the internal_L3_CLK signal to the corresponding rising
or falling edge at the L3CLK n pins.
- This specification is the delay from a rising or falling edge of L3_ECHO_CLKn to data valid and ready to be sampled
assuming the timing relationships shown in Figure 10 and the loading shown in Figure 8. Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 At recommended operating conditions. See Table 4.
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- Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV DD.
- For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
or falling edge of the input L3_ECHO_CLK n (see Figure 10). Input timings are measured at the pins.
- For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10. For consistency with other
input setup time specifications, this will be treated as negative input setup time.
- tL3_CLK/4 is one-fourth the period of L3_CLK n. This parameter indicates that the MPC7455 can latch an input signal that is
of L3_ECHO_CLKn at any frequency.
- All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge
a purely resistive 50-Ω load (see Figure 8).
- For DDR, the output data will typically l ead the edge of L3_CLK
valid time specifications, this will be treated as negative output valid time.
- tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
- These configuration bits allow the AC timing of the L3 interface to be altered via software. L3OH0 = L2CR[12],
This Document,” for more information on which devices are addressed by this document. Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued) At recommended operating conditions. See Table 4.
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Figure 10 shows the L3 bus timing diagrams for the MPC7455 interfaced to MSUG2 SRAMs. Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
5.2.4.2 L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or late write SRAMs at the L3 interface, the parts should be connected as shown in Figure 11. control, and write data. Read data is launched by the SRAM synchronous to the delayed L3_CLKn signal it received. MPC7455 will latch the incoming data on the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
the timing relationships of Figure 12 and the loading of Figure 8. Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs At recommended operating conditions. See Table 4.
28 Freescale Semiconductor
- Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV DD.
- All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L3_ECHO_CLK n (see Figure 10). Input timings are measured at the pins.
- All output specifications are measured from the midpoint voltage of the rising edge of L3_CLK n to the midpoint of the signal
- tL3_CLK/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
- Timing behavior and characterization are currently being evaluated.
- These configuration bits allow the AC timing of the L3 interface to be altered via software. L3OH0 = L2CR[12],
This Document,” for more information on which devices are addressed by this document. Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs (continued) At recommended operating conditions. See Table 4.
30 Freescale Semiconductor
Figure 12 shows the L3 bus timing diagrams for the MPC7455 interfaced to PB2 or late write SRAMs. Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 14 through Figure 17. Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) 1 At recommended operating conditions. See Table 4.
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Figure 16 provides the boundary-scan timing diagram. Figure 16. Boundary-Scan Timing Diagram Figure 17 provides the test access port timing diagram. Figure 17. Test Access Port Timing Diagram
6 Pin Assignments
shows the side profile of the CBGA package to indicate the direction of the top surface view. Figure 18. Pinout of the MPC7445, 360 CBGA Package as Viewed from the Top Surface
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shows the side profile of the CBGA package to indicate the direction of the top surface view. Figure 19. Pinout of the MPC7455, 483 CBGA Package as Viewed from the Top Surface
7 Pinout Listings
the MPC7455, 483 CBGA package. Table 15. Pinout Listing for the MPC7445, 360 CBGA Package
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Table 15. Pinout Listing for the MPC7445, 360 CBGA Package (continued)
- OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor
recommended value of Vin or supply voltages see Table 4.
- These input signals are for factory use only and must be pulled up to OV DD for normal machine operation.
- These signals are for factory use only and must be left unconnected for normal machine operation.
- This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and w ill be sampled at
- This signal must be negated during reset, by pull-up to OV DD or negation by ¬HRESET (inverse of HRESET), to
- These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state
after they have been actively negated and released by the MPC7445 and other bus masters.
- These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10.This pin can externally cause a performance monitor event. Counting of the event is enabled via software. 11.Unused address pins must be pulled down to GND. 13.These signals must be pulled down to GND if unused, or if the MPC7445 is in 60x bus mode.
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Table 16. Pinout Listing for the MPC7455, 483 CBGA Package
Table 16. Pinout Listing for the MPC7455, 483 CBGA Package (continued)
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8 Package Description
The following sections provide the package parameters and mechanical dimensions for the CBGA package.
8.1 Package Parameters for the MPC7445, 360 CBGA
- OVDD supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]);
PLL (after filtering to become AVDD). For actual recommended value of V in or supply voltages, see Table 4.
- These input signals are for factory use only and must be pulled up to OV DD for normal machine operation.
- To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8 V) or to HRESET (selects
or to HRESET (selects 1.5 V). If used, pulldown resistors should be less than 250 Ω.
- This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and w ill be sampled at
- This signal must be negated during reset, by pull-up to OV DD or negation by ¬HRESET (inverse of HRESET), to
- These pins require weak pull-up resistors (for example, 4.7 k Ω) to maintain the control signals in the negated state
after they have been actively negated and released by the MPC7455 and other bus masters.
- These input signals for factory use only and must be pulled down to GND for normal machine operation.
10.This pin can externally cause a performance monitor event. Counting of the event is enabled via software. 11.Unused address pins must be pulled down to GND. 13.These signals must be pulled down to GND if unused or if the MPC7455 is in 60x bus mode. 15.Power must be supplied to GV DD, even when the L3 interface is disabled or unused. 16.These signals are for factory use only and must be left unconnected for normal machine operation.
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8.2 Mechanical Dimensions for the MPC7445, 360 CBGA
Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7445,
- DIMENSIONING AND TOLERANCING
- DIMENSIONS IN MILLIMETERS.
- TOP SIDE A1 CORNER INDEX IS A
8.3 Substrate Capacitors for the MPC7445, 360 CBGA
Figure 21. Substrate Bypass Capacitors for the MPC7445, 360 CBGA
8.4 Package Parameters for the MPC7455, 483 CBGA
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8.5 Mechanical Dimensions for the MPC7455, 483 CBGA
Figure 22. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7455,
- DIMENSIONING AND TOLERANCING
- DIMENSIONS IN MILLIMETERS.
- TOP SIDE A1 CORNER INDEX IS A
8.6 Substrate Capacitors for the MPC7455, 483 CBGA
Figure 23. Substrate Bypass Capacitors for the MPC7455, 483 CBGA
9 System Design Information
This section provides system and thermal design recommendations for successful application of the MPC7455.
9.1 PLL Configuration
46 Freescale Semiconductor
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1.0 GHz Parts
00110 PLL bypass PLL off, SYSCLK clocks core circuitry directly
11110 PLL off PLL off, no core clocking occurs
- PLL_CFG[0:4] settings not listed are reserved.
- The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,
“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.
- In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
- In PLL-off mode, no clocking occurs inside the MPC7455 regardless of the SYSCLK input.
Table 17. MPC7455 Microprocessor PLL Configuration Example for 1.0 GHz Parts (continued)
48 Freescale Semiconductor
example L3 clock frequencies that can be obtained for a given set of core frequencies.
9.2 PLL Power Supply Filtering
mount capacitors with minimum effective series inductance (ESL) is recommended. The circuit should be placed as close as possible to the A V DD pin to minimize noise coupled from nearby circuits. footprint and very close to the periphery of the 483 CBGA footprint, without the inductance of vias. Table 18. Sample Core-to-L3 Frequencies
- The core and L3 frequencies are for reference only. Note that maximum L3 frequency is design dependent. Some
the maximum L3 frequency. Shaded cells do not comply with Table 10.
- These core frequencies are not supported by all speed grades; see Table 8.
Figure 24. PLL Power Supply Filter Circuit
9.3 Decoupling Recommendations
OVDD/GVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. capacitors: 100–330 µF (A VX TPS tantalum or Sanyo OSCON).
9.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. (no-connect) signals must remain unconnected. Power and ground connections must be made to all external V DD, OVDD, GVDD, and GND pins in the MPC7455.
9.5 Output Buffer DC Impedance
is varied until the pad voltage is OV DD/2 (see Figure 25).
50 Freescale Semiconductor
and RN are designed to be close to each other in value. Then, Z 0 = (RP + RN)/2. Figure 25. Driver Impedance Measurement
relatively unaffected by bus voltage.
9.6 Pull-Up/Pull-Down Resistor Requirements
4.7–1 kΩ) if it is used by the system. This pin is CKSTP_OUT . due to ground bounce, power supply noise or noise coupling. Table 19. Impedance Characteristics
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
52 Freescale Semiconductor
If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. The L3 interface does not normally require pull-up resistors.
9.7 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 26 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0- Ω isolation resistor so that it is asserted when the system reset signal (HRESET ) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the COP header be designed into the system as shown in Figure 26, if this is not possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations. The COP header shown in Figure 26 adds many benefits—breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface—and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 26; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 26 is common to all known emulators. The QACK signal shown in Figure 26 is usually connected to the PCI bridge chip in a system and is an input to the MPC7455 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the MPC7455 must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is de-asserted when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are
QACK should be merged via logic so that it also can be driven by the PCI bridge. Figure 26. JTAG Interface Connection
- RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7455. Con
pin 5 of the COP header to OV DD with a 10-kΩ pull-up resistor.
- Key location; pin 14 is not physically present on the COP header.
- Component not populated. Populate only if debug tool does not drive QACK .
- Populate only if debug tool uses an open-drain type output and does not actively de-assert QAC K
- If the JTAG interface is implemented, connect HRESET from the target source to TRST from the
HRESET from the target source to TRST of the part through a 0-Ω isolation reisistor.
54 Freescale Semiconductor
9.8 Thermal Management Information
printed-circuit board is suggested. If a spring clip is used, the spring force should not exceed 10 pounds. Figure 27. Package Exploded Cross-Sectional View with Several Heat Sink Options
a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
9.8.1 Internal Package Conduction Resistance
Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection.
9.8.2 Thermal Interface Materials
56 Freescale Semiconductor
than the thermal grease joint. temperature, dielectric properties, cost, etc. Figure 29. Thermal Performance of Select Thermal Interface Material
18930 West 78
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1 Freescale Semiconductor 57 System Design Information Dow-Corning Corporation 800-248-2481 Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dow.com Shin-Etsu MicroSi, Inc. 888-642-7674 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com Thermagon Inc. 888-246-9050 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com The following section provides a heat sink selection example using one of the commercially available heat sinks.
9.8.3 Heat Sink Selection Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (RθJC + Rθint + Rθsa) × Pd where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet RθJC is the junction-to-case thermal resistance Rθint is the adhesive or interface material thermal resistance Rθsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation, the die-junction temperatures (T j) should be maintained less than the value specified in Table 4. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T a) may range from 30° to 40°C. The air temperature rise within a cabinet (T r) may be in the range of 5° to 10°C. The thermal resistance of the thermal interface material (R θint) is typically about 1.5°C/W. For example, assuming a T a of 30°C, a Tr of 5°C, a CBGA package R θJC = 0.1, and a typical power consumption (P d) of 15.0 W, the following expression for T j is obtained: Die-junction temperature: T j = 30°C + 5°C + (0.1°C/W + 1.5°C/W + R θsa) × 15 W For this example, a R θsa value of 3.1°C/W or less is required to maintain the die-junction temperature below the maximum value of Table 4. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction
58 Freescale Semiconductor
attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. package outline size of the package. The other two, die, and bump and underfill, have the same size as the die. Dimensions for these volumes for the MPC7445 and MPC7455 are given in Figure 20 and Figure 22, respectively. material properties: 0.034 W/(m K) in the xy-plane direction and 3.8 W/(m K) in the direction of the z-axis. Figure 30. Recommended Thermal Model of MPC7445 and MPC7455
10 Document Revision History
Table 20 provides a revision history for this hardware specification. Table 20. Document Revision History
1 Updated for Rev F devices; information specific to Rev C devices is now documented in a separate part
Removed 600 and 800 MHz speed grades. Increased leakage current specifications in Table 6 from 10 to 30 µA. Updated power consumption specifications in Table 7. Reduced I/O power guidance in Table 7 from <20% to <5%. Added footnote 1 to Figure 9 and Figure 11. Removed CI and WT from Input Setup and Input Hold lists in Table 10; these are output-only signals. these are asynchronous inputs. mistakenly omitted in Rev 0. Updated Table 13 and Table 14 to reflect new L3 AC timing in Rev F devices. Corrected Note 10 in Table 16 and Table 17; this is an event pin, not an enable pin. Corrected entries for L3_ECHO_CLK[1,3] in Table 17; these are I/O pins, not input-only. Added Note 16 to Table 17; all No Connect pins must be left unconnected. Changed name of PLL_EXT to PLL_CFG[4] and updated all instances. Updated Table 18 to reflect PLL configuration settings for Rev F devices. Added dimensions D2 and E3 to Figure 20. Transposed dimensions D4 and E4 in Figure 21 (dimensions were reversed). information, including Figure 28.
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
60 Freescale Semiconductor
Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 11.1, “Part Numbers Fully Addressed by This Document.” Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision level code which refers to the die mask revision number. Section 11.2, “Part Numbers Not Fully Addressed by This Document,” lists the part numbers which do not
1.1 Removed reference to Note 4 for DTI signals in Table 15 and Table 16: these signals are unused in 60x
bus mode and must be pulled down (see Note 13); they are not ignored. Improved precision of die and package dimensions in Figure 20 and Figure 21. 2 Corrected entries in T able 17 for 33 MHz and 50 MHz bus frequencies with multipliers of 24x and higher. Corrected typographical errors in heatsink selection example in Section 9.8.3, “Heat Sink Selection Example.” Removed erroneous instances of PLL_EXT signal name and changed remaining instances of PLL_CFG[0:3] to PLL_CFG[0:4]. (These were artifacts from older revisions; see entry for Rev 1.0.) Corrected erroneous instances (artifacts) mentioning 1.6 V core voltage. Core voltage for devices completely covered by this revision (and revisions 1. x) of this document is 1.3 V. Corrected errors in PLL multipliers in Table 17: 32x and 25x are not supported ratios, 3x and 4x are supported, 10.5x and 12.5x PLL settings were incorrect. Replaced notes at bottom of Table 17 (erroneously missing in revisions 1. x). Updated coplanarity specifications in Figure 20 and Figure 21 from 0.2 mm to 0.15 mm. 3 Added Revision G (Rev 3.4) devices to specifications. Added new PowerPC trademarking information. 4 Added substrate capacitor information in Section 8.3, “Substrate Capacitors for the MPC7445, 360 CBGA,” and Section 8.6, “Substrate Capacitors for the MPC7455, 483 CBGA.” Clarified maximum and typical L3 clock frequency in Section 5.2.3, “L3 Clock AC Specifications”; typical L3 frequency now stated as 250 MHz based on changes to L3 AC timing. Significantly changed L3 AC timing in Table 12 and T able 13. These changes reflect both updates based on latest characterization and error corrections (effects of non-zero L3OH values were incorrectly documented in earlier revisions of this document). Clarified address bus pull-up resistor recommendations in Section 9.6, “Pull-Up/Pull-Down Resistor Requirements.” Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 9.6, “Pull-Up/Pull-Down Resistor Requirements.” Modified Table 9, Figure 5, and Figure 6 to more accurately show when the mode select inputs (BMODE[0:1], L3VSEL, BVSEL) are sampled and AC timing requirements. Figure 20 and Figure 22: Updated/corrected dimensions in mechanical drawings. 4.1 Document tempate update. Table 20. Document Revision History (continued)
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1 Freescale Semiconductor 61 fully conform to the specifications of this document. These special part numbers require an additional document called a part number specification.
11.1 Part Numbers Fully Addressed by This Document
Table 21 provides the Freescale part numbering nomenclature for the MPC7455.
11.2 Part Numbers Not Fully Addressed by This Document
Parts with application modifiers or revision levels not fully addressed in this specification document are described in separate part number specifications which supplement and supersede this document; see Table 22 through Table 25. Table 21. Part Numbering Nomenclature
- Processor core frequencies supported by parts addressed by this specification only. Parts addressed by part
number specifications may support other maximum core frequencies.
- The X prefix in a Freescale part number designates a “Pilot Production Prototype” as defined by Freescale SOP
may still occur while shipping pilot production prototypes. Table 22. Part Numbers Addressed by XPC74 x5RXnnnLC Series Part Number Specification (Document
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
62 Freescale Semiconductor
11.3 Part Marking
Parts are marked as the example shown in Figure 31. Figure 31. Part Marking for BGA Device Table 23. Part Numbers Addressed by XPC74 x5RXnnnNx Series Part Number Specification (Document Table 24. Part Numbers Addressed by XPC74 x5RXnnnPx Series Part Number Specification (Document Table 25. Part Numbers Addressed by XPC74 x5RXnnnSx Series Part Number Specification (Document MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code.
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1 Freescale Semiconductor 63 THIS PAGE INTENTIONALLY LEFT BLANK
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