XC6401

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MT6516 Design Notice V1.0

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Copyright © MediaTek Inc. All rights reserved. 3 OutlineOutline ▪ MT6516 Main Features & Package ▪ Design Notice – MT6516 schematic design notice – PMIC MT6326 design notice – Audio part design notice – Speech part design notice – Camera design notice – Display design notice – DDR memory layout rule – USB 2.0 high speed design notice ▪ Factory Mode and Engineer Mode ▪ Download and META Link ▪ MT6516 Memory Support Plan ▪ Appendix - Peripherals Design Notice – WIFI/BT Co-module Application Note – MT3326 GPS application note – DTV part design note – FM design notice Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 4 ▪ Separate Application (ARM9) and hard real-time Modem (ARM7) ▪ Multi-Cores with HW coprocessors SoC – Application: ARM926EJS 416MHz – Modem: ARM7 (52MHz/104MHz) + 2 DSP(104MHz) – CEVA DSP (312MHz) for video and unpredictable multimedia application on Smartphone ▪ 65nm process. Ultra low power design. ▪ Graphics, Display, Image, Camera, Video multimedia hardware accelerators. – 2D Graphics - support Window Mobile Bitblt function – 3D Graphics - Support OpenGL ES 1.1 Common/Common Lite profile – 3D Performance: fill rate = 32M, triangle rate = 3.7M ▪ Wide range of resolution up to WVGA size ▪ Various display Interface Support – 8080 host IF (MIPI DBI) – 8/9/16/32-bit Serial IF – RGB interface (MIPI DPI) – MIPI DSI interface ▪ High Performance Memory controller @ 104MHz, support – 32-bit / 16-bit LP-DDR SDRAM – 4 chip selects : support up to 4 DRAM devices – NAND-boot supported – NAND data storage supported ▪ Peripherals –D u a l S I M – 3 x SDIO, 3 x I2C, 1 x I2S, 4 x UART – 1-wire interface, 7 x PWM – 8 x 8 Key Matrix – Touch panel interface – USB 2.0 high speed integrate with PHY. MT6516 Main FeatureMT6516 Main Feature Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 5 MT6516 Design Package Building BlocksMT6516 Design Package Building Blocks MCP Memory 1G DDR 2G NAND 2.8㛤 LCD QVGA Camera 5MP Autofocus T-Flash Card MT6140D+SKY77344 EDGE Transceiver MT5151 DTV Receiver MT3326 GPS Receiver MT6611 & MT5921 WiFi/BT Co-module Apps. Processor ARM926EJS 416Mhz Modem MCU ARM7 104Mhz Multimedia ASIC AR1000 FM MT6326 PMIC TI BQ27500 Smart battery (Optional) SIM Interface (Dual SIM capable) UART SDIO UART SDIO BPI I2C I2C Parallel Camera I/F EMI NFI I2C SDIO LCM I/F 3D Scaler MP3 H.264 JPEG codec Internal Memory Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 6 MT6516 PackageMT6516 Package CA1A (Max.)be1 / e2NED Substrate Thk. Stand Off Package Thk. Ball Dia. Ball Pitch Ball Count Body Size Table 1 Definition of TFBGA 15mm*15mm, 564-ball, 0.378 mm pitch Package (Unit: mm) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. Design Notice Design Notice -- MT6MT6516 Schematic Design Notice516 Schematic Design Notice Copyright © MediaTek Inc. All rights reserved. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 8 Schematic Notice (1/7): BootSchematic Notice (1/7): Boot--up selectionup selection H(DVDD)L ( G N D ) IONEJTAG Enable one JTAG functionDisable IBOOT boot from external memor boot from bootrom SECU_EN Enable secure booting Disable IADMUX ADMux memory device AD-Demux memory device ICORESIGHT Coresight enable, Coresight disable FSOURCE burn efuse Normal 1JO )=-

MT6516 currently only support DDR memory, so this selection always choose GND
Connect FSOURCE to GND by 0ohm, otherwise the UUID number will be unstable. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 9 Schematic Notice (2/7)Schematic Notice (2/7) The AVDD Power must follow the connection show above to avoid the influence between AFE, RFE and MBUF Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 10 Schematic Notice (3/7)Schematic Notice (3/7) Connect AU_VCM_NO to GND Add 2 capacitors (1uF, 0.1uF) in AVDD12_PLL Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 11 C504 V T503 M1005C080MTACB V T505 M1005C080MTACB V T504 M1005C080MTACB V T506 M1005C080MTACB V T507 M1005C080MTACB R507 47K R502 47K R504 47K R503 47K R505 47K R506 47K V T501 M1005C080MTACB V T502 M1005C080MTACB MCDA31 MCDA11 MCCM01 MCCK1 MCDA01 MCDA21 J501 SD_CARD_SOCKET (SKT SD/MMC Standard Ty TF_5015880801-A DAT21 CD/DAT32 CMD3 VDD4 CLK5 VSS26 DAT07 DAT18 Shield 11Shield 10 Shield 12 Shield 9 VDD

For better interoperability and stability, please reserve 47k ohm in each memory card interface line. Schematic Notice (4/7)Schematic Notice (4/7) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 12 Schematic Notice (5/7)Schematic Notice (5/7) Add a diode between MT6516 PWR_KEY and MT6326 PWRKEY MT6516 MT6326 PMIC Power Key Bottom Add a diode and a EINT to MT6326 PWRKEY Add a 1k resistor to avoid ESD damage. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 13 U100E tk65_18 MT6516-564/P0.53/B0.27(15X15)/IAC JTRST_BAD34 JTCKAD38 JTDIAB36 JTMSAC33 JTDOAC35 JRTCKAB34 J2TRST_B AM32 J2TCK AK30 J2TDI AN33 J2TMS AP34 J2TDO AR35 J2RTCK AL31 IONEJTAG T38 JZTRST_B 16 JZTDO 16 JZTMS 16 JZTDI 16 JZTCK 16 JTDI16 JTDO16 JTCK16 JZRTCK 16 JTMS16 JRTCK16 JTRST_B16 IONEJTAG 16 Schematic Notice (6/7) :Debug PortSchematic Notice (6/7) :Debug Port ARM9 (AP side) JTAG ARM7 (Modem side) JTAG Use only one JTAG to control AP and modem side MCU Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 14 Schematic Notice (7/7) : NFI InterfaceSchematic Notice (7/7) : NFI Interface ▪ To support 1.8 V NAND MCP, you need to – Connect VDD33_LCD of BB part to 1.8 V – Check if LCM module IO can support 1. 8V first. Connect LCM IO power pin (VDDIO) to 1.8 V (see LCM Selection Guide to 1.8 V LCM section) BBBB LCM IOLCM IO ‧Beware that NAND flash, parallel LCM, and VDD33_NLD must use same power domain ! Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 15 RF IQ Connection ( Remember add 510ohm RF IQ Connection ( Remember add 510ohm Between Baseband and MT6140D)Between Baseband and MT6140D) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 16 Reset Button Design Suggestion Reset Button Design Suggestion 1. Basically, the MT6516 phone don’t need reset button. (Users remove battery when system hang) 2. There are two kinds of suggestion design of reset button. 1. Only add a pull low button on SYSRST_B pin 1. Advantage : cost effective 2. Disadvantage : User must press pwrkey to restart system 2. Add a reset chip on pwrkey pin and SYSRST_B pin. 1. Advantage : User can press reset then direct restart the phone. 2. Disadvantage : Need a extra reset chip PWRKEY SW702 KSW

12 SYSRST_B

Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 17 Default UART Dispatch NoticeDefault UART Dispatch Notice UART1 UART3 USB Port COPY HERE UART2 UART4 Download Bootloader, META Link, Production Line Test Point User Define, Default Use for AGPS User Define, Default Use for Bluetooth Data Log for Debugging, Boot-Up Selection and Setting. Modem side META link. Download Image BIN file, Active Sync, Mass Storage, RNDIS Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 18 Reference Power DistributionReference Power Distribution VDD33 VDD33_TRACER VDD33_MIPI/MIPI_TX/MIPI_RX VDD33_I2C (Camera) VDD33_MC0/1/2 VDD33_NLD VDD33_SPI VDD33_EMI (6 Balls) AVDD30_VSIM AVDD30_VSIM2 AVDD33_USB AVDD12_USB VCORE 1.3V VDD 2.8V VSDIO VM 1.8V VSIM VGP VUSB 3.3V VCAM_A VDDK (52 Balls) VDD33_CAMERA ‧MT6326 ‧MT6516 Core Power USB Core Power General IO ETM IO MIPI Power SPI Power NAND/LCM Power EMI Power (LPDDR) Camera I/O Power SCL1/SDA1 Power SIM1 Power SDIO1/SDIO2/SDIO3 Power SIM2 Power USB PHY Power Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 19 MT6516 reference phone PCB layer defineMT6516 reference phone PCB layer define -BZFS /P /BNF \`%FGJOF .BUFSJBM 4VHHFTUJPO %JF $PO TVHHFTU UIJDLOFTT NJM 7JB cc c SolderMask SolderMask cc 0.4 cc c Add Plating plating 1C O M P ( L 1 )c3'5SBDF Copper foil 0.5 oz H oz+plating c 1.4 cc c c PP PP 1080 65% 4.3 2.82 2L 2 c4JHOBM Copper foil 1.0 oz 0.50 oz+plating c 1.3 cc c c CORE PP 1080 65% 4.3 2.82 3L 3 c(/% Copper foil 1.0 oz Copper 1.0 oz c 1.3 cc c c PP FR-4 Core 4mil 4.3 4 4L 4 c3'5SBDF Copper foil 1.0 oz Copper 1.0 oz c 1.3 cc c c CORE PP 7628 50% 4.3 8.38 5L 5 c(/% Copper foil 1.0 oz Copper 1.0 oz c 1.3 cc c c PP FR-4 Core 4mil 4.3 4 6L 6 c4JHOBM Copper foil 1.0 oz Copper 1.0 oz c 1.3 cc c c CORE PP 1080 65% 4.3 2.82 7L 7 c4JHOBM Copper foil 1.0 oz 0.50 oz+plating c 1.3 cc c c PP PP 1080 65% 4.3 2.82 8S O L D ( L 8 )c3'5SBDF Copper foil 0.5 oz cc c Add Plating plating H oz+plating c 1.4 cc c SolderMask SolderMask cc 0.4 Board Thickness =1.00mm +/- 10%mm cc c c c 39.06 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 21 MT6326 PMICMT6326 PMIC Base Band Processor 2G Transceiver Memory RAM Flash Boost Converter 1. Back Light 2. Flash Light 3. USB OTG KP LED Driver (Open Drain) Vibrator Driver (Open Drain) Class-D Audio Amplifier 1 WIFI BlueTooth Camera Sensor (AF) Audio Switch Charger Controller Reset Generator I2C M 1 2 3 4 5 6 7 8 9 0 # LCM Module USB Device SIM1 Class-D Audio Amplifier 2 Essential LDOs VA VIO VRTC1 VRTC2 VSIM1 VGP2

2 DC-DC

(For Vcore) DVFS DC-DC (For Vmem) 2G Transceiver LDOs VRF, VTCXO Basic Feature LDOs VUSB, VBT VCAM_D VCAM_A Extra LDOs WIFI General Purpose Vcore2 1.2(0.9_1.8V(1.5)/600mA Vm 1.8_2.8V/600 mA VIO_2.8V/150mA VA_2.8V/150mA Vrtc1_2.8V/2mA VUSB 3.3V/100mA VBT 2.8_3V/100mA VCAM_D 1.3_1.5_1.8_2.8V/100mA VCAM_A 1.8_2.5_2.8V/250mA VRF 2.8V/250mA VTCXO 2.8V/50mA Vrtc2_1.2_1.5V/0.1mA Backup Battery VWIFI2V8 2.8_3_3.3V/150mA VWIFI3V3 2.8_3_3.3V/300mA MT6326 Control 3G Transceiver LDOs VPA 1.3~3.4V/600mA 3G PAAnalog Switch SDIO Device VSDIO 2.8_3.3V/350mA 3G TransceiverV3GRX 2.8_3_3.3V/100mA V3GTX 2.8_3_3.3V/200mA DC-DC (For 3G PA) PMOS +Rsense Charger In Current Sink *8 (Current sharing) (MUX) Vcore1 1.2(0.9_1.8V(1.5)/600mA 2-in-1 Receiver VGP1 1.8/2.8/100mA SIM2 VSIM1 1.8_3V/100mA VSIM2 1.8_3V/100mA Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 22 MT6326 PMIC LDOMT6326 PMIC LDO Regulator Output Voltage Output Current Output Components Notes VCORE 0.9~1.35 VCORE 2 0.9~1.35 VM 1.8 V3GPA 1.3~3.4 600 2.2uH + 4.7uF VBAT should keep 600mV higher than V3GPA to keep good regulation. V3GTX 2.5/2.8/3/3.3 200 4.7uF V3GRX 2.5/2.8/3/3.3 100 4.7uF VRF 2.8 250 4.7uF VTCXO 2.8 50 1uF VA 2.8 150 4.7uF 'PS"7%% '.QPXFSSFRVJSFNFOU VWIFI3V3 2.5/2.8/3/3.3 300 4.7uF VWIFI2V8 2.5/2.8/3/3.3 150 4.7uF VIO 2.8 150 1uF 'PS7%%BOEQFSJQIFSBM*0SFRVJSFNFOU VSIM 1.8/3.0 100 1uF VUSB 3.3 100 1uF VSDIO 2.8/3 300 4.7uF 2.8/3.0 100 1uF VRTC 1.5/1.2 0.1 1uF BAT_BACKUP 2.8 2 1uF #BDLVQCBUUFSZ Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 23 VBAT Input FilterVBAT Input Filter ▪ VBAT input should reserve enough filter to prevent interference to RF performance. ▪ All above component should be as close to MT6326 IC as possible

In red frame , all component should be in shielding case. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 24 ClassClass--D Audio Amplifier Output FilterD Audio Amplifier Output Filter ▪ Reserve 2 stage filter at output stage of Class-D to prevent interference to RF performance. ▪ 1st stage filter should be close to IC, 2nd stage filter should be close to loud speaker. ▪ All the traces from IC to 2nd stage filter should not exposed to prevent interference to RF performance. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 25 ClassClass--D : 2D : 2--inin--1 Receiver Function1 Receiver Function ▪ MT6326 has 2 in 1 receiver function , when use external amplifier , must connect RECIN_P and RECIN_N. ▪ The typical value of R1 and R2 are 20 ohm each , and suggest R3 and R4 to be 4 ohm (32–20–8=4) ▪ Due to value variation of R1 and R2 are higher , so maybe suffer audio volume. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 26 ClassClass--D : Audio Amplifier Power OutputD : Audio Amplifier Power Output ▪ Although MT6326 class-D power output is 1W at 8 Ω , because congenital power source limitation is 4.2V from VBAT , but compare with other discrete amplifiers , MT6326 equal other amplifier in performance. TI Poutput Profile Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 27 Boost1 For Parallel Backlight LCM or other 5V Boost1 For Parallel Backlight LCM or other 5V requirementrequirement ▪ Reserve filter at input/output to prevent interference to RF performance. ▪ L200/L201/C205/C279 should be in shield case and close near MT6326 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 28 Boost2 For Serial Backlight LCMBoost2 For Serial Backlight LCM ▪ Reserve discrete B/L driver to prevent any improper design causing interference to RF performance.

In this red frame, all components are reserved only. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 29 IC Protection: PWRKEY and BAT_ONIC Protection: PWRKEY and BAT_ON Please reserve 1k resistor on phone PCB to protect PWRKEY no matter if PWRKEY connect to any I/O connector or not. Please reserve 1k resistor on phone PCB to protect BAT_ON pin if BAT_ON is used to detect battery. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 30 IC Protection: VBATIC Protection: VBAT I/O Cable MT6326 Power Supply Phone GND VBAT Reserve 1. 22uF Capacitor 2. Zener diode on phone. Reserve 1000uF or above capacitor at the output of power supply, and at the end of connector cable. MT6326 has lower VBAT voltage rating. (Max. 4.3V.) Some protection should reserve to prevent the damage by voltage surge.

Design notice in Phone side: 1. At least 22uF capacitor. 2. Add Zener diode (5.1V) to protect the IC against low frequency voltage surge. Put it between battery connector and MT6326. Notice: If using IO connector or test point to supply VBAT for download, manufacture, or repair, should let VBAT trace passing zener diode and 22uF capacitor before entering IC. Notice: Using 5.1V zener will introduce some leakage when VBAT = 4.2V.
Design notice in Power Supply side: Add 1000uF (or above) capacitor at the output of the power supply to reduce the voltage bounce caused by long power cable. And the power cable should be as short as possible. Also add 1000uF (or above) capacitor at the end of power cable (near phone side). Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 31 IC Protection: CHRINIC Protection: CHRIN MT6223/35/38 /MT6326 6.8V9VCharger OVP Point 30V15VMax. Charger Input External OVP/OCP MT6305 /MT6318 VCHG R201 0 U202 BQ24316 2 7 4 5 IN VSS ILIM OUT NC /fault /CE VBAT VBAT TO CHRIN C235 1u (16V 0805) CHRIN R202 220K R205 25K C205 1uF F201 FUSE(1A 0603) External OVP/OCP: NC Notice : You can get better charger protection by using external OVP/OCP device. OVP/OCP Qualified Vendor : 1. TI – BQ24314 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 32 IC Protection: OVP + ChargerIC Protection: OVP + Charger MT6223/35/38 /MT6326 6.17V(APL3206) 6.8V(APL3206A)9VCharger OVP Point 30V15VMax. Charger Input External OVP/OCP MT6305 /MT6318 OVP/OCP + Charger Qualified Vendor : 1. ANPEC - APL3206 QBI External OVP + Charger : Notice : You can get better charger protection by using external OVP/OCP device. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 33 Bypass Capacitor: Bypass Capacitor: VcoreVcore and VMand VM ▪ Reserve enough bypass capacitors both at Vcore and VM to obtain good system stability. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 34 DVDD12_MIPI Power ConnectionDVDD12_MIPI Power Connection ▪ MT6326 Vcore1 default is 1.3V , and MIPI_1.2V power spec. is 1.1~1.3V , so if need to use MIPI could connect Vcore2(if not used). Besides , must add external LDO for MIPI_1.2V. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 35 Bypass Capacitor: Bypass Capacitor: Layout Rule For Vcore ▪ Due to MT6516 have many Vcore (VDDK) balls , and these balls scatter around package of MT6516. Please put bypass capacitor around MT6516 to increase system reliably.

●Current SourceCurrent Source
●Current SourceCurrent Source Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 36 Bypass Capacitor: AVDD and VDDBypass Capacitor: AVDD and VDD ▪ Reserve required input filter for ABB as specified in left schematics. ▪ AVDD28_MBUF suggest to connect to VTCXO. ▪ Reserve 1uF for I/O power input. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 37 Layout Notice: Charging PathLayout Notice: Charging Path ▪ Charging related component (U204, Rsense, R219) should be close to battery connector. ▪ Minimum trace width are marked on the schematics above. ▪ ISENSE and BATSNS should be connected as the figure above. ▪ The trace from Rsense to battery connector (Marked in Red) should not share with other VBAT traces. ▪ ISENSE/BATSNS should be routed as differential traces which are away from noisy signals. F200 FUSE(1A 0603) 40mil ISENSE BATSNS CHRIN GATDRV VBAT Rsense 0.2 6mil R219 10K U204 APL3206 QBI ACIN1 ACIN2 OUT 7OUT 8 GND3 VBAT 4 GATDRV 5 CHRIN 6 EP 6mil VCHG 6mil 6mil6mil 40mil 40mil 40mil Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 38 ▪ The exposed pad of the charger OVP IC should connect to a large copper ground plane to get good thermal performance. ▪ The exposed pad should has at least 6 GND via connecting to inner layer. Exposed pad to a large copper ground F200 FUSE(1A 0603) 40mil ISENSE BATSNS CHRIN GATDRV VBAT Rsense 0.2 6mil R219 10K U204 APL3206 QBI ACIN1 ACIN2 OUT 7OUT 8 GND3 VBAT 4 GATDRV 5 CHRIN 6 EP 9 6mil VCHG 6mil 6mil6mil 40mil 40mil 40mil Layout Notice: Charger OVP ICLayout Notice: Charger OVP IC Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 39 Layout Notice: VBAT TracesLayout Notice: VBAT Traces ▪ The VBAT for the 5 blocks show above (Class-D, Buck converter, Boost1, Boost2 converter and Analog LDOs) should star-connect to the bulk capacitor near battery connector. Class-D Buck Converter Analog LDOs Boost1 Converter Boost2 Converter Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 40 Layout Notice: VBAT TracesLayout Notice: VBAT Traces RF PA Boost2 Class-D Amplifier Charging path Buck and boost converters Bulk capacitor near Battery Connector Analog LDOs ▪ Star-connect different VBAT group to BATTERY Connector directly Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 41 ClassClass--D GNDD GND ▪ The GND for Class-D should isolated carefully. L1 L2 L3 L4 L5 L6 L7 L8 GND merge, other GND (Mark by Black) should be isolate. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 42 Layout Notice: GND_VREF TracesLayout Notice: GND_VREF Traces ▪ VREF capacitor (1uF) should be close to IC. ▪ GND_VREF (GND for VREF) should isolate carefully. Pin67 (GND_VREF) Capacitor for VREF The trace should connect to GND of battery connector The trace should isolated and protected by GND Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 43 ▪ The output trace (Marked in above schematics) should be differential, and protected by GND. ▪ 1st filter should be as close to IC as possible. (As the left figure showed.) ▪ The trace width should be – 8 ohm speaker: 25 mil. – 4 ohm speaker: 40 mil. Layout Notice: ClassLayout Notice: Class--D OutputD Output Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 44 ▪ Components should be as close to IC as possible. ▪ L200/D200/L201/C205/D200/C208 should be close and parallel to each other. ▪ The direction of L200/D200 should arrange as the arrowhead in left figure. ▪ Must add D204 to prevent feedback of VBUS when turn off boost1. Layout Notice: Boost1Layout Notice: Boost1 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 46 OutlineOutline ▪ Analog gain setting ▪ RC value ▪ PCB layout ▪ Audio feature – MP3 decoder – 3D surround effect –E Q 2 . 0 – Audio AGC – Audio Compensation Filter ▪ For audio features, please refer to – L1_Audio_Design_and_Interface.pdf – Audio_Post-Processing_Interface_V1.13.pdf – Audio Customization v1.0.pdf Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 47 Audio Block DiagramAudio Block Diagram "6@.065- "6@.0653 "6@065@1 "6@065@/ "6@'.*/- "6@'.*/3 .69 .69 4UFSFPUP .POP '.". SBEJP DIJQ 7PJDF 4JHOBM "VEJP 4JHOBM 7PJDF "NQ "VEJP "NQ3 "VEJP "NQ- "6@7*/@1 "6@7*/@/ "6@7*/@/ "6@7*/@1 .697PJDF 4JHOBM "VEJP -$)%"$ "VEJP 3$)%"$ 7PJDF %"$ 7PJDF "%$ 1(" Audio Buffer Voice Buffer Microphone PGA Free Datasheet http://www.Datasheet-PDF.com/

Audio buffer – 112= -1dB –Positive gain results distortion
External amplifier –increasing external amplifier gain for louder volume – Earphone mode
Audio buffer – 112= -1dB –Positive gain results distortion
External RC trade-off WPJDF #VGGFS <E#> BVEJP #VGGFS <E#> TFUUJOHJO FOHJOFFSJOH NPEF Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 49 External RC valueExternal RC value ▪ RC value on mp3_out path 1) Bandwidth: 2) Amplitude degradation: 3) Larger resistance, better bass, smaller volume; 4) Larger capacitance, better bass, higher cost, larger PCB area. 5) Pout < Earphone speaker rated power 6) example:

(R1, C, Fc, Amplitude) – (100ohm, 47uF, 25.65Hz, -12.3dB) RCfc 2log20][ RR RdBamplitude +=+ C 47u (4V) C 47u (4V) 150 HP Jack1 150 R1 AGND MP3_OUTR MP3_OUTL R1C R=R1+R2 )( 2 R VP rms out = Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 50 External RC valueExternal RC value ▪ Different types of capacitors have different distortion. – distortion: Tantalum cap. > MLCC X5R > MLCC Y5V – Don’t use MLCC Y5V in audio path/ mic0/ FM_IN

Capacitors’ THD+N vs. Frequency are showed as below:
green: X5R (+/-10%); Audio Precision Analyzer Rin=100kohm
red: X5R (+/-10%); Audio Precision Analyzer Rin=100kphm
blue: Y5V (+80%, -20%); Audio Precision Analyzer Rin=300ohm
cyan: Y5V (+80%, -20%); Audio Precision Analyzer Rin=300ohm MediaTek 02/21/08 21:55:08EXTERNAL SOURCE THD+N VS FREQUENCY cap_THD+NvsFreq.at27 ColorSweep Trace Line Style Thick Data Axis Comment 1 1 Blue Solid 3 DSP Anlr.THD+N Ratio A Left 6238EVB (200mVrms, AA=100 2 1 Cyan Solid 3 DSP Anlr.THD+N Ratio A Left 6238EVB (200mVrms, AA=300 5 1 Green Solid 3 DSP Anlr.THD+N Ratio A Left 6235EVB (200mVrms, AA=100 7 1 Red Solid 3 DSP Anlr.THD+N Ratio A Left 6235EVB (200mVrms, AA=300 -120 -100 -80 -60 -40 -20 d B 20 20k50 100 200 500 1k 2k 5k 10k Hz Free Datasheet http://www.Datasheet-PDF.com/

HP EINT can’t be on earphone path. – Permissible reverse voltage: – The reason of damage by reverse voltage
Reverse voltage will damage Ta2O5,
After Ta2O5 is broken, there is large current passed through tantalum capacitor. Free Datasheet http://www.Datasheet-PDF.com/

An extra pin for HP EINT and accessory need a pull-low resister. – 6-pin earphone jack
Two extra pull-low resistors on CH-L/R B301 BLM18BD252SN1 0603 B300 BLM18BD252SN1 0603B302 BLM18BD252SN1 0603 C325 TCTP0J476M8R-Y2 CAP-0805 VR315 0402 VR314 0402 VR316 0402 C326 1nF 0402 EINT7_HEADSET2 FM_ANT 14 C327 1nF 0402 C329 1nF 0402 C330 2.2uF 0402 R381 4.7k 0402 R308 100 0402 MP3_OUTR2,3 C324 33pF 0402 MP3_OUTL2,3 C328 33pF 0402 R312 100 0402 VR317 0402 C323 100pF 0402 AU_MOUTR2,3 AU_MOUTL2,3 MP3_OUTL 2,3 MP3_ER R314 1K 0402 MP3_OUTR 2,3 L306 BLM18BD252SN1 0603 MIC_HP R380 4.7k 0402 VR318 0402 J302 earphone PHONEJACK(AJR4R-6KXXX1) GND1 MIC2 OUTR3 OUTL4 NA5 NA6 C322 TCTP0J476M8R-Y2 CAP-0805 EINT7_HEADSET: H= earphone plug in L= earphone plug out Free Datasheet http://www.Datasheet-PDF.com/

protected audio R & L stereo trace by GND separately. In headset mode, please separate L/R channel and microphone trace by GND. Free Datasheet http://www.Datasheet-PDF.com/

Separated GND of CH-L and CH-R.
connect the GND of CH-L and CH-R at the end of earphone jack. Not connect the GND at earphone microphone. – (3) The bead at FM ANT on earphone path may degrade crosstalk about 15dB.
Choose bead with low DRC bead and good THD+N
It is a trade-off between FM feature and crosstalk performance. MIC+MIC+ HP HP L R x O Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 55 I/O connector (10pins)I/O connector (10pins) ▪ UART + USB + Earphone TP901 FM_ANT7 T911 ESD9X5.0ST5G T910 ESD9X5.0ST5G T909 ESD9X5.0ST5G UTXD11 XMP3_L3 XMP3_R3 L903BLM18BD252SN1 L902BLM18BD252SN1 L904BLM18BD252SN1 C904 1n L901 BLM18BD252SN1-(0603) D903 SDM20U40-7/RB520S-30 1 2 R916 47K VDD C903 1n XMIC3 V T907 M1005C080MTAAB J903 Mini 10pin I/O A TXD1 VCHG+2 RXD3 D-4 GND_FM5 D+6 MP3_L7 MIC8 MP3_R9 AccDet10 GND314 GND211 GND012 GND113 URXD11 USB_DM1 VCHG/USB_PWR R318 1K HEADSET DETECTION EINT0_ACC_DET1 USB_DP1 C907 33p V TN904 AVSC18S05E007 C908 33p C906 33p TP905TP906 C905 1n Free Datasheet http://www.Datasheet-PDF.com/

Tuning external audio amplifier ON/OFF delay time
mp3_outL/R to external amplifier input must add coupling capacitor to avoid voltage drop. – Earphone mode
Turn on de-pop function by software
Tantalum capacitor +/- reverse mounting. Free Datasheet http://www.Datasheet-PDF.com/

Audio buffer gain <112
Increase external audio amplifier gain – Earphone mode
Audio buffer gain <112
decrease resistance on earphone path – Increase capacitanc e for good bandwidth – Microphone PGA
uplink speech volume – nvram_default_audio.c: #define GAIN_NOR_MIC_VOL3 – Engineering mode: audio, norm al mode. microphone, volume3
sound recorder/video recording volume – nvram_default_audio.c: #define GAIN_NOR_MIC_VOL4 – Engineering mode: audio, norm al mode. microphone, volume4
FM recorded file playback – Increase FM_record_PGA if FM playback volume is small. – mcu\\1audio\\afe2.c: #defi ne FM_RADIO_RECORDING_VOLUME Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 59 New Proposed Microphone CircuitNew Proposed Microphone Circuit ▪ Advantage – 10uf capacitor is not needed any more – Less passive components are needed ▪ Circuit: Normal mode C306 33pF C305 33pF MICN02 C310 100nF 0402 C300 100nF 0402 MIC+ L300 2000@1GHz R300 0402 R302 0402 MICP02 VR300 0402 AU_MICBIAS_P2 MIC300 MIC MIC/OD4/ID1 R301 10K Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 60 New Proposed Microphone CircuitNew Proposed Microphone Circuit ▪ Circuit: Headset mode AU_MICBIAS_P C318 100nF 0402 R303 0402MICN12 MICP12 C311 100pF 0402 C314 100nF 0402 R317 10k 0402 C321 33pF 0402 R306 0402 Headset GND C332 33pF 0402 R318 0402 MIC_HP AUXADIN52 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 61 New Proposed Microphone CircuitNew Proposed Microphone Circuit ▪ Layout consideration-Normal mode C306 33pF C305 33pF MICN02 C310 100nF 0402 C300 100nF 0402 MIC+ L300 2000@1GHz R300 0402 R302 0402 MICP02 VR300 0402 AU_MICBIAS_P2 MIC300 MIC MIC/OD4/ID1 R301 10K Should be routed in differential Should be routed in differential Connect the 4 GND together and then connect to the main GND by a single via Rload Vr Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 62 New Proposed Microphone CircuitNew Proposed Microphone Circuit ▪ Layout consideration-Headset mode AU_MICBIAS_P C318 100nF 0402 R303 0402MICN12 MICP12 C311 100pF 0402 C314 100nF 0402 R317 10k 0402 C321 33pF 0402 R306 0402 Headset GND C332 33pF 0402 R318 0402 MIC_HP AUXADIN52 Connect the 4 GND together and then connect to the main GND by a single via Should be routed in differential Should be routed in differential Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 63 How to Optimized How to Optimized RloadRload ▪ The Rload can be calculated by the follow procedure – Measure the voltage on the microphone MIC_P in a quite environment – Select a Rload to let Vr has almost the same voltage as MIC_P Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 65 Camera Design Note Camera Design Note –– Parallel InterfaceParallel Interface ▪ All camera pins are dedicated ▪ Layout notice – CMMCLK, CMPCLK need to be well shielded by GND plane ▪ BB side power level – VDD33_CAMERA (AJ9, AK10) = Camera side IO level DOVDD VCAM_D R2 4.7K SCL SDA CMDAT9 CMDAT0 CMDAT8 CMDAT7 CMDAT5 CMDAT4 CMDAT3 CMDAT2 CMDAT1 CMDAT6 CMRST CMSTROBE CMHREF CMVREF CMPDN Hirose FX12B-40P-0.4SV AVDD1 DVDD2 DOVDD3 DGND4 AGND5 STROBE6 SIOD7 SIOC8 RESETB9 VSYNC10 HSYNC11 PWDN12 MCLK13 PCLK14 DATA915 DATA816 DATA717 DATA618 DATA519 DATA420 DATA321 DATA222 DATA123 DATA024 DGND25 DGND 26 MDP1 27 MDN1 28 DGND 29 MCP 30 MCN 31 DGND 32 MDP0 33 MDN0 34 DGND 35 R1 4.7K RCP RDN0 RDP0 RCN RDN1 RDP1 CMPCLK VCAM_DVCAM_A + 1 + 3 CMMCLK VCAM_A SIOCAG5SCL1 RESETBAJ7CMRST DATA0 ~ DATA9 AV2,AL9,AT4,AM8,AU3 AN7,AN5,AK8,AP4,AL7 CMDAT0~CMDAT9 STROBEAN3CAM_STROBE PWDN SIOD MCLK PCLK HSYNC VSYNC Camera side AM4CMPDN AP2SDA1 AR3CMMCLK AG9CMPCLK AT2CMHREF AH8CMVREF MT6516 (Pin definition) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 66 Camera Design Note Camera Design Note –– MIPI (CSIMIPI (CSI--2) Interface2) Interface PWDNAM4CMPDN CAM_STROBE STROBEAN3 RESETBAJ7CMRST MDN0 MDP0 MCN MCP MDN1 MDP1 Camera side E1RDN0 E3RDP0 F2RCN G3RCP G1RDN1 H2RDP1 MT6516 (Pin definition) VCAM_D R2 4.7K SCL SDA CMDAT9 CMDAT0 CMDAT8 CMDAT7 CMDAT5 CMDAT4 CMDAT3 CMDAT2 CMDAT1 CMDAT6 CMRST CMSTROBE CMHREF CMVREF CMPDN Hirose FX12B-40P-0.4SV AVDD1 DVDD2 DOVDD3 DGND4 AGND5 STROBE6 SIOD7 SIOC8 RESETB9 VSYNC10 HSYNC11 PWDN12 MCLK13 PCLK14 DATA915 DATA816 DATA717 DATA618 DATA519 DATA420 DATA321 DATA222 DATA123 DATA024 DGND25 DGND 26 MDP1 27 MDN1 28 DGND 29 MCP 30 MCN 31 DGND 32 MDP0 33 MDN0 34 DGND 35 R1 4.7K RCP RDN0 RDP0 RCN RDN1 RDP1 CMPCLK VCAM_DVCAM_A + 1 + 3 CMMCLK VCAM_A ▪ All MIPI DSI pins are dedicated that connect from BB to LCM – 1 CLK Lane + 2 Data Lanes ▪ BB side TVRT (pin G5) connect 1.8K 1% resistor to GND and close to BB ▪ Layout notice – All signal pairs need to 50ohm impedance matching for single end and 100ohm for differential – All signal length need be equal a nd well shielded by GND plane ▪ BB side power level – VDD33_CAMERA (AJ9, AK10) = Camera side IO level DOVDD – DVDD12_MIPI (J7, K8) connect to VCORE(1.2V) – DVDD28_MIPITX (H8, J9), DVDD28_MIPIRX(J5), AVDD28_MIPITX (G7), and VDD33_MIPI (L11) connect to VDD (2.8V) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 68 Display InterfacesDisplay Interfaces ▪ Various Interface Support – 8080 host IF (MIPI DBI) – 8/9/16/32-bit Serial IF – RGB interface (MIPI DPI) – MIPI DSI interface ▪ High performance LCD controller enable wide range of display resolution – Landscape or Portrait mode. – From 128x96(SubQCIF) ~ 852x480(WVGA) ▪ Advance color processing – Embedded LCD Gamma correction table. – Color correction matrix. – true color support. – Contrast, brightness adjustment. – 6 overlay layers with per-pix el alpha channel and gamma table – 2x or 4x temporal dithering Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 69 LCM Design Note LCM Design Note –– CPU (Host) InterfaceCPU (Host) Interface ▪ LCM side must have FMARK(F_Sync) frame update HW pin and need to connect to LPTE(W3) for tearing free Tier-1 performance ▪ LCM side IOVCC reserve VMEM(1.8V) & VDD(2.8V) option for 1.8V NAND application ▪ BB side power level – VDD33_NLD (pin AA9, AC9, W9) = LCM side IOVCC level FMARK / F_SyncW3LPTE D17~D0 /RESET /RD RS /WR /CS LCM side AA5, AF2, AP6, AE3, AB8, AD4, AC7, AJ1, AH2, AL1, AG3, AF4, AC5, AK2, AD6, AJ3, AD8, AN1 NLD17~NLD0 W7LRSTB Y2LRDB Y4LPA0 AA1LWRB W1LPCE0B MT6516 (Pin definition) J500 LCD-44PIN-CON IOVCC1 VCI2 GND13 LED6A4 LED5A5 LED4A6 LED3A7 LED2A8 LED1A9 GND210 LCM_ID11 /CS12 /WR13 RS14 /RD15 /RESET16 D1717 D1618 D1519 D1420 D1321 D1222 D1123 D1024 D925 D826 D727 D628 D529 D430 D331 D232 D133 D034 BLC38 XL40 YD41 XR42 YU43 GND339 GND444 FMARK37 IM335 IM036 LED_CA4 LED_CA3 LED_CA2 LED_CA1 LED_CA6 LED_CA5 R505 LRSTB LPCE0B_MAIN_LCM LWRB LPA0 LRDB VR501 C501 2.2u NLD1 NLD10 NLD9 NLD8 NLD2 TP_Y- TP_X- NLD0 NLD7 NLD11 TP_Y+ TP_X+ NLD4 NLD6 NLD5 NLD13 NLD3 NLD12 NLD15 NLD14 NLD16 NLD17 ADC2_LCMID R513 C500 2.2uVR500 LPTE R504 NCGPIO29_MAIN_LCM_BLC VMEM VDD Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 70 LCM Design Note LCM Design Note –– RGB (DPI) InterfaceRGB (DPI) Interface ▪ RGB (DPI) interface separated into two groups – 3 wire (or 4 wire) SPI interface for LCM initial code setting – Image databus (Dedicated pins and connect from BB to LCM directly) ▪ Layout notice – DPICK, LSCK must well isolated by GND plane – All Image signal length need to be equal as best. ▪ BB side power level – VDD33_NLD (pin AA9, AC9, W9) = LCM side IOVCC(VDDI) level RSTW7LRSTB DCKAC1DPICK B0 ~ B5AL1,AH2,AJ1,AC7,AD4,AB8NLD8 ~ NLD13 G0 ~ G5AE3,AB6,AF2,AA5,AG1,Y8NLD14 ~ NLD19 R0 ~ R5 DENB HSYNC VSYNC SPI_CLK SPI_SDI SPI_CS LCM side AB2DPIDE AC3,AA7,AD2,AE1,AB4,Y6NLD20 ~ NLD25 W5DPIHSYNC AA3DPIVSYNC U5LSCK U1LSDA V4LSCE0B MT6516 (Pin definition) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 71 LCM Design Note LCM Design Note –– MIPI (DSI) InterfaceMIPI (DSI) Interface ▪ All MIPI DSI pins are dedicated that connect from BB to LCM – 1 CLK Lane + 2 Data Lanes ▪ F_Sync for MIPI DSI command mode connect to dedicated pin LPTE ▪ BB side TVRT (pin G5) connect 1.8K 1% resistor to GND and close to BB ▪ Layout notice – All signal pairs need to 50ohm impedance matching for single end and 100ohm for differential – All signal length need be equal and well shielded by GND plane ▪ BB side power level – VDD33_NLD (pin AA9, AC9, W9 ) = LCM side IOVCC(VDDI) level – DVDD12_MIPI (J7, K8) connect to VCORE(1.2V) – DVDD28_MIPITX (H8, J9), DVDD28_MIPIRX(J5), AVDD28_MI PITX (G7), and VDD33_MIPI (L11) connect to VDD (2.8V) F_Sync / TEW3LPTE TDN1B4PAD_TDN1 TCPB2PAD_TCP TCNC3PAD_TCN RESET TDP1 TDN0 TDP0 LCM side A3PAD_TDP1 W7LRSTB D2PAD_TDN0 C1PAD_TDP0 MT6516 (Pin definition) VCI_LCM LEDA LEDK GND1 DATAP02 DATAN03 GND4 DATAP15 DATAN16 GND7 CLKP8 CLKN9 GND10 VCI11 RESET12 GND13 LEDA14 LEDK15 GND17 F_Sync16 TDN1 TDP0 TDN0 TDP1 LPTE TCP TCN LCM_RST Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 73 OutlineOutline ▪ Overview ▪ High speed memory layout considerations –P l a c e m e n t – Suggested routing order – Ground/Power plane – Signal layout – Other general layout considerations ▪ Check list Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 74 Overview Overview DDR SDRAM signals ▪ We can categorize DDR SDRAM interfaces into 4 groups as follows. ▪ Signal quality could be degraded by any PCB layout issue. ▪ We must take care of different groups of DDR SDRAM. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 75 High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations ▪ It is recommended that the PCB layout of memory interface is the first priority for your design. ▪ We can check memory PCB layout characteristics in the following order: 1. Placement 2. Suggested routing order 3. Ground/Power plane 4. Signal layout 5. Other general layout considerations Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 76 ▪ Placement – Memory device must place as close to BB Chip as possible – Avoiding extra long trace (Max trace1500mil) – Avoiding other high frequency de vices place close to Memory – Route these traces smoothly, reduce the via counts and avoiding traces interlace if possible – You can swap byte in order to reduce trace s interlace if there has restriction in placement (only for SD/DDR RAM) – “Swap byte” means to connect DQS0 from BB chip to memory DQS1 in order to reduce the interlacing of data traces, e.g. D[0:7] from BB chip to memory D[8:15]. – Note: Swap the corresponding DQS ,D QM and DQx at the same time. Byte0 Byte0Byte1 Byte1 Byte1 Byte0 Byte0 Byte1Swap High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 77 High Speed Memory layout considerationsHigh Speed Memory layout considerations ▪ Layout routing – Please route traces by the following order: 1. Power/GND plane 2. Data group 3. Clock group 4. Command/Address/control groups – Because high frequency signal integrity is highly related to solid ground and power plane, data groups are operating at twice the clock frequency. – It is recommended that the designer takes care of the layout routing in the very beginning of the design. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 78 BB Memory Traces Power plane (VMEM) VMEM power trace Bypass cap of VMEM should be connected to the power plane. High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations ▪ Ground/Power plane – A solid power/ground plane must be prov ided near all traces routing layers. – It will minimize the ground return current to get better performance. – There are 2 methods for reference: 1. It is recommended all traces are routed above a solid GND plane, and there is a power plane (memory power domain) under the GND plane if possible. e.g. 1st layer : Traces 2nd/3rd layer: Trace (strongly recommended - the same group of traces routed on the same layer) 4rd layer: GND 5th layer: Power plane (VMEM) if possible, which is under the traces of memory interface. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 79 High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations 2. All traces are routed above a solid GND plane , and under a DC power plane (VBAT domain) to provide good shield (the traces of memory interface protected by VBAT and GND) e.g. 1st layer : VBAT 2nd layer: Trace (strongly recommended - the same group of traces routed on the same layer) 3rd layer: Trace 4th layer: GND Note: All power trace bypass capacitors must be placed as close to the devices' power pins as possible, and all capacitor's GND should have the shortest and widest trace to the GND plane. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 80 ▪ Layer definition – ཌྷ‭ṧх૧ሼ௜ྛ䍛 ▪ Stack-up Suggested Layer DefinitionSuggested Layer Definition Signal (horizontal)L6 Signal (vertical)L5 PowerL4 GNDL3 Signal (horizontal)L2 Signal (vertical)L1

6 Layer for EVB

PP (3mil) Signal PP (3mil) Signal Core (ᅀਠІ行ৣ) GND PP (3mil) POWER Signal PP (3mil) Signal (X) (0) ᙄCOREێٙ度ێ,Չ̴ ٙPPێ度༰ᑛ PPێ度༰ᑛ,L1ʿL2ٙSignalϞ௰ ٙreturn path PPێ度༰ᑛ,L5ʿL6ٙSignalϞ௰ ٙreturn path Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 81 High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations ▪ If we take a good power plane under traces, we can get good power trace impedance performance. No power planeNo power plane There are a power plane under memoryThere are a power plane under memory Interface tracesInterface traces The impedance reduce to halfThe impedance reduce to half When added power planeWhen added power plane Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 82 High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations Data jitter=1.04ns Strobe jitter=85.6ps P-P= 499mV Data jitter=1.22ns Strobe jitter=145ps P-P= 598mV Data jitter=0.892ns Strobe jitter=78.5ps P-P= 307mV Only power traceOnly power trace Not good Added a small Added a small power plane power plane under BB chipunder BB chip Better Added power Added power plane under BB plane under BB chip and DRAMchip and DRAM Best Data jitter=1ns Strobe jitter=348ps @output of receiver @IO pad@IO pad of receiverof receiver @IO pad of driver @IO pad of receiver @IO pad of driver @IO pad of driver @output of receiver @IO pad of receiver @output of receiver Data jitter=0.775ns Strobe jitter=261ps Data jitter=0.584ns Strobe jitter=110ps Add a power plane on PCB to enhance performance (reducing signal jitter) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 83 High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations Signal layout ▪ We categorized all signals into 4 groups, prioritized as follows: – 1st priority: Data group – 2nd priority: Clock group – 3rd priority: Control/Command groups ▪ If possible, control trace impedance between BB chip and DRAM, trace impedance is related to PCB dielectric constant, trace width, trace thickness, and routing method (using microstrip or stripline). ▪ The performance will get better if signal trace impedance is under control. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 84 High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations 1. Data group (1/2) – DQx and DQS must be routed in a group and routed in the same layer and reduce via counts if possible. e.g. D[0:7] is aligned to DQS[0]; D[8:15] is aligned to DQS[1]. So, D[0:7] must be routed in a group with DQS[0], and D[8:15] must be routed in a group with DQS[1]. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 85 space width: 1.5W DQS1 trace width: W DQS0 trace width: W GND Via required on entire GND shield High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations 1. Data group (2/2) (Remind : power/ GND plane is the most important) – Within the same data group: (M ax. trace length – 500 mil )< Trace length < (Max. trace length) – Between different data group: (Max. trace length – 500 mil )< Trace length < (Max. trace length) | DQS - Clock trace length | < 300 mil – If possible, control data trace impedance to ensure it meets the requirement (please check input impedance of memory). – Within the same group if DQx trace width is W, the space between DQx is 1.5 W. – To reduce the crosstalk on DQ Sx , GND shielding is required. – If the trace width is W , the trace space between DQSx and GND is at least 1.5W, and the width between DQS0 and DQS1 is at least 3W. – Do not route data group traces in parallel for a long distance. 12mil DQSx Serpentine SpacingSerpentine Spacing Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 86 Space width 1.5W 1.5W 1.5W GND need GND VIA on whole GND shield Differential clock pair (trace width: W) High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations 2. Clock group (1/2) – There are a differential pair of high speed clocks in the DDR SDRAM memory device, so we need to take care of these traces to ensure the clock integrity. – Route these 2 clock traces in para llel and keep equal trace length. – Control clock trace impedance (please check memory device). If clock trace is W the space between clk and /clk is at least 1.5W and there need GND shield wrap around the clock differential pair. The space GND and Clock trace at least 1.5W , and the GND shield need enough GND via if we can not give enough GND via , we would rather take GND shield off , and the space to adjacent signals is at least 2W. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 87 High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations 2. Clock group (2/2) – Away from other high frequency traces – Each clock trace must have solid power and ground plane near the entire route. – Each clock trace is recommended to route on the same layer to reduce Via number, and to keep the same trace characteristics. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 88 High Speed Memory Layout ConsiderationsHigh Speed Memory Layout Considerations 3. Control/Command groups ▪ Every trace must have solid power and ground plane near the entire route. ▪ Every trace is recommended to route on same layer to reduce Via number, and to keep the same trace characteristics. ▪ Route address traces from priority A0 (most toggled ) to A15 (less toggled), and A0 should be close to ground if possible. |Trace length - Clock trace length| < 500 mil Within CMD/ADR group: |Max. (CMD/ADR trace length) – Min. (CMD/ADR trace length)| <250 mil ▪ Remind : power ground is the most important , you just need to meet the traces match criterion as possible ▪ If serpentine is needed , the spacing is at least 12mil Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 89 Check ListCheck List ▪ Placement – Memory device must placed as cl ose to the BB chip as possible. – Avoid extra long trace (Max. trac e: 1500 mil) and other high frequency devices placed close to memory – Route these traces smoothly, reduc e the Via counts and avoiding traces interlacing if possible ▪ Considerations on ground/power plane (power/GND plane is the most important ) – It is recommended all traces to be routed above a solid GND plane, and there is a power plane (memory power domain) under GND plane if possible. e.g. 1st layer: Traces 2nd layer: Trace (strongly recommended — the same group of traces routed on the same layer) 3rd layer: GND 4th layer: Power plane (VMEM) if possible, the plane is under the traces of memory interface. – Or all traces are routed above a solid GND plane, and under a DC power plane (VBAT domain) to provide a good shield (the traces of memory interface protected by VBAT and GND). e.g. 1st layer : VBAT 2nd layer: Trace (strongly recommended — the same group of traces routed on the same layer) 3rd layer: Trace 4th layer: GND ▪ Trace length is as match as possible , All traces refer to clock , within 500mil length difference is acceptable (DDR , DQS and DQ is a group , and DDR clock ,/clock are within 100mil) ▪ If serpentine is needed , the spacing is at least 12mil 12mil DQSx Serpentine SpacingSerpentine Spacing Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 91 MTK USB2.0 Solution IntroductionMTK USB2.0 Solution Introduction ▪ This document introduces MTK USB2.0 design and some points for attention. – MTK USB2.0/ OTG device can operate at USB2.0 High-Speed (HS) mode (480Mb/s) and Full-Speed (FS) mode (12Mb/s). ▪ General HS eye diagram is shown as below. The output swing is differential 0.4V. Bad eye diagram will lead to certification fail or signal integrity problem. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 92 USB Pin DefinitionUSB Pin Definition ▪ USB2.0 pin out description. – General pins – Optional pins for supporting OTG * Comparator used for detecting changes of VBUS voltage. IOPAD_USB_VBUS1 Analog 1.2V groundGNDAVSS12_USB8 Analog 1.2V supply. VDDAVDD12_USB7 Analog 5.1K reference resistor IOPAD_USB_VRT6 Analog 3.3V ground GNDAVSS33_USB5 Analog 3.3V supply VDDAVDD3_USB4 USB serial differential bus (positive)IOPAD_USB_DP3 USB serial differential bus (minus)IOPAD_USB_DM2 DescriptionTypeSymbolPin Optional function for USB OTG ID pin for detecting slave plug in. IOPAD_USB_ID9 DescriptionTypeSymbolPin Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 93 Must be 5.1K ohm, 1% Place close to IC Reserve bead and bypass capacitor for USB 1.2, 3.3V Power Don’t have to connect VBUS/ID Schematics Design for USB2.0 Device (2/2)Schematics Design for USB2.0 Device (2/2) ▪ MT6516 (Device Only) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 94 Schematics Design for USB2.0 High SpeedSchematics Design for USB2.0 High Speed ▪ Beware of USB_VRT pin should keep away from noise source and high speed clock data like camera databus. ▪ Reserve 0402 cap (NC) on DP/DM for ESD protection and rise time/fall time tuning for USB-IF compliance test. ▪ If want to get USB-IF OTG logo, should use micro-AB connector. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 95 D- data line VUSB 15K ohm USB sideInside MTK USB 15K ohm D+ data line 100K ohm Inside MTK USB Standard charger side D+ data line VUSB D- data line 100K ohm Non-standard charger side 100K ohm D+ data line Inside MTK USB VUSB D- data line USB/ Charger DetectionUSB/ Charger Detection ▪ Used for MT6516 and later on MTK ICs (MT6268/MT6516/MT6253) ▪ When charger interrupt happens, turn on D- pull high 100K ohm resistor and check the polarity of D- – If the D- is LOW, it is USB charger, otherwise it is a standard or a non- standard charger Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 96 VUSB 15K ohm Standard charger side D- data line 1.5K ohm Inside MTK USB D+ data line VUSB Non-standard charger sideInside MTK USB 15K ohm D+ data line 1.5K ohm D- data line USB/ Charger Detection (Cont.)USB/ Charger Detection (Cont.) ▪ Then check whether it is standard or non-standard charger. Turn on D+/D- internally 15K ohm pull low resistor and D+ 1.5K ohm pull high resistor at the same time. – Check D- polarity. If the D- is HIGH, it is standard charger, otherwise it is a non-standard charger. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 97 High Speed USB Layout Checklist (1/2)High Speed USB Layout Checklist (1/2) ▪ General design and layout rules – With minimum trace lengths, route clock source and HS USB differential pairs first. Keep maximum possible distance between clocks/periodic signals to USB differential pairs to minimize crosstalk. – Route HS USB signal pairs toget her with equal length by using a minimum vias and corners. This reduces signal reflections and impedance changes. – Maintain parallelism between USB differential signals with the trace spacing needed to achieve 90 ohms differential impedance. – When it becomes necessary to turn 90 ¢, use two 45¢ turns or an arc instead of making a single 90¢ turn. This reduces reflections on the signal by minimizing impedance discontinuities. – Do not route USB traces under crystals, oscillators, clock synthesizers, magnetic devices or ICs that use and/or duplicate clocks. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 98 High Speed USB Layout Checklist (2/2)High Speed USB Layout Checklist (2/2) ▪ General design and layout rules (Conti.) – Stubs on HS USB signals should be avoided, as stubs will cause signal reflections and affect signal quality. – Avoid crossing over anti-etch if possible. Crossing over anti-etch (plane splits) increases inductance and radiation levels by forcing a greater loop area. Likewise, avoid changing layers with high-speed traces as much as practical. – Keep HS USB signals away from high current area. The current transient during state transitions could induce noise to USB. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 99 Avoid creating stubs if possible Proper way to connect resistors or varistors StubsStubs ▪ Avoid creating unnecessary stubs on data lines, if a stub is unavoidable (for example: ESD issue), please keep the stub as short as possible. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 100 TP Failure to maintain parallelism of USB2.0 data lines Ground or Power plane Don’t cross plane splits Avoid creating stubs Proper routing technique maintains spacing guidelines Poor Routing TechniquesPoor Routing Techniques ▪ Cross a plane split. ▪ Creating a stub with a test point. ▪ Failure to maintain parallelism. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 101 Case Study (1/5)Case Study (1/5) ▪ Case 1: – 2A36/2A37 should be removed. Large cap at USB_DP/USB_DM will lead to bad jitter performance. – Measured eye at board is shown below. It will occur turn-around error at system application. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 102 Case Study (2/5)Case Study (2/5) ▪ Case 2: – After bead, at least 0.1uF capacitor between VDD33_USB, VDD12_USB and ground must be added as follows. – Measured eye diagram has bad jitter performance. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 103 ▪ Case 3: – Some time we got worse jitter due to poor layout, then VUSB33 and VUSB12 are coupled by noise. – It is improved by increasing bypass capacitor C221 and C235. Before modification Improved after modification Chip side Case Study (3/5)Case Study (3/5) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 104 Original design without analog switch Add different analog switch Fairchild FSUSB42 Fairchild FSUSB30 Case Study (4/5)Case Study (4/5) ▪ Case 4: – Customer wants to share USB data pi ns with audio/UART pins through the same 5-wire USB connector by using analog switch. – Different analog switches cause different attenuation of signals; please make sure component and layout will get proper eye diagram. – No suggestion on using analog switch, 11-pin USB connector could be used instead. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 105 Cable with large series resistance Design with normal USB cable Cable with proper series resistance Case Study (5/5)Case Study (5/5) ▪ Case 5: – Sometimes customer may design a special connector for USB, such as 18-pin I/O. – Poor cable will cause poor performance. – Please follow USB cable design guide. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 106 ConclusionsConclusions ▪ Layout and component selection are critical for USB2.0 high speed performance – Need to follow the design rule or there might be compatibility issue happens ▪ Grounding and shielding are both critical when design USB2.0 high speed capable cables – It can maintain USB signal quality with little jitter/ signal distortion caused by cable design ▪ Please refer to “MTK USB2.0/ OTG Design Guide “ for more detail. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. MT6MT6516516 Factory Mode & Factory Mode & Engineer Mode Notice Engineer Mode Notice Copyright © MediaTek Inc. All rights reserved. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 108 Engineer Mode and Factory mode Engineer Mode and Factory mode ▪ Factory mode – Enter phone menu ▪ Engineer mode – Enter phone menu – Enter “*#3646633#”, then dial Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 111 Flash Tool Flash Tool Download FlowDownload Flow ▪ Bootloader Download – Use UART1 to download bootloader ▪ Windows Mobile image download – Connect both UART1 and USB to download full WinMo image ▪ Flash tool can combine the two steps above. (Must connect both UART1 and USB to PC first !) ▪ Please refer to flash tool document in detail. Download Download BootloaderBootloader Download ImageDownload Image Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 112 Download tool Download tool ፯኿ Load ͦ錄裡ٙ Flash.Bin MT6516_mldrnandforMTK.nb0 MT6516_EBOOTNAND.nb0 Then press Download all Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 113 META META LinkLink (AP Side)(AP Side) ▪ Install Smartphone META tool. ▪ How to enter META mode (UART1) – If target have not been in META mode, click “Reconnect” button, then connect phone; – Phone will power on and enter in to META mode automatically ▪ UART can support up to 115200bps baud rate Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 114 META META LinkLink (Modem Side)(Modem Side) ▪ Install smartphone META tool (for first time) ▪ Link UART4 on handset to PC ▪ Open hyper terminal on PC and set correct COM port and parameters. ▪ Press “send key” and “end key” to power on. ▪ Set boot to META mode: Enter 9->3->1 ▪ Enter 0->0, continue to boot to META mode ▪ Close hyper terminal, switch UART4 to UART1. (UART1 link to PC) ▪ Wait about 12 seconds. ▪ Execute META tool ▪ Choose UART and enable “connect target already in META mode” in option menu. ▪ Can backup/restore calibration data in “update parameter” as feature phone. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. MT6MT6516516 MMemory emory SSupport upport PlanPlan Copyright © MediaTek Inc. All rights reserved. MTK MVG (Memory Verification Group) Apr 2009 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 116 MT6516Platform (2G/1G) +1G (x32) NAND + MobileDDR MCP MCP MCP Type Samsung K522F1GACM-A060 (2G+1G, 1.8V*, BGA137) Æ W0919 Elpida EHD013011MA-60 (2G+1G, 1.8V, BGA137) Æ W0921 Toshiba TYA000B801CFLP40 (2G+1G, 1.8V, BGA137) Æ W0922 Numonyx NANDBAR4N5BZBC5E (2G+1G, 1.8V, BGA137) Æ W0923 Micron MT29C2G24MAKLAJA-6 (2G+1G, 1.8V, BGA137) Æ W0924 Hynix H8BCS0PJ0MCP-56M (1G+1G, 1.8V, BGA137) Æ W0925 Samsung K522H1GACD-A060 (2G+1G, 1.8V, BGA137) Æ W0926 Micron MT29C1G24MAVLAJA-6 (1G+1G, 1.8V, BGA137) Æ W0927 Micron MT29C1G24MACLAJA-6 (2G+1G, 1.8V, BGA137) Æ W0928 Memory P/N (Week available) NAND(SLC, 2K page) + 133/166MHz MobileDDR EDGE Smart PhoneSegment EDGE Smart PhoneEDGE Smart Phone * Voltage supply of NAND flash. ** For devices not included in the weeks available, please contact with MTK PM for status update. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 119 OutlineOutline z Module function block and reference design ¾ Module function block ¾ Module reference design ¾ Reference interface assignment ¾ Key component list zSchematic and layout design guide ¾ Schematic design guide ¾ Layout design guide Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 120 WiWi--Fi/BTFi/BT Combo Module Product DefinitionCombo Module Product Definition ▪ Full-featured Wi-Fi 802.11b/g and BT 2.1 + EDR combo module ▪ Small-size package: 9.5×10.5×1.4 mm LGA (< 10×10 mm) ▪ MTK’s proprietary superior Wi-Fi/BT co-existence performance ▪ Wi-Fi and BT co-existence shares the 26 MHz clock frequency. ▪ Metal EM interference shielding ▪ Antenna: Dual antenna (mandatory)/Single antenna (optional) ▪ RoHS complaint Sample: Sep. 2008 MP: 2009/02 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 121 MTK Combo Module Block DiagramMTK Combo Module Block Diagram SDIO/SPI Interface GPIO EEPROM 1.8V3.3V Combo Filter PCM Interface UART InterfaceBluetooth SOC (MT6611 WLCSP) Coexistence BalunSwitch BPF PA Wi-Fi SoC (MT5921P WLCSP) Ref Clock ANT1 VBAT Tx/Rx 32k Sleep Clock ANT2 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 122 WiWi--Fi FeaturesFi Features ▪ Advanced Wi-Fi features – 802.11b/g/e/i/h/k/w compatible – IEEE 802.11e QoS (WMM/WMM-PS) – Background scan for specific SSID networks – IEEE 802.11i advanced secu rity (WEP/TKIP/AES/WPA/WPA2) – 802.11e optional U-APSD, DLS – 802.11 power saving mode – Wakeup by specific pa cket (pattern search) – Thermo-sensor to resi st temperature change ▪ Voice over WLAN (VoWLAN) – UMA (Unlicensed Mobile Access) technology – VoIP over WLAN ▪ Software support –W i n C E 5 . 0 – Win Mobile v5.0/6.1 – Win Mobile v7.0 (planning) – Linux v2.6 (planning) ▪ Wi-Fi certified Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 123 Bluetooth FeaturesBluetooth Features ▪ Radio features – Fully compliant with Bluetooth 2.1+EDR – Low-IF Architecture with high performance linearity – Supports Bluetooth class 2 and 3 – Tx transmit power: 4 dBm – 90 dBm sensitivity with exce llent interference rejection performance ▪ Baseband features – Up to 7 simultaneous active ACL links – Supports 3 simultaneous SCO and eSCO links SCO and scatternet – Supports lower power mode (Sniff, Hold and Park mode) – Ultra low power consumption in sleep mode – Supports AFH and PTA for WLAN/BT coexistence ▪ Software features – Supports standard HCI interface – Supports more than 15 profiles in MediaTek platform MT6611 Function Block Free Datasheet http://www.Datasheet-PDF.com/

WiFi power need to power on to keep daisy chain working normally.
WiFi can be shut down only as BT power off. 26MHz OSC.
MT5921+Mt6611 Module Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 125 Co-module Reference Design J900 MM8130-2600B COAXIAL/CON/MM8130-2600B AME8801 SOT-25-5 BYP 4 Vout 5Vin1 GND2 EN3 R9180R 0402 TCVCXO 26MHz Y900 TCXO3225 E/D 1 GND 2O/P3 VDD4 R917 910R 0402 R9120R 0402 R907 100k C900 2.2uF 0603 C911 2.2uF 0603 U901 CO_MODULE PAVDD331 GND2 WLAN_LED3 BT_GPIO17 BT_CLK10 GND5 GND6 GND9 BT_VCC28OUT8 GND4 BT_LDO28EN11 BT_VBAT12 BT_GPIO413 GND14 WLAN_ANT15 GND 16 BT_PCMOUT17 BT_PCMCLK18 BT_PCMIN19 BT_PCMSYNC20 BT_URXD21 BT_UTXD22 BT_GPIO523 BT_GPIO624 BT_32K25 BT_GPIO026 BT_SYSRST_B27 GND 28 SD_D2 36 GND 30 SRCLKENA 31 VDD18 32 GND 33 WLAN_CLK 34 SD_CLK 37 OSC_EN 35 SD_D3 38 SD_D0 39 SD_CMD 40 SD_D1 41 INT_N42 EXT_RST_N43 WL_GPIO244 DVDDMIO45 DVDD3347 BT_ANT 29 DVDD2848 GDN49 WLAN_32K50 GND51 ANT_SEL_P46 ANT_SEL_N52 GND54 WL_GPIO053 GND55 C902 4.7uF 0603 DVDD28 VDD18 +2.8V VWIFI_3V3 VBT PAVDD33 VDD18 DVDD28 R908 100k PAVDD33 VWIFI_3V3 BT_2V8 VWIFI_3.0 VBAT SDIO_D2 2,5 SDIO_CLK 2,5 SDIO_CMD 2,5 EXT_RST_N SDIO_D3 2,5 GPIO1162 BT_PCMIN BT_SYSRST_B BT_32K BT_PCMCLK SDIO_D0 2,5 BT_PCMOUT OSC_EN BT_PCMSYNC EINT12 URXD3 2 UTXD3 2 R926 100k DAICLK2 BT_PCMOUT 2 BT_PCMIN 2 DAIPCMIN2 DAIPCMOUT2 BT_PCMSYNC 2 BT_PCMCLK 2 DAISYNC2 EXT_RST_N GPIO1222 INT_N GPIO1152 INT_N2 BT_GPIO0 EINT5 2 BT_GPIO0 2 SDIO_D22,5 SDIO_CLK2,5 SDIO_CMD2,5 SDIO_D02,5 SDIO_D32,5 BT_SYSRST_B BT_32K SDIO_D12,5 MC1DA0 2,5 MC1CM0 2,5 MC1DA1 2,5 MC1DA2 2,5 MC1CK 2,5 MC1DA3 2,5 WLAN_32K SDIO_D1 2,5 WLAN_32K GPIO1232 BT_GPIO1 BTLDO28EN 2 BTLDO28EN2 GPIO133_WIFI_EN 2 GPIO1322 BT_GPIO1RTS INPUT Power C900 close to pin8 BT+WLAN MODULE OSC_EN Host UART CTS pin connect to GND DVDD28 R910 NC 0402 SRCKLENA C914 1uF 0402 R905 100k ANT_SEL_N ANT_SEL_N BT_CLK ANT_SEL_P BT_CLK ANT_SEL_P WLAN_CLK WLAN_CLK C901 1uF 0402 R901 100k 0402 R9230 0402 C906 NC 0402 L900 NC 0402 R9140R 0402 C912 1nF 0402 C903 1.2pF 0402 J901 MM8130-2600B COAXIAL/CON/MM8130-2600B 3 4 TP902 TP30MIL R9030R 0402 ANT901 WiFi_ANT ANT901 <Designator> PADX2(2.X2.2/P2.5) R9040R 0402 R9240 0402 C908 1nH 0402 C913 4.7uF 0603 R9150R 0402 R902 100K 0402 R916 0R 0402 C910 1uF 0603 BT_ANT PAD1.35X1.5 R9270R 0402 R906 100k R909100K 0402 C909 1uF 0603 R9110R 0402 C907 0.5pF 0402 L901 2.2pF 0402 R9130R 0402 26MHz Oscillator SDIO Interface UART Interface PCM Interface Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 126 Interface Assignment 26MHz Oscillator List Y900ԭௗFK2600008 (Load 15pF, 2.8V~3.3V) Y900EPSONSG-310SCN. (Load 15pF, 2.8V~3.3V) Y900TXC8W26000011 (Load 15pF, 2.8V~3.3V) Y900AkerSMA026000-3DR3T0 (Load 15pF, 2.8V~3.3V) 26MHz Oscillator DesignatorVendorPart numberItem Type Pin Function GPIO133 WIFI_RSTB GPIO116 WLAN_32K MC1CM0 MC1DA0 MC1DA1 MC1DA2 MC1DA3 MC1CK I/O *' SDIO INT5 WiFi_interruptI/O Type Pin Function GPIO122 BT_RSTB GPIO115 BT_32K UTXD3 URXD3 DAICLK DAIPCMOUT DAIPCMIN DAISYNC I/O *' PCM UART INT1 BT_interruptI/O

MT6611 PCM/UART power domain support 2.8~3.3v, not support 1.8V Free Datasheet http://www.Datasheet-PDF.com/

Fixed Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 128 Schematic Design Guide(1)_Power SupplySchematic Design Guide(1)_Power Supply zPAVDD33 is a dedicated input pin for module internal PA power supply and please connect it to 3.3V. zDVDD28, DVDD33 and DVDDMIO are the WiFi portion digital IO power source, please connected to 3.0V for optimum Tx performance. zVDD18 is the WiFi RF/analog/digital LDO input pin and can be connected to DC/DC 1.8V power source without degrading the module performance. BT_VCC28OUT DVDD28 VDD18 WiFi/BT MODULE PAVDD331 GND2 WLAN_LED3 BT_GPIO17 BT_CLK10 GND5 GND6 GND9 BT_VCC28OUT8 GND4 SD_D2 36 VDD18 32 GND 33 WLAN_CLK 34 SD_CLK 37 OSC_EN 35 SD_D3 38 SD_D0 39 SD_CMD 40 SD_D1 41 INT_N42 EXT_RST_N43 WL_GPIO244 DVDDMIO45 DVDD3347 DVDD2848 GDN49 WLAN_32K50 GND51 ANT_SEL_P46 ANT_SEL_N52 GND54 WL_GPIO053 PAVDD33 DVDD33 DVDDMIO Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 129 BT Power Domain (2)BT Power Domain (2) ▪ Distributed into two domains: V_BAT and 2.8V – V_BAT power source could come from phone battery and BT_VCC28 is the internal LDO output pin. – The BT 2.8V internal LDO was controlled by BTLDO28EN pin connected to host GPIO. BTLDO28EN 2.2uF BT_VCC28OUT V_BAT 4.7uF WiFi+BT MODULE BT_GPIO17 BT_CLK10 GND5 GND6 GND9 BT_VCC28OUT8 BT_LDO28EN11 BT_VBAT12 BT_GPIO413 GND14 WLAN_ANT15 GND 16 BT_PCMOUT17 BT_PCMCLK18 BT_PCMIN19 BT_PCMSYNC20 BT_URXD21 BT_UTXD22 BT_GPIO523 BT_GPIO624 BT_32K25 BT_GPIO026 BT_SYSRST_B27 GND 28 SD_D2 36 GND 30 SRCLKENA 31 VDD18 32 GND 33 WLAN_CLK 34 SD_CLK 37 OSC_EN 35 BT_ANT 29 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 130 Schematic Design Guide(3)_Clock SourceSchematic Design Guide(3)_Clock Source zThe WiFi/BT device can share a same clock with a daisy chain function .This mechanism allows Bluetooth can work normally without extra power consumption even WiFi operating in the sleep mode. zThe oscillator with 2.8~3.3V operated voltage , 20ppm tolerance and 15pF load capacitance is recommended

32KHz clock for device sleep mode - The 32KHz source come from BB GPIO output.. WLAN_32K BT_32K BT_32K25 WLAN_32K50 (GPIO115) (GPIO116) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 131 Schematic Design Guide(4)_InterfaceSchematic Design Guide(4)_Interface zPlease add 100K pull resistors for the SDIO data pin except SD_CLK pin. zFor BT UART interface, please note to connect the MT6516 host UART CTS pin to GND. WiFi SDIO InterfaceBT UART Interface Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 132 MT5921 Power Sequence MT5921 Power Sequence In order to prevent from the IO driving unpredictable signals, it is recommended that the 1.8V is applied before IO power or they are applied at the same time. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 133 The power on reset time is related to the frequency of main reference clock source. The normal functions are not ready until the power-on-reset was done. MT5921 Power On /Reset TimingMT5921 Power On /Reset Timing Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 134 MT6611 Power On InitializationMT6611 Power On Initialization ▪ Hardware reset sequence & timing requirement – (1) Set BT_LDO_EN to high – (2) Wait for at least 2ms – (3) Set BT_RESET to high – (4) Wait for at least 1000ms – (5) MT6611 is ready for receive HCI command BT_LDO_EN BT_RESET (1) (2) (4) (5) (3) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 135 Module Layout Guide – 1/4 Layer1z Please place the bypass capacitors to the 3.3/2.8/1.8V power rail as close as possible. z Please keep 50 ohm transmission for The WiFi/BT RF trace. zPlease isolate the WiFi/BT main clock trace with GND zPlease reserve the 9 square GND PAD for better performance for module BT_ANT :50ohm trace WLAN_CLK Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 142 ▪ MTK GPS Overview – MT3326 GPS Feature – MT3326 System Block ▪ MTK GPS Reference Design – MT3326 Schematic Design Note – MT3326 PCB Design Note – MT3326 QVL – MT3326 Debug SOP – MT3326 ATE Tool ▪ MTK GPS Tier One Performance ▪ Summary ▪ Q&A AgendaAgenda Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 143 MT3326 FeaturesMT3326 Features ▪ Dimensions: – 48-pin QFN lead-free pack age (6 x 6 x 0.85 mm) ▪ Specification: – Host-based GPS receiver – 22 tracking/66 acquisiti on channel GPS receiver – Supports WAAS/EGNOS/MSAS/GAGAN – Supports up to 210 PRN channels – Jammer detecti on and reduction – Indoor/outdoor multi-pa th detection and compensation – Supports A-GPS with FCC E911 compliance – Maximum fix update rate up to 10 Hz ▪ Reference Clock Support: – TCXO Frequency : 12 .6 MHz ~ 40.0 MHz ▪ Interfaces: – 2 UARTs , SPI , I 2C , GPIO ▪ Low Power Consumption: – Acquisition mode : 39 mA – Tracking mode : 26 mA MT3326 Compact Layout Area : 12 x 12 mm Free Datasheet http://www.Datasheet-PDF.com/

GPIO Pull Low Æ GPS Receiver Off
GPIO Pull High Æ GPS Receiver On SAW TCXO LDO 2V8 External LNA MTK GPS IC MT3326 GPS_PWR_EN 29_RX0 26_TX0 22_SYNC UART2_TX UART2_RX BPI _BUS6 (Optional) MT6516 Passive Antenna 0.5 ppm Optional: If 2.8V voltage can be provide by PMIC, the external LDO can be eliminated. GPIO MT6326MT6326 PMIC 2.8 V Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 146 MTK GPS Total Solution MTK GPS SW Build inMTK GPS SW Build in GPS Antenna ReviewGPS Antenna Review Factory Tool SupportFactory Tool Support TierTier--1 Field Trial1 Field Trial MTK GPS Phone Total SolutionMTK GPS Phone Total Solution Reference DesignReference Design CH1 S22 LOG 5 dB/ REF 0 dB CENTER 1 . 575 000 000 GHz SPAN . 200 000 000 GHz Cor Avg Hld PRm MARKER 1

1.57542 GHz

17 May 2000 13:18:10

1 : -29 . 366 dB 1 . 575 420 000 GHz CH1 Markers BW : . 019597108 GHz cent : 1 . 576044505 GHz Q : 80 . 422 1_ loss : -29 . 366 dB CH1 S22 1 U FS CENTER 1 . 575 000 000 GHz SPAN . 200 000 000 GHz Cor Avg Hld PRm MARKER 1

17 May 2000 13:18:39

1: 5 3 .4 1 4 -824 . 22 m 122 . 57 pF 1 . 575 420 000 GHz CH1 Markers 2: 5 4 .0 9 8 -304 . 69 m 1 . 57604 GHz 3: 9 5 .9 4 1 -4 . 6016 1 . 56624 GHz 4: 4 0 .0 8 0 -28 . 146 1 . 58584 GHz Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 147 MT3326 Reference CircuitMT3326 Reference Circuit GPS RF front end TCXO UART LDO Com pact BOM and Layout Area! Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 148 MT3326 Reference Circuit (2/4)MT3326 Reference Circuit (2/4) GPS RF Front End LNA Input Matching : Please place these components close to LNA Input Decoupling Capacitor for Noise filtering Mixer Input Matching : Please place these components close to MT3326_Pin 46 Antenna Matching Passive Antenna : Circular Polarization Patch Antenna is recommend SAW Filter : For filtering jamming Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 149 MT3326 Reference Circuit (3/4)MT3326 Reference Circuit (3/4) Frequency :16.368 MHz Frequency Stability : +/- 0.5ppm C1011 10nF C1013 1uF R1001 U1007 RAKON/IT3205BE/16.368MHz VCC4 OUT 3 GND 2NC1 2V8 2V8 TCXO C1018 1uF (X5R) U1005 XC6221A182NR VIN4 CE1 VSS2 VOUT 3 C1017 1uF R1002 100K 2V8 VBAT GP019_GPS_PWR_EN2 POWER TCXO LDO TCXO VCC : Avoid the noise interference for frequency stability Reserve 0 ohm to isolate the impact of PCB GND temperature variation on TCXO. GPIO from MT6516 to control LDO On/ OFF Stabilize the LDO output Voltage Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 150 MT3326 Reference Circuit (4/4)MT3326 Reference Circuit (4/4) GPS_UART0 connect to MT6515 UART interface MT3326 Supply voltage : *Analog Voltage : RF_1V5 * Digital Voltage : Core_1V2 LDO I/O P Capacitor : Place these Capacitors close to the MT3326 LDO input Pin and output Pin for stabilizing voltage Optional : Connect to MT6516 BPI_BUS. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 151 PCB Design FlowPCB Design Flow PlacementPlacement Layout 1:Layout 1: RF TraceRF Trace Layout 2 :Layout 2 : Layout 3:Layout 3: LDO LDO ---- 2V82V8 Analog Power Analog Power ---- RF_1V5RF_1V5 Layout 4:Layout 4: Digital Power Digital Power ---- Core_1V2Core_1V2 Layout 5:Layout 5: Interface Connect with Interface Connect with MT6238MT6238 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 152 PCB Component Placement (1/3)PCB Component Placement (1/3) LDO TCXO SAW Filter External LNA MT3326 The route of reference clock is the shortest to avoid interfering by other noise The Capacitors close to analog and digital voltage output Keep the RF path from antenna to MT3326 as short as possible Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 153 MT 3326 PCB Component Placement (2/3)PCB Component Placement (2/3) MT 3326 SAW filter & External LNA If the location of GPS function block is far away from GPS antenna Pad, please place the first-stage SAW filter and external LNA close to GPS antenna port for reducing RF path loss. GOOD !! BAD !! Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 154 GPS Antenna 12X12X7 Active Patch GSM Antenna Metal monopole on bottom. Avoid GSM TX interfere with GPS RX. 15mm clearance for triple band 25mm BT Antenna Metal PIFA is recommended. It can be mounted on Speaker Holder. Chip antenna is also an option. 90mm GND Length for triple band GPS Placement 10.5mmX10.4mm Near GPS Antenna Pen Material is plastic near GSM ANT. Place GSM Cal Kit below pen. It occupy less GSM ANT Area. GPS Antenna Placement (3/3)GPS Antenna Placement (3/3) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 155 z Probe-Feed RHCP Patch (Fig.1) Patch Size: 12X12X4, 13X13X4 Vendors: Whayu, Yageo, CIRO, Microgate, Amotech z Probe-Feed LP Patch (Fig.2) Patch Size: 15X10X4, 16X6X5 Vendors: Whayu, Yageo, CIRO, Microgate, Amotech 12mm 12mm Fig.1 10mm / 6mm 15mm / 16mm Fig.2 Proposal of GPS Patch Antenna for Slim PhoneProposal of GPS Patch Antenna for Slim Phone 12X12X4 15X10X4 16X6X5 -1.1 US D Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 156 PCB Layout Design Note (1)PCB Layout Design Note (1) ▪ RF Part : ▪ RF Path keep as short as possible for reducing RF signal transmitted loss. ▪ All RF traces have to do impedance control (50 Ohm) for good sensitivity. ▪ RF traces route on the surface layer and far away from other high speed signal trace are recommended. ▪ Isolate external LNA input and output pin by copper plane. ▪ To keep the digital signal trace far away from the GPS layout area. ▪ Clear the metal below all matching component area to reduce the parasitic capacitance. Clear the metal below the RF trace and Pad !!! High Parasitic capacitance couldn’t reach optimal RF match Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 157 ▪ TCXO Part: ▪ Keep TCXO clock trace as short as possible. ▪ Keep the noisy traces far away from TCXO clock traces. ▪ TCXO clock traces enclosed by PCB copper is recommended. ▪ Position TCXO far away from any high temperature component like as GSM_PA to avoid the frequency drift. PCB Layout Design Note (2)PCB Layout Design Note (2) MT3326 TCXO TCXOTCXO TCXO Pin 11 TCXO Clock Input Pin 46 GPS signal Input The Best Position : 1. Clock trace is the shortest 2. It’s easy to route Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 158 ▪ Power Line Part ▪ Power trace should keep as low impedance and adequately add de-coupling capacitor for noise filtering. - Recommended width of power trace : Main Trace: 20 mils at least Branch into IC pin/ball: 10 mils at least ▪ Keep de-coupling capacitors close to the power pin of GPS chipset and external LDO. ▪ Use many, many via holes to connect the power traces between layers. PCB Layout Design Note (3)PCB Layout Design Note (3) Use many via holes to connect the power traces between layers Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 159 Qualified Vender List Qualified Vender List ---- TCXOTCXO KyoceraKyoceraKT2520Y16368ACW28TMA Aurum Tech Inc.RakonIT2205BE 16.368 MHzTCXO 2520 (16.368 MHz ) EPSON TOYOCOMEPSON TOYOCOMTCO-5869MTCXO (16.368 MHz) +/- 2.0ppm TXCTXC7Q16300001-16.368MHz NDKNDKENG3090B KyoceraKyoceraKT3225F16368ACW28TA0 ITTIITTI1300269-16-16.368MHz EPSON TOYOCOMEPSON TOYOCOMTG-5005CE-21G Unifirst EnterpriseTEWTTS14NSB-A8 Aurum Tech Inc.RakonIT3205BE/IT3205CE TCXO (16.368 MHz) +/- 0.5ppm VendorManufacturerPart numberComponent Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 160 ὍӮTOKOTK71728 AMEAMEAME8801CEEVZ ૹᐕTorexXC6215/XC6401 LDO_2V8 MAXIMMAXIMMAX2659 NECNECUPC8231 ỌλJRCNJG1117HA8 External LNA VendorManufacturerPart numberComponent Qualified Vender List Qualified Vender List ---- LNA & LDOLNA & LDO Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 161 Qualified Vender List Qualified Vender List ----GPS AntennaGPS Antenna Size (mm3)Antenna Vendor 13X13X4Amotech 12X12X4, 13X13X4, 15X15X4CIRO 15X15X4Mag.layers 12X12X4, 15X15X4Yageo 12X12X4, 13X13X4, 15X15X4Whayu Circular-Polarized Patch Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 162 MT3326 HW Debug SOPMT3326 HW Debug SOP Verify voltage level of all power Supplies Check Connection of UART TXD & RXD Check GPS HW Configuration GPIO Setting & PMIC 2.8V GPS Function Ok! Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 163 MTK GPS Phone Manufacture FlowMTK GPS Phone Manufacture Flow Assembly Download OK? Com port Baud rate FW Download Single Channel CNR Current is good? Conductive ATE Antenna Multi- Channel Unit TTFF and Hot Start are good? Or Open Sky Radiation MiniGPS Repair station PCBA MT3326 No need !!MT3326 No need !! Free Datasheet http://www.Datasheet-PDF.com/

32 Channel

Firmware Ver. Usage Customers Production line End users Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 165 Test Instruments (1/2)Test Instruments (1/2) Multi-Channel GPS Satellite Simulation System Spirent GSS6560 Spirent STR4500 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 166 Single channel GPS-101 GPS Satellite Simulator VNA SA NFA Areoflex SG Test Instruments (2/2)Test Instruments (2/2) Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 168 OutlineOutline z DTV function block and reference design ¾ DTV function block ¾ DTV reference design zReference interface assignment and key component ¾ Reference interface assignment ¾ Key component zSchematic and layout design guide ¾ Schematic design guide ¾ Layout design guide Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 170 DTV Function Block z DTV solution consists of MT5151, MT5162 tuner and one low-power SDRAM. It's integrated in MCM TFBGA-124 package to provide high integration level and high performance solution. z MTK DTV solution provides worldwide DVBT compliant standard in VHF and UHF reception via the common SDIO/SPI interface. Silicon Tuner Silicon Tuner TS Demux TS Demux I Q AGC TSPD I2C Demod & Time Slicing Control Demod & Time Slicing Control MPE-FEC MPE-FEC CPU CPU I/Q ADC & RF Interface I/Q ADC & RF Interface Time Domain Processing Time Domain Processing Freq. Domain Processing Freq. Domain Processing FEC FEC Host Interface Host InterfaceMemory Controller Memory Controller Low-Power SDRAM Low-Power SDRAM TSIF SDIO SPI Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 171 TP1213~1217 Test pinڐball׳ ,不஗Չ˼數Зᇞ༨൳ JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO DTV_DVDD12 DTV_DVDD28 DTV_AVDD12 DTV_AVDD12 JTAG_SRST JTAG_RTCK JTAG_RST# DTV_DVDD12 DTV_DVDD28 DTV_AVDD28 DTV_VDD18 DTV_DVDD28 DTV_VDD18 DTV_DVDD12 RF_AGCRF_AGC_T DTV_DVDD28 DTV_VDD18 DTV_VDD18Q RX D232A TXD232A DTV_DVDD28 DTV_DVDD28 DTV_DVDD12 /MT5151_RESET DTV_DVDD28 DTV_DVDD12 RF_AGC_TRF_AGC_T DTV_VDD18Q DTV_VDD18Q DTV_DVDD28 DTV_VDD18Q RF_AGC DTV_VDD18 TXD232A TXD232A TXD232A TXD232A JTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDO /MT5151_RESET VCC_RF DTV_VDD18Q TXD232A TXD232A RX D232A RX D232A 1TP1201 TP30MIL

1 TP1205

0.1uF 0402 3 4 J903 MM8130-2600B COAXIAL/CON/MM8130-2600B C1235 5.6pF0402 D801 ESD1P0RFL In1 GND2 GND3 OUT4 GND5 U1202 LP92H (B8763) FILTER/SMD/LP92A/EPCOS

1 TP1215

0.1uF 0402 C1290 0.1uF 0402 L1210 LQW15AN19NG00 0402 L1239 LQW15AN82NG00 0402 R1234 1K 0402

1 TP1213

1 TP1208

0.1uF 0402 C12996.8pF 0402 C1218 2.2uF 0603 C1224 0.1uF 0402 C1230 0.1uF 0402 VIN4 CE1 VSS2 VOUT 3 U1200 XC6221A282NR SSOT-24-4/XC6221 Unbal1 Bal 2 Bal 3GND4 Z1207 DLP11SN900HL2 L/CHOKE/SMD/DLP11SN C1237 100pF 0402

1 TP1206

0.1uF 0402 R1211 100K 0402 L1218 15nH, 5%, LQW15A, wirewound 0402 R1231 12pF 0402 C1252 47nF 0402 C1123 1uF (X5R) 0402 C1236 12pF 0402 C1208 0.1UF 0402 DTV ANT PAD/1P/3.58X5.56 ANT903

1 TP1211

0.1uF 0402 C1232 NC 0402 R1232 NC 0402 R1228 NC 0402 Unbal1 Bal 2 Bal 3GND4 Z1206 DLP11SN900HL2 L/CHOKE/SMD/DLP11SN L1214 LQW15AN19NG00 0402

1 TP1209

2.2uF 0603 C1216 0.1uF 0402 L1241 LQW15AN33NG00 0402 C1214 0.1uF 0402 C1221 0.1uF 0402 R1225 4.7K 0402

1 TP1216

6.8pF 0402 L1212 LQW15AN13NG00 0402 L1219 nc 0402

1 TP1214

1 TP1207

RFN_LG15 RFP_LF16 GND_RX 1F14 VCOCREGK16 RFP_UH16 RFN_UJ15 VDD_SX1L15 VCOREGOUTT14 VCTRLR11 VCOMONR13 DEMODCLK_PN7 DEMODCLK_NM8 PAD_SDATM10 PAD_SCLTN9 QINK6 QIPL5 IIPJ7 BBPGA_CTRL_2D10 BBPGA_CTRL_1E9 IINH6 WBPDOUTR7 ATESTP8 AVSS33_1P6 VDD28C15 VDD12D16 VDD_RX1E15 RESETD14 RFVGA_CTRLB14 DGNDC13 DGNDE13 GND_RX 1G13 GND_SX 1H14 VDD12M16 GND_SX 1M14 VDD28N15 VDD28P16 UART_TXN13 UART_RXP14 VDD12R15 VDD18T16 VDD_RX3B12 VDD18QA11 VDD18B10 DGND C11 GND_RX2D12 GND_RX2E11 GND_RX2F12 GND_RX3F10 GND_RX1G11 GND_SX2H12 GND_SX2H10 GND_RX3G9 DGNDA9 DGNDC9 GND_RX3F8 GND_RX3H8 VDD18QB8 VDD18QA7 VDD28B6 RF_AGCA5 DGNDE5 GPIO_DATA0C5 GPIO_DATA1D6 GPIO_DATA2B4 GPIO_DATA3C7 GPIO_DATA4D8 GPIO_DATA5E7 GPIO_DATA6D4 GPIO_DATA7A3 GPIO_DATA8A1 GPIO_DATA9F6 GPIO_DATA10C3 VDD28 B2SDIO_CMD C1SDIO_CLK D2SDIO_DATA_0 E1SDIO_DATA_1 E3SDIO_DATA_2 F2SDIO_DATA_3 G3DGND F4VDD12 G1VDD28 H2EJTAG_SRST L1EJTAG_RTCK K2EJTAG_TDO J3EJTAG_TDI G7EJTAG_TMS G5EJTAG_TCK J1EJTAG_TRST H4RESET_TUNER J5XTALPD K4TSPD_TUNER L3 DIGPDM4 VDD12 M2DGND N3AVSS12_1 N1AVDD12_1 P2AVDD12_2 R1XOC R EG T2AVSS12_2 R3XOR EGOU T P4XTAL_P T4 VDD_DIGR5 LOOUTPN5 LOOUTNM6 AVDD33_1T6 GND_DIGL7 GND_DIGL9 GND_RX3K8 GND_DIGJ9 XTAL_32KT8 GND_SX2J11 GND_SX3K10 GND_SX3L11 VDD_SX2T10 VDD18R9 VDD28P10 DGNDN11 DGNDM12 DGNDP12 VDD18T12 U1201 MT5151 MCM TBGA124(7x7)/B0.32/P0.4/SMD C1245 100pF 0402 C1248 1000pF 0402 R1210 4.7K 0402 C1247 15pF 0402 C1225 0.1uF 0402 C1201 1uF 0603 C1204 0.1uF 0402 C1209 0.1uF 0402

1 TP1217

0.1uF 0402 C1253 0.5pF 0402 C1211 0.1uF 0402 C1227 2.2uF 0603 C1246 1000pF 0402 R1208 NC 0402 C1228 0.1uF 0402

1 TP1210

33nH, 5%, LQW15A, wirewound 0402 R1230 33pF 0402 C1241 82pF 0402 C1243 82pF 0402 C1213 22pF 0402 C1233 1uF 0402 C1203 0.1uF 0402 VCC_RF VCC_RF VCC_RF VCC_RF DTV_AVDD28 DTV_VDD18 DTV_DVDD12 DTV_VDD18 VCC_RF DTV_VDD18Q DTV_DVDD12 DTV_DVDD28 DTV_VDD18 DTV_DVDD28 DTV_DVDD28 DTV_VDD18DTV_VDD18Q DTV_AVDD12DTV_DVDD28 DTV_VDD18QDTV_DVDD12 DTV_DVDD28 DTV_DVDD28 VCC_RF DTV_AVDD28 DTV_AVDD12 DTV_DVDD12 DTV_1V2 DTV_2V8 DTV_2V8 DTV_1V8VGP2 DTV_1V8 VCORE2 DTV_1V2 VCC_PA VBAT MC2CK 2,5 MC2DA0 2,5 MC2DA1 2,5 MC2CM0 2,5 RX D232A4 TXD232A4 GPIO121_DTV_PWR_EN2 GPIO1282 SPI_MISO 2,5 SPI_MOSI 2,5 CLOSE U1 UHF CLOSE U1 CLOSE U1 Put more ground via between UHF network and VHF network SDIO/SPI MUX pin to MT6516 EJTAG Debug pin (Test pinર列዆ᄁ) Dig out layer 2 of this xtal and layer 3 is solide ground SDIO is mux pin with SPI TOP_MODE10 TOP_MODE8 Strap Pin ڐRFVGA_CTRL ball ڐRF_AGC ball CLOSE U1 Sam modified 12/19 VHF VHF POWER DTV Reference Design (Dual-Band: VHF & UHF) RF 2.8V LDO Diplexer & ANT Matching 26M XTAL UHF SAW Filter VHF Band-select Filter Balun Balun Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 172 TP1213~1217 Test pinڐball׳ ,不஗Չ˼數Зᇞ༨൳ JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO DTV_DVDD12 DTV_DVDD28 DTV_AVDD12 DTV_AVDD12 JTAG_SRST JTAG_RTCK JTAG_RST# DTV_DVDD12 DTV_DVDD28 DTV_AVDD28 DTV_VDD18 DTV_DVDD28 DTV_VDD18 DTV_DVDD12 RF_AGCRF_AGC_T DTV_DVDD28 DTV_VDD18 DTV_VDD18Q RX D232A TXD232A DTV_DVDD28 DTV_DVDD28 DTV_DVDD12 /M T5151_RESET DTV_DVDD28 DTV_DVDD12 RF_AGC_TRF_AGC_T DTV_VDD18Q DTV_VDD18Q DTV_DVDD28 DTV_VDD18Q RF_AGC DTV_VDD18 TXD232A TXD232A TXD232A TXD232A JTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDOJTAG_TDO /MT5151_RESET VCC_RF DTV_VDD18Q TXD232A TXD232A RX D232A RX D232A 1TP1201 TP30MIL 0.1uF 0402 3 4 J903 MM8130-2600B COAXIAL/CON/MM8130-2600B D801 ESD1P0RFL In1 GND2 GND3 OUT4 GND5 U1202 LP92H (B8763) FILTER/SMD/LP92A/EPCOS 0.1uF 0402 C1290 0.1uF 0402 L1210 LQW15AN19NG00 0402 R1234 1K 0402 R1233 1K 0402 0.1uF 0402 2.2uF 0603 C1224 0.1uF 0402 C1230 0.1uF 0402 VIN4 CE1 VSS2 VOUT 3 U1200 XC6221A282NR SSOT-24-4/XC6221 0.1uF 0402 R1211 100K 0402 C1252 47nF 0402 C1123 1uF (X5R) 0402 C1208 0.1UF 0402 DTV ANT PAD/1P/3.58X5.56 ANT903 0.1uF 0402 C1232 NC 0402 R1228 NC 0402 Unbal1 Bal 2 Bal 3GND4 Z1206 DLP11SN900HL2 L/CHOKE/SM D/DLP11SN 0.1uF 0402 C1207 2.2uF 0603 C1221 0.1uF 0402 C1214 0.1uF 0402 R1225 4.7K 0402 6.8pF 0402 L1212 LQW15AN13NG00 0402 RFN_LG15 RFP_LF16 GND_RX 1F14 VCOCREGK16 RFP_UH16 RFN_UJ15 VDD_SX 1L15 VCOREGOUTT14 VCTRLR11 VCOMONR13 DEMODCLK_PN7 DEMODCLK_NM8 PAD_SDATM10 PAD_SCLTN9 QINK6 QIPL5 IIPJ7 BBPGA_CTRL_2D10 BBPGA_CTRL_1E9 IINH6 WBPDOUTR7 ATESTP8 AVSS33_1P6 VDD28C15 VDD12D16 VDD_RX 1E15 RESETD14 RFVGA_CTRLB14 DGNDC13 DGNDE13 GND_RX 1G13 GND_SX 1H14 VDD12M16 GND_SX 1M14 VDD28N15 VDD28P16 UART_TXN13 UART_RXP14 VDD12R15 VDD18T16 VDD_RX3B12 VDD18QA11 VDD18B10 DGND C11 GND_RX2D12 GND_RX2E11 GND_RX2F12 GND_RX3F10 GND_RX1G11 GND_SX2H12 GND_SX2H10 GND_RX3G9 DGNDA9 DGNDC9 GND_RX3F8 GND_RX3H8 VDD18QB8 VDD18QA7 VDD28B6 RF_AGCA5 DGNDE5 GPIO_DATA0C5 GPIO_DATA1D6 GPIO_DATA2B4 GPIO_DATA3C7 GPIO_DATA4D8 GPIO_DATA5E7 GPIO_DATA6D4 GPIO_DATA7A3 GPIO_DATA8A1 GPIO_DATA9F6 GPIO_DATA10C3 VDD28 B2SDIO_CMD C1SDIO_CLK D2SDIO_DATA_0 E1SDIO_DATA_1 E3SDIO_DATA_2 F2SDIO_DATA_3 G3DGND F4VDD12 G1VDD28 H2EJTAG_SRST L1EJTAG_RTCK K2EJTAG_TDO J3EJTAG_TDI G7EJTAG_TMS G5EJTAG_TCK J1EJTAG_TRST H4RESET_TUNER J5XTALPD K4TSPD_TUNER L3 DIGPDM4 VDD12 M2DGND N3AVSS12_1 N1AVDD12_1 P2AVDD12_2 R1X OCREG T2AVSS12_2 R3X OREGOUT P4XTAL_P T4 VDD_DIGR5 LOOUTPN5 LOOUTNM6 AVDD33_1T6 GND_DIGL7 GND_DIGL9 GND_RX3K8 GND_DIGJ9 XTAL_32KT8 GND_SX2J11 GND_SX3K10 GND_SX3L11 VDD_SX2T10 VDD18R9 VDD28P10 DGNDN11 DGNDM12 DGNDP12 VDD18T12 U1201 MT5151 MCM TBGA124(7x7)/B0.32/P0.4/SMD C1245 100pF 0402 R1210 4.7K 0402 C1225 0.1uF 0402 C1201 1uF 0603 C1204 0.1uF 0402 0.1uF 0402 1TP1200 TP30MIL OUT3 GND2 VCON 1 GND4 X1200 TXC 26M TCXO3225 C1249 0.1uF 0402 C1211 0.1uF 0402 C1253 0.5pF 0402 C1227 2.2uF 0603 R1208 NC 0402 C1228 0.1uF 0402 L1216 BLM15EG121SN1 0402 0.1uF 0402 VCC_RF VCC_RF VCC_RF VCC_RF DTV_AVDD28 DTV_VDD18 DTV_DVDD12 DTV_VDD18 VCC_RF DTV_VDD18Q DTV_DVDD12 DTV_DVDD28 DTV_VDD18 DTV_DVDD28 DTV_DVDD28 DTV_VDD18DTV_VDD18Q DTV_AVDD12DTV_DVDD28 DTV_VDD18QDTV_DVDD12 DTV_DVDD28 DTV_DVDD28 VCC_RF DTV_AVDD28 DTV_AVDD12 DTV_DVDD12 DTV_1V2 DTV_2V8 DTV_2V8 DTV_1V8VGP2 DTV_1V8 VCORE2 DTV_1V2 VCC_PA VBAT MC2CK 2,5 MC2DA0 2,5 MC2DA1 2,5 MC2CM0 2, 5 RX D232A4 TXD232A4 GPIO121_DTV_PWR_EN2 GPIO1282 SPI_MISO 2,5 SPI_MOSI 2,5 CLOSE U1 UHF CLOSE U1 CLOSE U1 Put more ground via between UHF network SDIO/SPI MUX pin to MT6516 EJTAG Debug pin (Test pinર列዆ᄁ) Dig out layer 2 of this xtal and layer 3 is solide ground SDIO is mux pin with SPI TOP_MODE10 TOP_MODE8 Strap Pin ڐRFVGA_CTRL ball ڐRF_AGC ball CLOSE U1 POWER DTV Reference Design (UHF band only) RF 2.8V LDO 26M XTAL UHF SAW Filter Balun ANT Matching & RF connector Delete VHF network For UHF band only Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 174 Reference Interface Assignment MT5151 BGA SDIO (4-bit) RSTB 2.8V RF LDO LDO EN PMU 2.8V 1.8V 1.2V Example in MT6516 Type Pin Function GPIO128 RSTB GPIO121 LDO EN MC0CM0 MC0DA0 MC0DA1 MC0DA2 MC0DA3 MC0CK GPIO *' SDIO Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 175 Key Component z There are four key components on DVBT reference design, SAW filter, crystal, Balun, and high Q wirewround inductor. L1212,L1210,L1214,L1239,L1241,L1240 L1213,L1217,L1218MurataLQW15A seriesInductor Z1206, Z1207MurataDLP11SN900HL2Balun X1200eCERAFL2600025Crystal U1202EPCOSB8763 (LP92H)Filter DesignatorVendorPart numberItem Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 177 Schematic Design Guide z The ESD protection of RF input is poor, ESD device should be added to protect RF circuit. z UHF SAW filter & VHF hybrid filter should be added in RF path to filter out-band and GSM interference signal. z To ensure good performance, the frequency accuracy of crystal should meet +/- 30 ppm requirement with loading capacitance SPEC of 10pF. z In order to have better power noise immunity, RF 2.8V supply voltage is provided by stand-alone LDO. z IO-2.8V and SDRAM-1.8V should be provided by linear regulation power. Core-1.2V could be DC-DC power. z RF Balun is strongly suggested to use for optimal RF performance Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 178 DTV Layout Guide – 1/3 z DTV placement should keep away from GSM and CDMA related circuits. z Don't place DTV near noisy components, such as PMIC, memory or other clock-wise/ high- swing signal. z RF trace of DTV should keep away from high speed signal, such as LCD and camera data bus. z To avoid any other noisy layout closer to RF ANT port z Put solid ground polygon and ground via surround layout area for metal casing. DTV MT6516 GSM PA GSM RF PMIC BT+WLAN GPS Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 179 DTV Layout Guide – 2/3 Shielding case RF Front-end z Keep RF trace on same layer, don't use via on RF trace as possible as you can. z To avoid interference, use shielding case to cover DTV related circuits. z Put RF Balun as closer as possible to chip input. And Make routing symmetrically. z Put RF front-end routing in 50ohm trace and let those inductors in orthogonal direction with each others. z Place 2.8V RF LDO and crystal near to MT5151 as possible as you can. z Dig out the copper plating under Crystal pad output (pin3) to chip in inner layer . z RF trace should keep 50ohm impedance and as short as possible. z Place bypass capacitors close to power pin. z Put DTV’s off-chip components surround by it in sequence to minimize rounting. z Put RFAGC in/ out R-C network as closer as possible to pin crystal RF Balun Bypass Cap. C1203 Bypass Cap. C1209 Bypass Cap. C1214 Bypass Cap. C1204 Bypass Cap. C1230 RFAGC In R-C RFAGC out R-C Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 180 DTV Layout Guide – 3/3 Layer2 Layer3 z As below shown, make a dig-out clearance gap (>= 6mil) to cut ground plane from layer 2 to layer 6 to isolate RF and digital GND. z Dig out layer 2 ploygon under RF front-end network Start to cut GND plane End to cut GND plane Dig-out Dig-out Balls inside this RF Area: B16~P16;G15~N15;F14~M14; G13;D12~H12;E11~L11;F10~K10 ;G9~L9;F8~K8 Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 187 MTK FM Solution ConnectionMTK FM Solution Connection MT6188 or MT6189CN MTK BB series (except MT6205) FM audio output System audio output Control interface Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 189 Layout GuidelinesLayout Guidelines ▪ Placement – Place the FM chip near the earphone jack. Avoid high-speed digital devices, such as memory devices, near the RF signal area. – Bypass cap for power should be placed beside the VCCVCO pin (MT6188 pin 9; MT6189 pin 13). ▪ Routing – FM antenna trace should have a 50 Ȥ impedance. – Power should be routed to the bypass cap and the VCCVCO pin first, then to all other power pins on the FM chip. See the following pages for example. – Apply a single solid ground fo r all FM block ground signals. See the following pages for example. – Protect the following areas with GND vias and planes:

RF signal from the earphone jack all the way to the FM chip;
32.768 kHz or 26 MHz signal;
VCO inductor (MT6188 pins 11,12; MT6189 pins 15,16);
Loop filter of MT6189 (connected to pin 17). Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 190 Power Feeding Network Layout GuidelinesPower Feeding Network Layout Guidelines ▪ It is recommended to connect power of MT6189 and MT6188 sequentially, and placing the capacitance beside VCCVCO. (Examples below.) ▪ The FM power should be monopolized: do not connect other blocks to VCC_FM. VCCVCO VCCST VDD VCCRF Bad MT6188 VCCVCO VDD VCCRF VCCST VCCAMP Good MT6189 Do not connect to other blocks through FM block. This capacitor cannot be placed here. VCCVCO VDD VCCRF Good MT6188 VCCST Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 191 Ground LayoutGround Layout ▪ Ground GNDVCO, the loop filter, and front-end matching on the same ground plane. – Using different ground planes connect ed by wire makes the FM signal susceptible to interference with another signals on the system. – This rule is applicable for both MT6189 and MT6188: all GND pins must be located on the same ground plane. Bad MT6189 Good MT6189 All ground pins are connected by wires. This design contains no ground plane. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 192 Other System Considerations for FMOther System Considerations for FM ▪ Rule 1: Protect the BB 32.768kHz crystal layout – If the 32.768kHz signal is corrupted by digital signals, FM channel locking may be unstable. – BB 32.768kHz crystal layout rules:

Place the 32.768kHz crystal unit close to the BB, and L2 beneath crystal needs to be complete ground. The crystal must be protected by ground vias and ground planes.
Do not route power, MCP, FM I2C traces near 32.768kHz crystal unit.
The 32.768kHz traces between crystal unit and BB should be on top layer. ▪ Rule 2: Backlight driver adoption – USE a charge pump backlight driver. – DO NOT USE a DC-DC backlight driver in projects with FM application. Doing so may cause increased noise levels when the backlight is on. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 194 Audio Interface Design GuidelinesAudio Interface Design Guidelines ▪ On earphone pins AFL, AFR, and MIC: –P l a c e 1 nF shunt capacitors (shunt to earphone GND pin) closest to the earphone jack. To improve earphone echo performance, connect the 3 capacitors from each pin to the earphone GND pin separately. (See next page.) – Place the BLM18BD252SN1 series bead second closest to the earphone jack. – No other components can be closer to the earphone jack. ▪ Place a series 150 nH inductor on earphone GND pin as antenna matching. ▪ Earphone GND wire (FM_ANT) should not be connected to the earphone connector shell. ▪ An earphone longer than 150 cm is recommended for better performance. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 195 FM_ANT MIC E-L E-R others FM tuner MT6188 Matching inductor PCB Earphone Earphone Connector 22uH Earphone_GND MIC E-L E-R NC L R MIC Audio Interface Design ConceptAudio Interface Design Concept Add caps on L, R paths, to provide extra path for FM. Add beads on headset related pins, to avoid interference (or bypass) path. These beads should be placed as close to the phone jack as possible. This point is the earphone GND. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 196 1~2 dBEarphone length > 150 cm 2~3 dB1 nF shunt cap between earphone AFL, AFR, MIC, and GND pins 14.5 dBSeries beads on earphone AFL, AFR, and MIC pins Improvement amount Wireless Sensitivity EnhancementWireless Sensitivity Enhancement ▪ Each earphone suggestions improves wireless sensitivity significantly. The following table shows the improvement amount based on MTK’s experiments. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 198 C402 1nF 1 2 C403 1nF 1 2 NP_NC1 NP_NC2 J401 MINI_JACK_6P FM_ANT {1} ESD400 VCE.1 . 2 ESD401 VCE.1 . 2 ESD402 VCE.1 . 2 XMICP C404 33pF 1 2 L101 22uH 2 1 C405 33pF 1 2 B402 2500 Ohm @ 100 MHz B403 2500 Ohm @ 100 MHz L101 150nH XSPK_L B401 2500 Ohm @ 100 MHz XSPK_R XSPK_L C401 1nF 1 2XSPK_R Audio Interface Reference CircuitAudio Interface Reference Circuit (2.5mm or 3.5mm Earphone Jack)(2.5mm or 3.5mm Earphone Jack) Add beads on these lines. These beads should be placed as close to the earphone jack as possible. To audio amp, mic circuits These caps cannot be closer to the earphone jack than the beads. Series 150 nH inductor for antenna matching. Shunt these earphone lines with 1nF caps. Connect this 22uH inductor to mobile phone ground. BLM18BD252SN1BLM18BD252SN1 can be used instead of a 22 uH inductor. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 199 Mini USB Earphone DesignMini USB Earphone Design ▪ With only 1 GND pin on IO connector ▪ With 2 GND pins on IO connector Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 200 These 4 pins are directly connected to PCB ground. DO NOT connect these pins to the GND/FM_ANT pin. 4 outer shell pins of the IO connector. Mainly used for better connector strength. Can also serve as charger GND. MECH_GND CANNOT be directly connected to PCB ground. MUST be connected to PCB ground through a 22uH inductor. GND for all Mini USB accessories and FM antenna. GND/FM ANT Notes for PCB designFunctionIO pin name IO connector pin description Earphone GND wire connection. Charger GND wire connection. Charger: Connect these pins. Earphone: DO NOT connect these pins. Mini USB IO Connector Design Recommendation: Mini USB IO Connector Design Recommendation: Only 1 GND Pin on IO ConnectorOnly 1 GND Pin on IO Connector Accessory interior design suggestion ▪ The earphone GND wire MUST be used for the FM antenna. Inside the earphone, the GND wire CANNOT be connected to any other wire or to the outer shell in any way. Other wires inside the earphone CANNOT be connected to PCB GND. ▪ The 22uH inductor cannot tolerate high current. For high current application, such as a charger, connect the charger GND wire inside the charger to both the GND/FM_ANT pin and the charger outer shell. ▪ In this example, the earphone GND wire is connected to IO connector pin6, and the charger GND wire is connected to pin6 and the charger outer shell. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 201 MP3_OUTL0 ESD203 1 122 T204 VCE . 1.2MP3_OUTR0 R210 33R L202 22uH R209 33R L201 150nH IO200 Mini USB 10 Pin Plug NC1 MP3_OUTL2 MP3_OUTR3 UTXD14 URXD15 GND/FM_ANT6 MIC_IN7 USB_DM8 USB_DP9 VCHG10 MECH_GND 11 MECH_GND 12 MECH_GND 13 MECH_GND 14 ESD201 11 2 2 ESD203 1 122 ESD210 1 122 MIC0 C225 1nF T211 . 1.2 T205 VCE .1 . 2 T204 VCE . 1.2 VCHG L204 BLM18BD252SN1 L205 BLM18BD252SN1 L206 BLM18BD252SN1 FM_ANT C223 1nF C224 1nF USB_DP0 USB_DM0 UTXD1 URXD1 Connect this 22uH inductor to mobile phone ground. Series 150 nH inductor for antenna matching. Shunt these earphone lines with 1nF caps. Add beads on these lines. These beads should be placed as close to the earphone jack as possible. These caps cannot be closer to the earphone jack than the beads. To audio amp, mic circuits Audio Interface Reference Circuit:Audio Interface Reference Circuit: Only 1 GND Pin on IO ConnectorOnly 1 GND Pin on IO Connector Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 202 Accessory interior design suggestion ▪ The earphone GND wire MUST be used for the FM antenna. Inside the earphone, the GND wire CANNOT be connected to any other wire or to the outer shell in any way. Other wires inside the earphone CANNOT be connected to PCB GND. ▪ The 22uH inductor cannot tolerate high current. For high current applications, such as a charger, use another IO connector pin if available. The charger GND wire inside the charger can also be connected to the charger outer shell. ▪ In this example, the earphone GND wire is connected to IO connector pin6, and the charger GND wire is connected to pin1 and possibly the charger outer shell as well. These 4 pins are directly connected to PCB ground. DO NOT connect these pins to EAR_GND/FM_ANT. 4 outer shell pins of the IO connector. Mainly used for better connector strength. Can also be served as charger GND. MECH_GND This pin is directly connected to PCB ground. DO NOT connect this pin to the EAR_GND/FM_ANT pin. GND for Mini USB accessory, with large GND current. CKT_GND CANNOT be directly connected to PCB ground. MUST be connected to PCB ground through a 22uH inductor. Earphone GND, also FM antenna.EAR_GND/FM_ANT Note for PCB designFunctionIO pin name Earphone GND wire connection Charger GND wire connection Inside earphone, DO NOT connect these pins. IO connector pin description Mini USB IO Connector Design Recommendation: Mini USB IO Connector Design Recommendation:

2 GND Pins on IO Connector2 GND Pins on IO Connector

Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 203 MP3_OUTL0 ESD203 1 122 T204 VCE . 1.2MP3_OUTR0 R210 33R L202 22uH R209 33R L201 150nH IO200 Mini USB 10 Pin Plug CKT_GND1 MP3_OUTL2 MP3_OUTR3 UTXD14 URXD15 GND/FM_ANT6 MIC_IN7 USB_DM8 USB_DP9 VCHG10 MECH_GND 11 MECH_GND 12 MECH_GND 13 MECH_GND 14 ESD201 11 2 2 ESD203 1 122 ESD210 1 122 MIC0 C225 1nF T211 . 1.2 T205 VCE .1 . 2 T204 VCE . 1.2 VCHG L204 BLM18BD252SN1 L205 BLM18BD252SN1 L206 BLM18BD252SN1 FM_ANT C223 1nF C224 1nF USB_DP0 USB_DM0 UTXD1 URXD1 Connect this 22uH inductor to mobile phone ground. Series 150 nH inductor for antenna matching. These caps cannot be closer to the earphone jack than the beads. To audio amp, mic circuits Shunt these earphone lines with 1nF caps. Add beads on these lines. These beads should be placed as close to the earphone jack as possible. Audio Interface Reference Circuit:Audio Interface Reference Circuit: Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 204 ▪ Series beads on earphone pins AFL, AFR, and MIC – Suggested: 06030603--size BLM18BD252SN1 beadsize BLM18BD252SN1 bead However, if board space is limited, 0402-size bead BLM15BD182SN1 or BLM15HD182SN1 can be used instead. ▪ Inductor connecting earphone GND wire to board GND – Suggested: 22 22 uHuH inductorinductor or BLM18BD252SN1 beadBLM18BD252SN1 bead However, if the earphone GND pin serves as the only GND path for the charger, then this component must be able to tolerate high current. The components in the table below can be used instead. Usable, but its wireless performance is the worst among the three. Not recommended unless such a high current is required. 1100 mA100 MHz08050.47 uHLQM21PNR47MC0D 800 mA90 MHz08051.0 uHLQM21PN1R0MC0D 485 mA100 MHz06031.0 uHLQH2MCN1R0M02 NotesRated current Self-resonant frequencySizeInductor value Murata part number Component Replacement SuggestionsComponent Replacement Suggestions Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 205 FM Design ChecklistFM Design Checklist Follow the FM system layout guide.´5 MT6189 projects only: A high Q inductor is used (for the 15 nH VCO inductor).´7 Mini USB earphones: Follow MTK’s suggestion for GND connection on PCB and inside earphone.´8 The FM antenna path is routed using a 50Ȥ RF trace, and a 150 nH inductor is used for antenna matching.´6 The VCC bypass cap is placed beside the VCCVCO pin, and the VCC feeding network routed is properly.´4 The earphone is longer than 150 cm.´3 1 nF shunt caps are placed between the AFL, AFR, MIC, and GND pins of the earphone jack.´2 Series beads are placed on the AFL, AFR, and MIC pins of the earphone jack.´1 CheckpointDone!Item If you require MTK’s assistance in FM design, please prepare this checklist and submit it along with schematics, layout files and earphone schematics/data sheet. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 206 More Detailed FM Earphone More Detailed FM Earphone Antenna IllustrationsAntenna Illustrations ▪ Illustration of FM earphone antenna ▪ FM earphone antenna pin definition ▪ FM earphone antenna troubleshooting Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 207 Illustration of FM Earphone Antenna (1/2)Illustration of FM Earphone Antenna (1/2) ▪ On next page, there is an illustration to explain the respective purposes of each components. It can help customers to know how to enhance FM wireless performance. ▪ Besides FM schematics, wrong earphone pin definition also destroys FM wireless performance. ▪ Notice that the only one path from Earphone_GND to PCB_GND is via FM_ANT Pin and 22uH. If there are another paths existing, FM receiving signal would degrade seriously. This issues frequently happens on customers’ projects. ▪ Four pins are enough on earphone including R, L, MIC, and Earphone_GND. ▪ Only Earphone_GND can be used as FM Antenna. ▪ Place all FM related components near earphone jack in PCB layout. Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 208 Illustration of FM Earphone Antenna (2/2)Illustration of FM Earphone Antenna (2/2) 5. Earphone lengthEarphone length 165 cm is recommended. 4. 150 150 nHnH Earphone antenna matching 3. 22 22 uHuH

Earphone GND connects to PCB GND only via this 22 uH.
RF choke @100MHz 52134 2. Parallel 1.0 Parallel 1.0 nFnF CAP_shortCAP_short @100MHz@100MHz Conduct FM signal to FM input from R, L, and MIC traces. FM receiving signal can be enhanced. 1. Serial Beads 2.5 Serial Beads 2.5 kOhmkOhm @100MHz@100MHz Avoid FM signal loss through R, L, and MIC traces. FM_ANT MIC E-L E-R others FM tuner MT6188 150 nH Earphone Connector 22uH Earphone_GND MIC E-L E-R NC L R MIC EarphonePCB 50 ohm Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 209 FM Earphone Antenna Pin Definition (1/3)FM Earphone Antenna Pin Definition (1/3) ▪ The following illustrates the correct pin definition for the FM earphone antenna: FM_ANT MIC E-L E-R PCB_GND others Earphone Connector Earphone_GND MIC E-L E-R NC EarphonePCB Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 210 FM Earphone Antenna Pin Definition (2/3)FM Earphone Antenna Pin Definition (2/3) ▪ Some incorrect pin definitions – Case 1: Floating FM_ANT pin – Case 2: Earphone_GND connects to both FM_ANT pin and PCB_GND FM_ANT MIC E-L E-R PCB_GND others MIC E-L E-R Earphone_GND EarphonePCB FM_ANT MIC E-L E-R PCB_GND others Earphone_GND MIC E-L E-R GND EarphonePCB Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 211 FM Earphone Antenna Pin Definition (3/3)FM Earphone Antenna Pin Definition (3/3) ▪ Some incorrect pin definitions – Case 3: Unnecessary GND pin used on the earphone side – Case 4: Unnecessary signal pins used on the earphone side FM_ANT MIC E-L E-R PCB_GND others Earphone_GND MIC E-L E-R GND EarphonePCB FM_ANT MIC E-L E-R PCB_GND others Earphone_GND MIC E-L E-R others EarphonePCB Free Datasheet http://www.Datasheet-PDF.com/

Copyright © MediaTek Inc. All rights reserved. 212 Case 1SHORTOPENOPEN Case 2SHORTSHORTSHORT CorrectOPENOPENSHORT Issue PCB_GND to Earphone_GND FM_ANT to PCB_GND FM_ANT to Earphone_GND FM Earphone Antenna TroubleshootingFM Earphone Antenna Troubleshooting ▪ Simple troubleshooting techniques: a. Check that only four earphone pins are used. ( Case 3, Case 4) b. Remove the 22 uH inductor. c. Plug in the earphone. d. Use a digital multimeter to check whether the connections between PCB_GND, FM_ANT pin, and Earphone_GND pin are OPEN or SHORT. Free Datasheet http://www.Datasheet-PDF.com/

Product Information

XC6401 specifications and overview.

Summary

MT6516 Design Notice V1.0

Description

MT6516 Design Notice V1.0

Source title XC6401 Datasheet(PDF) - List of Unclassifed Manufacturers

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