MC33410 MOTOROLA | Alldatasheet
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/C0077/C0067/C0051/C0051/C0052/C0049/C0048 DUAL CVSD/PLL CORDLESS PHONE SYSTEM FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP–48) Device Operating Temperature Package
ORDERING INFORMATION
XC33410FTA –40 ° to +85°C LQFP–48 SEMICONDUCTOR TECHNICAL DATA Order this document by MC33410/D 1MOTOROLA RF/IF DEVICE DATA /C0080/C0114/C0111/C0100/C0117/C0099/C0116 /C0080/C0114/C0101/C0118/C0105/C0101/C0119 /C0068/C0117/C0097/C0108 /C0067/C0086/C0083/C0068/C0047/C0080/C0076/C0076 /C0067/C0111/C0114/C0100/C0108/C0101/C0115/C0115 /C0080/C0104/C0111/C0110/C0101 /C0083/C0121/C0115/C0116/C0101/C0109 The MC33410 Dual CVSD/Cordless Phone system is designed to fit the requirements of a 900 MHz digital cordless telephone system. The device contains a CVSD (Continuously Variable Slope Delta Modulator/Demodulator) Encoder to digitize the speech for the RF transmission, and a CVSD Decoder to reconstruct the received digital speech from the RF receiver. Provisions are made to transmit and receive data as well. Included are three PLLs (Phase–Locked Loops). Two are intended for use with external VCOs and 64/65 or 128/129 dual modulus prescalers, and can control the transmit and receive (LO1) frequencies for the 900 MHz communication. The third PLL is configured as the 2nd local oscillator (LO2), and is functional to 80 MHz. Also included are muting, audio gain adjust (internal and external), low battery/carrier detect, and a wide range for the PLL reference frequency. The power supply range is 2.7 to 5.5 V. A data only (non–voice) mode is also included.
- Two Complete CVSD Sections for Full Duplex Operation
- Two PLLs and an LO Suitable for a 900 MHz System
- Adjustable Detection for Low Battery or Carrier Signal (RSSI)
- Minimal External Components
- Encode Path Includes Adjustable Gain Amplifiers, Filters, Mute, CVSD Encoder, Data Insert, and Scrambler
- Decoder Path Contains Data Slicer, Clock Recovery, Descrambler, Data Detect, CVSD Decoder, Filters, Mute and Power Amplifier
- Data can be Transmitted During Voice Conversation with Minimal or No Noticeable Audio Disruption
- Idle Channel Noise Control
- Independent Power Amplifier with Differential Outputs, Mute
- Selectable Frequency for Switched Capacitor Filters, CVSD Function, PLLs, and the LO
- Reference Frequency Source can be a Crystal or System Clock
- Serial µP Port to Control Gain, Mute, Frequency Selection, Phase Detector Gain, Power Down Modes, Idle Channel Control, Scrambler Operation, Low Battery Detect, and Others
- Mode Available for Data Only Transmission (non–voice)
- Ambient Temperature Range: –40 to 85/C0095C
- Power Supply Range: 2.7 to 5.5 V
- Power Down Modes for Power Conservation
- 48 Pin LQFP with 0.5 mm Lead Pitch This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. Motorola, Inc. 1998 Rev 0
2 MOTOROLA RF/IF DEVICE DATA
Anti–Alias LPF Gain Adj. Gain Adj. Mute LP Filter PLL Programmable Counters Dec. Clock CVSD Encoder VCO+ PreScaler Power Amp PLL VCO+ PreScaler 2nd LO LPF Tank MPU Interface MPU Low Batt /CD Idle Channel Data Det. Register SC Encode Clock LO Data Register Low Battery/ CD Status Dec. Clock Descrambler Clock Recovery Idle Channel Scrambler Data Slicer Data Out Digital Speech/ Data In Digital Speech/ Data Out Analog Speech Analog Speech Ref LP FilterMute Mute Ref. Freq. Ref SC SC PRELIMINARY SPECIFICATIONS (Subject to change) Parameter Symbol Min Typ Max Units Supply Voltage – 2.7 to 5.5 – V Supply Current (All sections active) – 13 – mA Remote Gain Adjust Range – 16 – dB Receive Path Gain Control Range – 28.5 – dB Output Current Capability (PAO+, PAO–) – ± 5.0 – mA Max. 2nd LO frequency – 80 – MHz Phase Detector Charge Pump Output Current µA High – ±400 – Low – ±100 – Digital Input Signal Amplitude to Data Slicer – >200 – mVpp Operating Ambient Temperature – –40 to +85 – °C NOTE: 1. Above specs represent design objectives, and are subject to change.
Figure 1. Typical Applications Circuit NOTE: Pin numbers are not firm and are not to be used for design–in purposes.
4 MOTOROLA RF/IF DEVICE DATA
RECOMMENDED OPERATING CONDITIONS (Subject to change) Parameter Symbol Min Typ Max Units Supply Voltage – 2.7 to 5.5 – V CVSD Clock Rate – 32, 50, or – kHz Encoder in Signal Level (max) – 3.0 – Vpp Peak Output Current at PAO+, PAO– – ± 5.0 – mA Reference Frequency Amplitude (Fref In) – >200 – mVpp R x Digital Input Signal Amplitude Vpp Min – 0.20 – Max – 0 to VCC – Crystal or Reference Frequency at Pin 14 – 4.0 to 18.25 – MHz Max. Input Frequency at FRx, FTx – TBD – MHz LO2 VCO Control Voltage (Pin 44) – TBD – V Max. 2nd LO Frequency – 80 – MHz
12 Bit Reference Counter Range (Note 1) – 3 to 4095 – –
13 Bit N Counter Range (Note 1) – 3 to 8191 – –
7 Bit A Counter Range (Note 1) –
with a 64/65 Modulus Prescaler – 0 to 63 – with a 128/129 Modulus Prescaler – 0 to 127 –
14 Bit LO2 Counter Range (Note 1) – 12 to
– –
6 Bit Counters (for SCF and Encode Clock) (Note 1) – 3 to 63 – –
Receive Path Gain Control Code Range (Note 1) – 6 to 25 – – Operating Ambient Temperature – –40 to 85 – °C NOTES: 1. Values specified are pure numbers to the base 10. 2. Above specs represent design objectives, and are subject to change. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION ÁÁÁÁ ÁÁÁÁ Pin ÁÁÁÁÁÁ ÁÁÁÁÁÁ Name ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Description
1 FR x MC Modulus Control Output to the Rx 64/65 or 128/129 dual modulus prescaler. 2 FR x Input to the Rx PLL. 3 PLL VCC Supply pin for the Rx PLL section. Allowable range is 2.7 to 5.5 V. 4 R x PD Phase detector charge pump output of the Rx PLL. 5 PLL Gnd Ground pin for the PLL sections. 6 Tx PD Phase detector charge pump output of the Tx PLL. 7 PLL VCC Supply pin for the Tx PLL section and the MPU Serial Interface section. Allowable range is 2.7 to 5.5 V. 8 FTx Input to the Tx PLL. 9 FTx MC Modulus Control Output to the Tx 64/65 or 128/129 dual modulus prescaler. 10 EN Enable input for the µP port. This signal latches in the register address and data. 11 CLK Clock input for the µP port. Maximum frequency is 2.0 MHz. 12 Data Bi–directional data line for the µP port. In Data Modem mode, this pin provides the recovered clock. 13 Status Logic output which indicates that a predetermined 16 or 24–bit code word has been detected in the Data Detect register, and the following data word has been loaded into register 10. In Data Modem mode, this pin provides the Transmit Data clock. 14, 15 Fref In, Fref Out A crystal, in the range of 4.0 to 18.25 MHz can be connected to these pins to provide the reference frequency. If an external reference source is used, it is to be capacitively coupled to Fref In. NOTE: 1. All VCC pins must be within ±0.5 V of each other.
5MOTOROLA RF/IF DEVICE DATA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION (continued) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Name ÁÁÁÁ ÁÁÁÁ Pin 16 Low Battery/CD An open collector output. When low, indicates either the supply voltage (VCC ) is low, or the carrier level is above the threshold. This output is off when disabled. 17 Enc Out The digital output of the scrambler, which passes data from the CVSD encoder, or the Tx Data register, or the Tx 1010 Generator. Source selection is done through the /C0109P port. 18 VCC Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V. Internally connected to Pins 27 and 37. 19 Enc In The analog input to the CVSD encoder. Max. input level is 3.0 Vpp. 20 Tx Audio Out Output of the transmit speech processing section. 21 Ground Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 30 and 40. 22 MCO Output of the microphone amplifier, and input to the filters. This output has rail–to–rail capability. 23 MCI Inverting input of the microphone amplifier. Gain and frequency response is set with external resistors and capacitors. 24 Enc Cap This capacitor sets the time constant for the CVSD encoder. This pin is sensitive to leakage. 25 VAG Analog ground for the audio section and the CVSD encoder and decoder. 26 Dec Cap The capacitor sets the time constant for the CVSD decoder. This pin is sensitive to leakage. 27 VCC Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V. Internally connected to Pins 18 and 37. 28, 29 PAO+, PAO– Differential outputs of the power amplifier stage for driving an earpiece or hybrid network. The gain and frequency response are set with external resistors and capacitors. 30 Gnd Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 21 and 40. 31 PAI Input to the power amplifier stage. This pin is a summing node. 32 R x Audio Output Output of the receive speech processing section. 33 VB The capacitor filters the internal 1.5 V reference voltage. If VB is adjusted, it may be monitored at this pin. Max. load current is 10 /C0109A. 34 R x Audio In Input to the receive speech processing section. 35 Dec Out The analog output of the CVSD decoder. 36 MP1 As an output, provides the recovered Rx data, or the Data Detect output, or the data slicer output. Or it can be set to a high impedance input (600 k/C0087) for the carrier detect input signal. Selection is done through the /C0109P port. See Table 6. 37 VCC Supply input for the audio sections, filters, and CVSD blocks. Allowable range is 2.7 to 5.5 V. Internally connected to Pins 18 and 27. 38 R x Digital InputThe digital stream from the RF receiver is applied to the data slicer at this pin. Minimum amplitude is 200 mVpp. Hysteresis ≈50 mV. 39 MP2 As an output, this pin provides the recovered clock from the Clock Recovery block. As an input, the CVSD decoder clock can be applied to this pin. Or this pin may be set to a disabled state. Selection is done through the /C0109P port. See Table 7. In Data Modem mode, the data to be transmitted is input to this pin. 40 Gnd Ground for the audio sections, filters, and CVSD blocks. Internally connected to Pins 21 and 30. 41 LO2 Out Buffered output of the 2nd LO frequency. A pullup resistor is required. 42 LO2 VCC Supply pin for the 2nd LO. Allowable range is 2.7 to 5.5 V. 43, 45 LO2+, LO2– A tank circuit is connected to these pins for the 2nd LO. 44 LO2 Ctl The varactor control pin for the 2nd LO. 46 LO2 Gnd Ground for the 2nd LO section. 47 LO2 PD Phase detector charge pump output of the 2nd LO PLL. 48 LO2 Gnd Ground for the 2nd LO section. NOTE: 1. All VCC pins must be within ±0.5 V of each other.
6 MOTOROLA RF/IF DEVICE DATA
bits 14 through 11. Please refer to Figure 1. gain stage, two low pass filters, and a mute switch. capability, and the dc bias level is at VB (≈1.5 V). Gain Adjust, provides 5 levels of gain in 4.0 dB increments. It is controlled with bits 6/15–11 as shown in Table 1. Table 1. Remote Gain Adjust Other combinations for the 5 bits are invalid. noise from the previously mentioned switched capacitor filter. The mute switch at Pin 20 will mute a minimum of 60 dB. at the selected frequency, according to Table 2. Table 2. CVSD Clock/Data Rates bits 2/22–21, according to Table 3. Table 3. Minimum Step Size Table 4. Idle Channel Detection Threshold
information (CVSD Encoder or Tx 1010 Generator). scrambler can be bypassed with Bit 7/1. Table 5. Scrambler/Descrambler Tap Selection output can be inverted by setting bit 5/19 = 1. replace the Clock Recovery Clock. Table 6. MP1 Options (Pin 36) Table 7. MP2 Options (Pin 39)
1 X Disabled (Hi–Z)
for an explanation of this function. can be bypassed with bit 7/1. stored in the Tx Data Register (loaded through register 8).
8 MOTOROLA RF/IF DEVICE DATA
register 10, at which time the Status pin and bit will go low. bits 3/16–15 according to Table 2. provided to the Decoder, and is available at Pin 39. Generator can be selected with bit 6/3 at any time. bits 1/22–21, according to Table 3. subsequent switched capacitor filter. provide bandwidth limiting in the audio range. are used to set the gain according to Table 8. Table 8. Receive Gain Adjustment shaping. The pins’ dc level is VB (≈1.5 V). muting will depend on the value of the feedback resistor. 256 kHz, or as close to that as possible.
VCO, and a 64/65 or 128/129 dual modulus prescaler. a current mode with bit 7/13. A register setting is 24d (001 1000). are to be used with an external tank circuit (Pins 43 to 45). certain amount of fine tuning of the oscillator’s performance. determined by the external pullup resistor. Table 9. LO2 Capacitor Selection long as the load current on this pin does not exceed 10 µA. an RSSI circuit. The desired mode is selected with bit 6/5. bits 3/23–21), and is compared to the internal reference VB.
10 MOTOROLA RF/IF DEVICE DATA
Table 10. LB/CD Threshold Adjustment Factor the threshold. Pin 16 requires an external pullup resistor. of a Clock line, an Enable line, and a bi–directional Data line. enabled through this interface. write or read data, and can be any frequency up to 2.0 MHz.
- The Enable line is taken high.
– The first bit must be a 0 to indicate a Write operation. (0001–1010). The MSB is entered first.
- After the 5th clock pulse is low, the Enable line is taken low.
At this transition, the address is latched in and decoded.
- The Enable line is maintained low while the data bits are
bits (e.g., register 6), the unassigned bits are to be 0.
- After the last bit is entered, the Enable line is to be taken
- The Enable line must then be kept low until the next
minimum of 4 bits, with 4 clock pulses, must be entered. Figure 2. Writing Data to the MC33410 Figure 3. Reading Data from the MC33410
- The Enable line is taken high.
– The first bit must be a 1 to indicate a Read operation. (0001–1010). The MSB is entered first.
- After the 5th clock is taken low, the Enable line is taken low.
- While maintaining the Enable line low, the data is read out.
output, and the MSB will be present on this line.
- The full contents of the register are then read out (MSB first,
or three clock rising edges, respectively.
- After the last clock pulse, the Enable line is to be taken high
- The Enable line must then be kept low until the next
900 MHz wireless system for transmitting data only
circuit (but not the Carrier Detect mode). data passes through the descrambler, and is output at Pin 36. Table 11. Entering Data Modem Mode Tx Clk = Fcrystal/(16 x Counter). Figure 5 to configure Pin 12.
- Writing to register 11 is shown in Figure 5.
Figure 4. Data Modem Mode Configuration
12 MOTOROLA RF/IF DEVICE DATA
Figure 5. Entering/Exiting Data Modem Mode is effective only if bit 5/20 is set to a 1. the Data Modem mode is not in use.
- Pins 18, 27 and 37 are internally connected together, and
- Pin 3 provides power to the Rx PLL section. Pin 5 is the
- Pin 7 provides power to the Tx PLL section, and the MPU
interface. Pin 5 is the ground pin.
- Pin 42 provides power to the 2nd LO section. Pins 46 and
- Reference Oscillator Disable (bit 5/0) – The reference
- Tx PLL Disable (bit 5/1) – The 13–bit and 7–bit counters,
- Rx PLL Disable (bit 5/2) – The 13–bit and 7–bit counters,
- LO2 PLL Disable (bit 5/3) – The VCO, 14–bit counter,
charge pump output at Pin 47 will be in a Hi–Z state.
- Rx Data Path Disable (bit 5/4) – The data slicer, clock
- CVSD Decoder Disable (bit 5/5) – The CVSD Decoder and
the Rx 1010 Generator are disabled.
- Rx Audio Path Disable (bit 5/6) – The anti–aliasing filter,
low pass filter, and variable gain stage are disabled.
- Power Amplifier Disable (bit 5/7) – The two power
- Tx Audio Path Disable (bit 5/8) – Disables the microphone
amplifier, low pass filter, and smoothing filter.
- CVSD Encoder Disable (bit 5/9) – The CVSD Encoder, Idle
register, and the scrambler are disabled.
- Low Battery/Carrier Detect Disable (bit 5/10) – The LB/CD
- Idle Channel Detect Disable (bit 5/18) – Powers down the
Idle Channel Detect circuit. PLLs are disabled (bits 5/1–3 = 1).
Table 12. Control Bit Listing (By Register Number) 6 – 0 1000000 Sets the 7–bit Tx A counter for the Tx PLL. 22, 21 00 Sets CVSD Decoder minimum step size per Table 3. 6 – 0 1000000 Sets the 7–bit Rx A’ counter for the Rx PLL. 22, 21 00 Sets CVSD Encoder minimum step size per Table 3. 20 – 17 0111 Adjusts the VB reference voltage (≈1.5 V) to improve low battery detection accuracy. Total adjustment range is ≈±9%. 11 – 0 $800 Sets the 12–bit counter for the PLL Reference Clock. (24 bits total)17 – 12 100000 Sets the 6–bit counter for the Switched Capacitor Filter clock. 23 – 18 100000 Sets the 6–bit counter to set the CVSD Encoder clock rate. (24 bits total) 1 0 Power down the Tx PLL. Data Detect, and Status circuits. 5 0 Power down the CVSD Decoder. Register, and Scrambler circuits. 10 0 Power down the Low Battery/Carrier Detect Circuit. 14 – 11 0111 Sets the 4–bit counter to set the response delay for the idle channel detect circuit. 17 – 15 100 Sets the idle channel detect threshold level. See Table 4. 18 0 Power down the Idle Channel Detect Circuit. 19 0 Inverts the Data Slicer output. 20 0 Sets the Data Modem mode of operation. 22 N/A The Status Output (same as Pin 13) is read out from this bit. 23 N/A The output of the Low Battery/Carrier Detect Circuit is read from this bit.
14 MOTOROLA RF/IF DEVICE DATA
Table 12. Control Bit Listing (By Register Number) (continued) 0 0 Mutes the power amplifiers (Pins 27 to 29). (16 bits total) 1 0 Mutes the receive speech processing path (Pin 30). 2 0 Mutes the transmit speech processing path (Pin 22). 3 0 Selects the Rx 1010 Generator to the CVSD decoder. 4 0 Selects the Tx 1010 Generator to the scrambler. 5 0 Sets Carrier Detect Mode vs. Low Battery mode. audio path (Pins 32 to 30). See Table 8. 1 0 Bypass the scrambler and descrambler. 2 0 Disables the automatic idle channel detect at the CVSD encoder. Bit 5/21 is still active. 5 – 4 00 Determines the function for Pin 36 (MP1). See Table 6. 7 – 6 00 Determines the function for Pin 39 (MP2). See Table 7. 10 – 8 010 Selects one of 8 programmable taps in the scrambler and descrambler. See Table 5. 0, the code word size is 16 bits. the data word size is 16 bits. 14 0 Disables the CVSD charge compensation circuit. 17 – 15 000 Test modes for production testing only. pass filter/VCO combination. pass filter/VCO combination. 8 23 – 0 $000000 Code word for the Tx Data Register is entered into this register. 9 23 – 0 $000000 Data word for the Tx Data Register is entered into this register.
Table 13. Control Bit Listing (By Function) 1 6 – 0 1000000 Sets the 7–bit Tx A counter for the Tx PLL. 2 6 – 0 1000000 Sets the 7–bit Rx A’ counter for the Rx PLL. 4 11 – 0 $800 Sets the 12–bit counter for the PLL Reference Clock. pass filter/VCO combination. pass filter/VCO combination. 1 22, 21 00 Sets CVSD Decoder minimum step size per Table 3. 2 22, 21 00 Sets CVSD Encoder minimum step size per Table 3. 4 23 – 18 100000 Sets the 6–bit counter to set the CVSD Encoder clock rate. 6 3 0 Selects the Rx 1010 Generator to the CVSD decoder. 6 4 0 Selects the Tx 1010 Generator to the scrambler. 5 17 – 15 100 Sets the idle channel detect threshold level. See Table 4. 7 2 0 Disables the automatic idle channel detect at the CVSD encoder. Bit 5/21 is still active.
16 MOTOROLA RF/IF DEVICE DATA
Table 13. Control Bit Listing (By Function) (continued) 5 19 0 Inverts Data Slicer output. 5 20 0 Sets Data Modem mode. Data Detect register has detected a code word. 7 0 0 Bypass the Clock Recovery Block (Data slicer output goes directly to the descrambler). 7 3 0 Bypass the Data Detect block (Descrambler output goes directly to the CVSD Decoder). 0, the code word size is 16 bits. the data word size is 16 bits. 8 23 – 0 $000000 Code word for the Tx Data Register is entered into this register. 9 23 – 0 $000000 Data word for the Tx Data Register is entered into this register. 7 1 0 Bypass the scrambler and descrambler. 7 10 – 8 010 Selects one of 8 programmable taps in the scrambler and descrambler. See Table 5. 7 5 – 4 00 Determines the function for Pin 36 (MP1). See Table 6. 7 7 – 6 00 Determines the function for Pin 39 (MP2). See Table 7. 4 17 – 12 100000 Sets the 6–bit counter for the Switched Capacitor Filter clock. 6 0 0 Mutes the power amplifiers (Pins 27 to 29). 6 1 0 Mutes the receive speech processing path (Pin 30). 6 2 0 Mutes the transmit speech processing path (Pin 22). audio path (Pins 32 to 30). See Table 8. 3 20 – 17 0111 Adjusts the VB reference voltage (≈1.5 V) to improve low battery detection accuracy. Total adjustment range is ≈±9%. 5 23 N/A The output of the Low Battery/Carrier Detect Circuit is read from this bit.
5 1 0 Power down the Tx PLL. 5 2 0 Power down the Rx PLL. 5 3 0 Power down the LO2 PLL. Data Detect, and Status circuits. 5 5 0 Power down the CVSD Decoder. Register, and Scrambler circuits. 5 10 0 Power down the Low Battery/Carrier Detect Circuit. 5 18 0 Power down the Idle Channel Detection Circuit.
18 MOTOROLA RF/IF DEVICE DATA
Table 14. Register Map
6 Bit Encode Clock Counter Divide Value
13 Bit Tx N Counter Divide Value (Bits 19 – 7)
13 Bit Rx N’ Counter Divide Value (Bits 19 – 7)
6 Bit Switched Capacitor Filter Counter Divide Value
4 Bit Idle Channel Counter Delay
4 Bit Idle
11 LSB
7 Bit Tx A Counter Divide Value
7 Bit Rx A’ Counter Divide Value
12 Bit Reference Counter Divide Value
Note: Shaded areas represent output bits to be read out.
19MOTOROLA RF/IF DEVICE DATA FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP–48) ISSUE D OUTLINE DIMENSIONS ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÉÉÉ ÉÉÉ ÉÉÉ A –T– Z0.200 (0.008) AB T–U –U– Z0.200 (0.008) AC T–U B 13 24 3748 –Z– S V P AE AE DETAIL Y DETAIL Y BASE METAL N J F D ST–UM0.080 (0.003) Z SAC SECTION AE–AE –AB– –AC– AD G 0.080 (0.003) AC M /C0095 TOP & BOTTOM Q /C0095 W K X EC H 0.250 (0.010) GAUGE PLANE R DETAIL AD DIM A MIN MAX MIN MAX INCHES 7.000 BSC 0.276 BSC MILLIMETERS A1 3.500 BSC 0.138 BSC B 7.000 BSC 0.276 BSC B1 3.500 BSC 0.138 BSC C 1.400 1.600 0.055 0.063 D 0.170 0.270 0.007 0.011 E 1.350 1.450 0.053 0.057 F 0.170 0.230 0.007 0.009 G 0.500 BASIC 0.020 BASIC H 0.050 0.150 0.002 0.006 J 0.090 0.200 0.004 0.008 K 0.500 0.700 0.020 0.028 M 12 REF 12 REF N 0.090 0.160 0.004 0.006 P 0.250 BASIC 0.010 BASIC Q 1 5 1 5 R 0.150 0.250 0.006 0.010 S 9.000 BSC 0.354 BSC S1 4.500 BSC 0.177 BSC V 9.000 BSC 0.354 BSC V1 4.500 BSC 0.177 BSC W 0.200 REF 0.008 REF X 1.000 REF 0.039 REF NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER.
3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.
4 DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5 DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6 DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–.
7 DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014).
8 MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER IS OPTIONAL. /C0095/C0095 /C0095/C0095/C0095/C0095
20 MOTOROLA RF/IF DEVICE DATA
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