XBUF634AIDDAT

BUF634A_V02 TI1 | Alldatasheet

Document overview

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Technical content

Frequency (Hz) Total Harmonic Distortion + Noise (dB) -120 -110 -100 -90 -80 10 100 1k 10k D003 RL = 16 : RL = 32 : RL = 250 : Vt 1 kQ 1 kQ VO VIN Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. BUF634A SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 BUF634A36-V,210-MHz,250-mAOutput,High-SpeedBuffer

1 Features

1• Pin-selected bandwidth: 35 MHz to 210 MHz

• High output current: 250 mA
• Slew rate: 3750 V/µs
• Low quiescent current: 1.5 mA (35-MHz BW)
• Wide supply range: ±2.25 V to ±18 V
• Internal output current limit
• Thermal shutdown protection
• Available in packages with thermal pad
• Extended temperature operation: –40°C to +125°C

2 Applications

• Memory, semiconductor testers
• Test equipment
• Headphone drivers
• Flight control systems
• Capacitive load drivers
• Valve drivers, solenoid drivers
• Line drivers

3 Description

The BUF634A is a high-performance, high-fidelity, open-loop buffer capable of driving 250 mA of output current. The BUF634A is a 36-V device with bandwidth adjustable from 35 MHz to 210 MHz by varying the value of an external resistor between the V– and BW pins. The BUF634A can be used as a standalone open-loop driver, or inside the feedback loop of a precision op amp to provide both high- precision as well as large output current drive with improved capacitive load drive. For low-power applications, the BUF634A operates on a 1.5-mA quiescent current with a 250-mA output, 3750-V/µs slew rate, and 35-MHz bandwidth. The device consumes 8.5-mA quiescent current in wide- bandwidth mode with a 210-MHz bandwidth. The BUF634A is fully protected by an internal current limit in its output stage and by thermal shutdown, making the device rugged and easy to use. The BUF634A is rated to function over the extended industrial temperature range of –40°C to +125°C. The BUF634A comes in three packages: D (SOIC), DRB (VSON), and DDA (HSOIC). The DRB (VSON) and DDA (HSOIC) packages have excellent thermal performance resulting from the thermal pad on the bottom side. The DRB package comes in a very small form factor of 3.0 mm × 3.0 mm, making the device a very suitable option for portable and size-constrained applications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) BUF634A SOIC (8) 4.90 mm × 3.90 mm VSON (8)(2) 3.00 mm × 3.00 mm HSOIC (8)(2) 4.90 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview package. Boost the Output Current of Any Operational Amplifier THD+N vs Frequency Using the BUF634A With the OPA2810 (VO = 10 VPP, 90-kHz Measurement Bandwidth)

SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 www.ti.com Product Folder Links: BUF634A Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Table of Contents

7.6 Electrical Characteristics: Low-Quiescent Current

10.1 Power Dissipation and Thermal Considerations... 20

12.3 Receiving Notification of Documentation Updates 24

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2019) to Revision B Page Changes from Original (February 2019) to Revision A Page

Underside(1) BW NC VIN NC V O NC G = 1 BUF634A www.ti.com SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 Product Folder Links: BUF634A Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

5 Device Comparison Table

DEVICE VS± (V) IQ / CHANNEL (mA) BW (MHz) SLEW RATE (V/µs) VOLTAGE NOISE (nV/√Hz) AMPLIFIER DESCRIPTION BUF634A ±18 1.5 – 8.5 35 – 210 3750 3.4 Unity-gain, open-loop buffer BUF634 ±18 1.5 – 15 30 – 180 2000 4 Unity-gain, open-loop buffer LMH6321 ±18 11 110 1800 2.8 Unity-gain, open-loop buffer with adjustable current limit

6 Pin Configuration and Functions

D and DDA (Preview) Packages 8-Pin SOIC, 8-Pin HSOIC With Thermal Pad Top View 8-Pin VSON With Thermal Pad Top View (1) I = input, O = output, P = power. (2) The DRB and DDA packages include a thermal pad on the backside of the device. The thermal pad must be connected to the same potential as V–. Connect the thermal pad and V– to a heat-spreading plane to achieve low thermal impedance. The thermal pad can also be unused (not connected to any heat-spreading plane or voltage), thus giving an overall higher thermal impedance. Pin Functions PIN I/O(1) DESCRIPTION NAME DDA(2) DRB(2) D BW 1 1 1 I Bandwidth adjust pin. Connect the BW pin to the V– pin for wide-BW mode and leave the BW pin floating for low-IQ mode. See the Adjustable Bandwidth section. NC 2, 5, 8 2, 5, 8 2, 5, 8 — No internal connection V– 4 4 4 P Negative power supply V+ 7 7 7 P Positive power supply VIN 3 3 3 I Input VO 6 6 6 O Output Thermal Pad — — Thermal pad. Must be electrically shorted to V–.

SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 www.ti.com Product Folder Links: BUF634A Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VS = (V+) – (V–) Supply voltage 40 (±20) V VIN Input voltage Vs ± 0.5 V Output short-circuit (to ground) Continuous TA Operating ambient temperature –40 125 °C TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) Limited by RΘJA and TJ,Max for safe operation. See the Output Current section.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VS = (V+) – (V–) Supply voltage ±2.25 ±15 ±18 V TA Ambient temperature –40 25 125(1) °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) BUF634A UNITD (SOIC) DRB (VSON) DDA (HSOIC)

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 122.9 50.5 41.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 55.2 60 57.1 °C/W RθJB Junction-to-board thermal resistance 68.4 23.6 17.0 °C/W ΨJT Junction-to-top characterization parameter 12.1 1.5 4.6 °C/W ΨJB Junction-to-board characterization parameter 67.2 23.6 17.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance NA 6.9 5.3 °C/W

www.ti.com SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 Product Folder Links: BUF634A Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated (1) Based on electrical characterization over temperature of 35 devices.

7.5 Electrical Characteristics: Wide-Bandwidth Mode

at TA = 25°C, VS = ±15 V, BW pin connected to V–, and RL = 100 Ω connected to mid-supply (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW Bandwidth, –3 dB RL = 1 kΩ 210 MHz RL = 100 Ω 200 Bandwidth for 0.1-dB flatness VO = 10 mVPP, RL = 100 Ω, RS = 50 Ω 50 MHz SR Slew rate VO = 20-V step, VIN-SR = 4000 V/µs 3750 V/µs Rise and fall time VO = 200-mV step 1.3 ns Settling time to 0.1% VO = 20-V step, VIN-SR = 2500 V/µs 90 ns Settling time to 1% VO = 20-V step, VIN-SR = 2500 V/µs 20 ns en Voltage noise f = 1 kHz 3.4 nV/√Hz in Current noise f = 100 kHz 0.85 pA/√Hz HD2 2nd-harmonic distortion VO = 2 VPP, f = 20 kHz –77 dBc VO = 10 VPP, f = 20 kHz –69 HD3 3rd-harmonic distortion VO = 2 VPP, f = 20 kHz –77 dBc VO = 10 VPP, f = 20 kHz –56 DC PERFORMANCE VOS Input offset voltage TA = 25℃ (see Figure 26) 36 65 mV Input offset voltage drift(1) TA = –40℃ to 125℃ (see Figure 28) 175 µV/℃ IB Input bias current VIN = 0 V 0.25 2 µA G Gain VO = ±10 V, RL = 1 kΩ 0.95 0.99 V/VVO = ±10 V, RL = 100 Ω 0.93 0.95 VO = ±10 V, RL = 67 Ω 0.91 0.93 INPUT Linear input voltage range RL = 1 kΩ, IB < 10 µA –13 13 V ZIN Input impedance RL = 100 Ω 180 || 5 MΩ || pF OUTPUT Output headroom to supplies IO = ±10 mA 1.6 1.8 VIO = ±100 mA 2.0 2.2 IO = ±150 mA 2.2 2.5 IO Current output, continuous ±250 mA ISC Short-circuit current ±375 ±550 mA ZO Output impedance DC, IO = 10 mA 5 Ω POWER SUPPLY VS Operating voltage range ±2.25 ±18 V IQ Quiescent current IO = 0 mA 8.5 12 mA PSRR Power-supply rejection ratio VS = ±2.25 V to ±18 V 64 75 dB THERMAL SHUTDOWN Thermal shutdown temperature 180 ℃

SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 www.ti.com Product Folder Links: BUF634A Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) Based on electrical characterization over temperature of 35 devices.

7.6 Electrical Characteristics: Low-Quiescent Current Mode

at TA = 25°C, VS = ±15 V, BW pin left open, and RL = 100 Ω connected to mid-supply (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW Bandwidth, –3 dB RL = 1 kΩ 35 MHz RL = 100 Ω 31 Bandwidth for 0.1-dB flatness VO = 10 mVPP, RL = 100 Ω, RS = 50 Ω 2.3 MHz SR Slew rate VO = 20-V step, VIN-SR = 4000 V/µs 3750 V/µs Rise and fall time VO = 200-mV step 4 ns Settling time to 0.1% VO = 20-V step, VIN-SR = 2500 V/µs 400 ns Settling time to 1% VO = 20-V step, VIN-SR = 2500 V/µs 90 ns en Voltage noise f = 1 kHz 8.1 nV/√Hz in Current noise f = 10 kHz 0.3 pA/√Hz HD2 2nd-harmonic distortion VO = 2 VPP, f = 20 kHz –54 dBc VO = 10 VPP, f = 20 kHz –65 HD3 3rd-harmonic distortion VO = 2 VPP, f = 20 kHz –40 dBc VO = 10 VPP, f = 20 kHz –44 DC PERFORMANCE VOS Input offset voltage TA = 25℃ (see Figure 26) 36 65 mV Input offset voltage drift(1) TA = –40℃ to 125℃ (see Figure 28) 175 µV/℃ IB Input bias current VIN = 0 V 0.03 0.25 µA G Gain VO = ±10 V, RL = 1 kΩ 0.95 0.99 V/VVO = ±10 V, RL = 100 Ω 0.93 0.95 VO = ±10 V, RL = 67 Ω 0.91 0.93 INPUT Linear input voltage range RL = 1 kΩ, IB < 10 µA –13 13 V ZIN Input impedance RL = 100 Ω 1400 || 5 MΩ || pF OUTPUT Output headroom to supplies IO = ±10 mA 1.6 1.8 VIO = ±100 mA 2.0 2.2 IO = ±150 mA 2.2 2.5 IO Current output, continuous ±250 mA ISC Short-circuit current ±350 ±550 mA ZO Output impedance DC, IO = 10 mA 7 Ω POWER SUPPLY VS Operating voltage range ±2.25 ±18 V IQ Quiescent current IO = 0 1.5 2.3 mA PSRR Power-supply rejection ratio VS = ±2.25 V to ±18 V 64 80 dB THERMAL SHUTDOWN Thermal shutdown temperature 180 ℃

7.7 Typical Characteristics

Figure 1. Gain and Phase vs Frequency and Figure 2. Gain and Phase vs Frequency and Temperature Figure 3. Gain and Phase vs Frequency and Figure 4. Gain and Phase vs Frequency and Figure 5. Gain and Phase vs Frequency and Figure 6. Gain and Phase vs Frequency and

1.2 k BW VIN VO Thermal Shutdown (1) BUF634A www.ti.com SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 Product Folder Links: BUF634A Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The BUF634A is a high-speed, unity-gain, open-loop buffer that can be used in a wide range of applications requiring large output current drive or large slew rates. The BUF634A can operate on power supplies ranging from 4.5 V to 36 V and includes an internal output current limiting feature as well as thermal shutdown, thereby making the device rugged and easy to use. The bandwidth of the BUF634A can be adjusted by connecting a resistor between the V– and BW pins. Its power scaling with bandwidth makes the device suitable for use in portable battery-powered applications. See the Adjustable Bandwidth section for a description of the relationship between bandwidth adjustment resistance and the device –3-dB bandwidth. The BUF634A can be used in a composite loop (inside the feedback loop of op amps) to increase output current, eliminate thermal feedback, and improve capacitive load drive. See Figure 44 for this circuit. Decoupling the high-power output current stage from the precision amplifier gives high precision performance by eliminating thermal effects on input offset of the composite circuit. With a large slew rate of 3750 V/µs, the BUF634A can quickly reproduce its input signal at its output without adding considerable delay when used in a composite loop. When used in a composite loop, the outer amplifier controls the circuit precision and distortion performance and the buffer augments the circuit output current drive capability. See the Functional Block Diagram section for a simplified circuit diagram of the open-loop complementary follower design of the BUF634A.

8.2 Functional Block Diagram

NOTE: Stage currents are set by I1.

8.3 Feature Description

8.3.1 Output Current

voltage and large output current to avoid permanent damage to the device.

8.3.2 Thermal Shutdown

protection is activated, the output stage is disabled and the output current is limited, allowing the device to cool. type, signal, load, and thermal environment. power dissipation for the package type.

8.3.3 ESD Protection

As shown in Figure 36, all device pins are protected with internal ESD protection diodes to the power supplies. flowing through the ESD diode. Restrict any current flowing through the ESD diodes to less than 10 mA. Figure 36. Internal ESD Protection

8.4 Device Functional Modes

8.4.1 Adjustable Bandwidth

from 1.5 mA (typ) to 8.5 mA (typ) with variation in bandwidth from 35 MHz to 210 MHz, respectively. Figure 37. Small-Signal Bandwidth versus Bandwidth Adjustment Resistance

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

the input bias current polarity. Figure 38. Buffer Connections

9.1.1 High-Frequency Applications

an isolation resistor at the output of the BUF634A for adequate phase margin and stability.

Figure 43. Bridge-Connected Motor Driver

9.2 Typical Application

corrected by the open-loop gain and feedback of the op amp. NOTE: C1 is not required for most common op amps. Use C1 with unity-gain stable, high-speed op amps. Figure 44. Boosting Op Amp Output Current

9.2.1 Design Requirements

• Boost the output current of an OPA2810
• Operate from ±12-V power supplies
• Operate from –40°C to +125°C
• Gain = 2 V/V
• Output current = ±250 mA
• Bandwidth greater than 100 kHz

9.2.2 Detailed Design Procedure

various operating conditions that can affect the stability of the op amp.

9.2.3 Application Curves

Figure 45. THD+N vs Output Voltage Using the BUF634A Figure 46. THD+N vs Frequency Using the BUF634A With

SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 www.ti.com Product Folder Links: BUF634A Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

10 Power Supply Recommendations

The BUF634A is intended for operation on supplies ranging from 4.5 V to 36 V (±2.25 V to ±18 V). At low power- supply conditions, such as ±2.25 V, the output swing may be limited. See the output voltage range specifications in the Electrical Characteristics tables for additional information. The BUF634A can be operated on single-sided supplies, split, and balanced bipolar supplies or unbalanced bipolar supplies. Operating from a single supply can have numerous advantages. With the negative supply at ground, the DC errors resulting from the –PSRR term can be minimized. Minimize the distance (< 0.1") from the power-supply pins to high-frequency, 0.1-µF decoupling capacitors. A larger capacitor (10 µF typical) is used along with a high-frequency, 0.1-µF supply- decoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these capacitors. When a split-supply is used, use these capacitors from each supply to ground. If necessary, place the larger capacitors further from the device and share these capacitors among several devices in the same area of the PCB.

10.1 Power Dissipation and Thermal Considerations

The BUF634A includes automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if the junction temperature exceeds approximately 180°C. When the junction temperature decreases to approximately 160°C, the buffer turns on again. The package and the PCB dictate the thermal characteristics of the device. Maximum power dissipation for a particular package is calculated using the following formula. where

• PDmax is the maximum power dissipation in the amplifier (W).
• Tmax is the absolute maximum junction temperature (°C).
• TA is the ambient temperature (°C).
• θJA = θJC + θCA
• θJC is the thermal coefficient from the silicon junctions to the case (°C/W).
• θCA is the thermal coefficient from the case to ambient air (°C/W). (1) The thermal coefficient for the thermal pad integrated circuit packages are substantially improved over the traditional SOIC package. The data for the thermal pad packages assume a board layout that follows the thermal pad package layout guidelines referenced above and detailed in the PowerPAD™ Thermally Enhanced Package application report. If the thermal package integrated circuit package is not soldered to the PCB, the thermal impedance increases substantially and may cause serious heat and performance issues. When determining whether or not the device satisfies the maximum power dissipation requirement, make sure to consider not only quiescent power dissipation, but dynamic power dissipation. Often times, this dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation provides visibility into a possible problem.

www.ti.com SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 Product Folder Links: BUF634A Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

11.1.1 SOIC Layout Guidelines (D Package Without a Thermal Pad)

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible, as illustrated in Figure 48.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. The SOIC-8 surface-mount package is excellent for applications requiring high output current with low average power dissipation. To achieve the best possible thermal performance with the SOIC-8 package, solder the device directly to a circuit board. Sockets degrade thermal performance because much of the heat is dissipated by conduction through the package pins. Use wide circuit board traces on all device pins, including pins that are not connected. For more information on designing the circuit board, see the BUF634AD Evaluation module user's guide.

11.1.2 HSOIC Layout Guidelines (DDA Package With a Thermal Pad)

Figure 47 shows the DDA package top-side etch and via pattern. Figure 47. DDA Thermal Pad Integrated Circuit Package PCB Etch and Via Pattern

1. Use an etch for the leads and the thermal pad.

small so that solder wicking through the vias is not a problem during reflow.

1. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area, and help

mm) diameter vias directly under the thermal pad because they are not in the area that requires soldering. As a result, wicking is not a problem.

1. The thermal pad is internally connected with V–. Therefore, always short the thermal pad to the same

potential as V– externally as well.

1. Connect all vias used under the thermal pad to remove heat to the V– plane.
2. When connecting these vias to the V– plane, do not use the typical web or spoke connection methodology.

Web and spoke connections have a high thermal resistance that slows the heat transfer during soldering. complete connection around the entire circumference of the plated-through hole.

1. The top-side solder mask must leave the pins of the package and the thermal pad area with the 13 vias
2. Apply solder paste to the exposed thermal pad area and all of the device pins.
3. With these preparatory steps in place, the device is placed in position and run through the solder reflow

operation as any standard surface-mount component.

11.2 Layout Example

Figure 48. BUF634A Layout Example (SOIC)

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macromodels in addition to a range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™ ) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder.

12.1.1.2 TI Precision Designs

The BUF634A is featured in several TI Precision Designs, available online at www.ti.com. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, OPA2810 Dual-channel, 27-V, rail-to-rail input/output FET-Input operational amplifier data sheet
• Texas Instruments, BUF634AD Evaluation module user's guide
• Texas Instruments, Combining an amplifier with the BUF634 application note
• Texas Instruments, Add current limit to the BUF634 application note
• Texas Instruments, Power amplifier stress and power handling limitations application note
• Texas Instruments, Shelf-life evaluation of lead-free component finishes application report

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

TINA-TI, TINA, E2E are trademarks of Texas Instruments. DesignSoft is a trademark of DesignSoft, Inc. All other trademarks are the property of their respective owners.

www.ti.com SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 Product Folder Links: BUF634A Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C 8X 0.37 0.25 1.75 0.1 1.95 1.5 0.1 6X 0.65

1 MAX

8X 0.5 0.3 0.05 0.00 (0.65) A 3.1 2.9 B 3.1 2.9 (DIM A) TYP 4X (0.23) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000 BUF634A SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 www.ti.com Product Folder Links: BUF634A Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.31) (1.75) (2.8) 6X (0.65) (1.5) ( 0.2) VIA TYP (0.5) (0.625) 8X (0.6) (R0.05) TYP (0.825) (0.23) (0.65) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 SYMM EXPOSED METAL SHOWN LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL BUF634A www.ti.com SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 Product Folder Links: BUF634A Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.31) 8X (0.6) (1.34) (1.55) (2.8) 6X (0.65) (0.725) 4X (0.23) (2.674) (0.65) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 4 5 METAL TYP SYMM BUF634A SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 www.ti.com Product Folder Links: BUF634A Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.7 MAX

6X 1.27 8X 0.51 0.31 3.81 TYP0.25 0.10 0 - 8 0.15 0.00 2.6 2.0 3.1 2.5 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 5.0 4.8 B 4.0 3.8 4221637/B 03/2016 PowerPAD SOIC - 1.7 mm max heightDDA0008J PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MS-012, variation BA. PowerPAD is a trademark of Texas Instruments. TM

0.1 C A B

0.1 C SEE DETAIL A TYPICAL DETAIL A SCALE 2.400 EXPOSED THERMAL PAD BUF634A www.ti.com SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 Product Folder Links: BUF634A Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT (5.4) 8X (1.55) 8X (0.6) 6X (1.27) (2.95) NOTE 9 (4.9) NOTE 9 (2.6) (3.1) SOLDER MASK OPENING ( ) TYP VIA 0.2 (1.3) TYP (1.3) TYP 4221637/B 03/2016 SYMM PowerPAD SOIC - 1.7 mm max heightDDA0008J PLASTIC SMALL OUTLINE SYMM SEE DETAILS SCALE:10X LAND PATTERN EXAMPLE 4 5 SOLDER MASK OPENING METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. TM METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED BUF634A SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 www.ti.com Product Folder Links: BUF634A Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.55) 8X (0.6) 6X (1.27) (5.4) (2.6) (3.1) BASED ON

0.127 THICK

PowerPAD SOIC - 1.7 mm max heightDDA0008J PLASTIC SMALL OUTLINE 2.20 X 2.620.175 2.37 X 2.830.150 2.6 X 3.1 (SHOWN)0.125 2.91 X 3.470.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X SYMM SYMM 4 5 BASED ON

0.125 THICK

METAL COVERED SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES BUF634A www.ti.com SBOS948B –FEBRUARY 2019–REVISED JANUARY 2020 Product Folder Links: BUF634A Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

www.ti.com 21-Apr-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples BUF634AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 BF634A BUF634AIDRBT PREVIEW SON DRB 8 250 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 125 B634A XBUF634AIDDAT ACTIVE SO PowerPAD DDA 8 2500 TBD Call TI Call TI -40 to 125 XBUF634AIDRBT ACTIVE SON DRB 8 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 21-Apr-2020 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Dec-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BUF634AIDR SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Dec-2019 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 8X 0.37 0.25 1.75 0.1 1.95 1.5 0.1 6X 0.65 8X 0.5 0.3 0.05 0.00 (0.65) A 3.1 2.9 B 3.1 2.9 (DIM A) TYP 4X (0.23) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT 8X (0.31) (1.75) (2.8) 6X (0.65) (1.5) ( 0.2) VIA TYP (0.5) (0.625) 8X (0.6) (R0.05) TYP (0.825) (0.23) (0.65) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.31) 8X (0.6) (1.34) (1.55) (2.8) 6X (0.65) (0.725) 4X (0.23) (2.674) (0.65) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 4 5 METAL TYP SYMM

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE 4202561/G

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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