X9C303V8IZ

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

• Solid-state potentiometer
• Three-wire serial interface
• 100 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up
• 99 resistive elements, log taper - Temperature compensated - End-to-end resistance, 32k ±15% - Terminal voltages, ±5V
• Low power CMOS -V CC = 5V - Active current, 3mA max. - Standby current, 750µA max.
• High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years
• Packages - 8 Ld TSSOP - 8 Ld SOIC - 8 Ld PDIP
• Pb-free available (RoHS compliant) Block Diagram 7-BIT UP/DOWN COUNTER 7-BIT NONVOLATILE MEMORY STORE AND RECALL CONTROL CIRCUITRY ONE OF HUNDRED DECODER RESISTOR ARRAY RL/VL RW/VW RH/VH U/D INC CS TRANSFER VCC ONE- GATES 0VSS

FN8223 Rev 2.00 Page 2 of 10 January 30, 2009 Pin Descriptions VH and VL The high (VH) and low (VL) terminals of the device are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is –5V and the maximum is +5V. It should be noted that the terminology of VL and VH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. VW VW is the wiper terminal, equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete, the device will be placed in the low power standby mode until the device is selected once again. Pinouts X9C303 (8 LD SOIC, 8 LD PDIP) TOP VIEW X9C303 (8 LD TSSOP) TOP VIEW

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # X9C303P X9C303P 0 to +70 8 Ld PDIP MDP0031 X9C303PI X9C303P I -40 to +85 8 Ld PDIP MDP0031 X9C303PIZ (Notes 1, 2) X9C303P ZI -40 to +85 8 Ld PDIP (300 mil) ( Pb-free) MDP0031 X9C303PZ (Notes 1, 2) X9C303P Z 0 to +70 8 Ld PDIP (300 mil) (Pb-f ree) MDP0031 X9C303S8* , ** X9C303S 0 to +70 8 Ld SOIC (150 mil) MDP0027 X9C303S8I* X9C303S I -40 to +85 8 Ld SOIC (150 mil) MDP0027 X9C303S8IZ* (Note 1) X9C303S ZI -40 to +85 8 Ld SOIC (150 mil) (Pb -free) MDP0027 X9C303S8Z* (Note 1) X9C303S Z 0 to +70 8 Ld SOIC (150 mil) (Pb-fre e) MDP0027 X9C303V8*, ** 9C303 0 to +70 8 Ld TSSOP (4.4mm) M8.173 X9C303V8I* C303 I -40 to +85 8 Ld TSSOP (4.4mm) M8.173 X9C303V8IZ* (Note 1) C303 IZ -40 to +85 8 Ld TSSOP (4.4mm) (Pb-fre e) M8.173 X9C303V8Z* (Note 1) 9C303 Z 0 to +70 8 Ld TSSOP (4.4mm) (Pb-free) M 8.173 X9C303S8I-2.7 X9C303S G -40 to +85 8 Ld SOIC (150 mil) MDP0027 X9C303S8IZ-2.7 (Note 1) X9C303S ZG -40 to +85 8 Ld SOIC (150 mil) (Pb-free) MDP0027 *Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. **Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. VCC CS VL VW INC U/D VH VSS X9C303 X9C303 CS VCC INC U/D VL VW VSS VH

FN8223 Rev 2.00 Page 3 of 10 January 30, 2009 Potentiometer Relationships Principles of Operation There are three sections of the X9C303: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions, the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for t IW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last counter position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is reset to the value last stored. Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW, the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven-bit counter. The output of this counter is decoded to select one of one-hundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9C303, move the wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. The wiper movement is performed as previously described ; once the new position is reached, the system would the keep INC LOW while taking CS HIGH. The new wiper position would be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This would allow the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference: system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. Pin Names SYMBOL DESCRIPTION VH High Terminal (Potentiometer) VW Wiper Terminal (Potentiometer) VL Low Terminal (Potentiometer) VSS Ground VCC Supply Voltage U/D Up/Down Control Input INC Increment Control Input CS Chip Select Control Input NC No Connection VL VH (VS) R99 R98 S100 S99 S98 VW Gi 20Log R1 R2 . . . R i+++ RTOTAL VW VS R1 R2 . . . R 99+++ R TOTAL= (REFER TEST CIRCUIT 1) Mode Selection CS INC U/D MODE L H Wiper Up L L Wiper Down H X Store Wiper Position H X X Standby Current L X No Store, Return to Standby L H Wiper Up (not recommended) L L Wiper Down (not recommended)

FN8223 Rev 2.00 Page 4 of 10 January 30, 2009 Symbol Table Typical Electrical Taper WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 100 % TOTAL RESISTANCE TAP R(VH - VW) R(VW - VL) Test Circuit #1 TEST POINT VW VH VL VS Test Circuit #2 FORCE VL VW VH TEST POINT CURRENT Circuit #3 SPICE Macro Model CW RTOTAL RH RL CH RW 10pF CL 10pF 25pF

FN8223 Rev 2.00 Page 5 of 10 January 30, 2009 Absolute Maximum Ratings Thermal Information Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Recommended Operating Conditions Physical Characteristics Marking Includes Manufacturer’s Trademark Resistance Value or Code Date Code CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications Over recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP (Note 3) MAX RTOTAL End-to-End Resistance 32  End-to-End Resistance Tolerance -15 +15 % VH VH Terminal Voltage -5 +5 V VL VL Terminal Voltage -5 +5 V RW Wiper Resistance Max Wi per Current ±1mA 40 100  Tap Position Relative Step Size Error Error = log (Vw(n)) - log (Vw(n - 1)) for tap n = 2 - 99, VH-VL = 10V 0.005 0.115 dB Resistor Noise At 1kHz 23 nV(RMS)/ Hz Charge Pump Noise At 850kHz 20 mV(RMS) End-to-End Resistance Temperature Coefficient T = -40°C to +85°C ±400 ppm/°C Ratiometric Temperature Coefficient Tap position 84 ±20 ppm/°C CH/CL/CW (Note 5) Potentiometer Capacitance See “C ircuit #3 SPICE Macro Model” on page 4 10/10/25 pF

FN8223 Rev 2.00 Page 6 of 10 January 30, 2009 limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP (Note 3) MAX ICC Vcc Active Current CS = VIL, U/D = VIL or VIH and INC = 0.4V to 2.4V @ Max tCYC 13 m A ISB Standby Supply Current CS = VCC - 0.3V, U/D and INC =V SS or VCC - 0.3V 200 750 µA ILI CS, INC, U/D Input Leakage Current V IN = VSS to VCC -10 +10 µA VIH CS, INC, U/D Input HIGH Voltage 2 V VIL CS, INC, U/D Input LOW voltage 0.8 V CIN (Note 5) CS , INC, U/D Input Capacitance V CC = 5V, VIN = VSS, TA = +25°C, f = 1MHz 10 pF EEPROM SPECS EEPROM Endurance Wiper storage operations over recommended operation conditions 100,000 Cycles EEPROM Retention At +55°C 100 Years NOTES: 3. Typical values are for TA = +25°C and nominal supply voltage. Standard Parts PART NUMBER MAXIMUM RESISTANCE WIPER INCREMENTS MINIMUM RESISTANCE X9C303 32k  Log Taper 40  Typical AC Conditions of Test Input Pulse Levels 0V to 3V Input Rise and Fall Times 10ns Input Reference Levels 1.5V limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL PARAMETER LIMITS UNITMIN TYP (Note 4) MAX tCl CS to INC Set-up 100 ns tlD INC HIGH to U/D Change 100 ns tDI U/D to INC Set-up 2.9 µs tlL INC LOW Period 1 µs tlH INC HIGH Period 1 µs tlC INC Inactive to CS Inactive 1 µs tCPH CS Deselect Time 20 ms tIW (Note 5) INC to VW Change 100 µs tCYC INC Cycle Time 2 µs

FN8223 Rev 2.00 Page 7 of 10 January 30, 2009 AC Timing Diagram NOTES: 4. Typical values are for TA = +25°C and nominal supply voltage. 5. This parameter is not 100% tested. 6. MI in the “AC Timing Diagram” refers to the minimum incremental change in the VW output due to a change in the wiper position. tR, tF (Note 5) INC Input Rise and Fall Time 500 ns tPU (Note 5) Power-up to Wiper Stable 500 µs tR VCC (Note 5) V CC Power-up Rate 0.2 50 mV/µs limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL PARAMETER LIMITS UNITMIN TYP (Note 4) MAX CS INC U/D VW tCI tIL tIH tCYC tID tDI tIW MI tIC tCPH tF tR 10% 90% 90% (NOTE 6)

FN8223 Rev 2.00 Page 8 of 10 January 30, 2009 Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M8.173

8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N8 8 7  0o 8o 0o 8o - Rev. 1 12/00

FN8223 Rev 2.00 Page 9 of 10 January 30, 2009 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C

0.010 BM CA

B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL INCHES TOLERANCE NOTESSO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994

FN8223 Rev 2.00 Page 10 of 10 January 30, 2009 X9C303 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2009. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Plastic Dual-In-Line Packages (PDIP) MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL INCHES TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20 N 8 14 16 18 20 Reference Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1

12 N / 2

E eB eA c