X98027 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 29
Technical content
Features
- 275MSPS maximum conversion rate
- Low PLL clock jitter (250ps p-p @ 275MSPS)
- 64 interpixel sampling positions
- 0.35V p-p to 1.4Vp-p video input range
- Programmable bandwidth (100MHz to 780MHz)
- 2 channel input multiplexer
- RGB and YUV 4:2:2 output formats
- 5 embedded voltage regulators allow operation from single 3.3V supply and enhance performance, isolation
- Completely independent 8 bit gain/10 bit offset control
- CSYNC and SOG support
- Trilevel sync detection
- 1.2W typical P D @ 275MSPS
- Pb-free plus anneal available (RoHS compliant)
Applications
- LCD Monitors and Projectors
- Digital TVs
- Plasma Display Panels
- RGB Graphics Processing
- Scan Converters Simplified Block Diagram RGB/YPbPrIN 1 PGA 8 bit ADC Offset DAC ABLC™ 8 or 16 SOGIN 1/2 HSYNCIN 1/2 VSYNCIN 1/2 Sync Processing Digital PLL Voltage Clamp RGB/YPbPrIN 2
3 RGB/YUVOUT
AFE Configuration and Control VSYNCOUT Data Sheet May 26, 2005
2 FN8221.0 May 26, 2005 Block Diagram
Ordering Information
(°C) PACKAGE PART MARKING X98027L128-3.3 275MHz 0 to 70 128 MQFP X98027L-3.3 X98027L128-3.3-Z (See Note) 275MHz 0 to 70 128 MQFP (Pb-free) X98027L-3.3Z NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. GIN1 RGBGND1 GIN2 RGBGND2 VIN+ VIN- PGA 8 bit ADC+ VCLAMP RIN1 RIN2 VIN+ VIN- PGA 8 bit ADC+ VCLAMP BIN1 BIN2 VIN+ VIN- PGA 8 bit ADC+ VCLAMP Offset DAC Offset DAC Offset DAC ABLC™ ABLC™ ABLC™
8 BS[7:0]
8 BP[7:0]
8 GS[7:0]
8 GP[7:0]
8 RS[7:0]
8 RP[7:0]
3 FN8221.0 May 26, 2005 T Absolute Maximum Ratings Recommended Operating Conditions Voltage on VA, VD, or VX Voltage on any analog input pin Voltage on any digital input pin CAUTION: Stresses above those listed under “Absolute Maximum Rati ngs” may cause permanent damage to the device. This is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, pixel rate = 275MHz, fXTAL = 25MHz, TA = 25°C, unless otherwise noted SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT FULL CHANNEL CHARACTERISTICS ADC Resolution 8B i t s Missing Codes Guaranteed monotonic None Conversion Rate Per Channel 10 275 MHz DNL Differential Non-Linearity ±0.7 +1.2 -0.9 LSB INL Integral Non-Linearity ±1.6 ±3.75 LSB Gain Adjustment Range ±6 dB Gain Adjustment Resolution 8B i t s Gain Matching Between Channels Percent of full scale ±1 % Full Channel Offset Error, ABLC™ enabled ADC L SBs, over time and temperature ±0.125 ±0.5 LSB Offset Adjustment Range, ABLC™ enabled or disabled ADC LSBs (see ABLC™ applications information section) ±127 LSB Overvoltage Recovery Time For 150% overrange, maximum bandwidth setting 5n s ANALOG VIDEO INPUT CHARACTERISTICS (R IN1, GIN1, BIN1, RIN2, GIN2, BIN2) Input Range 0.35 0.7 1.4 V P-P Input Bias Current DC restore clamp off ±0.01 ±1 µA Input Capacitance 5p F Full Power Bandwidth Programmable 780 MHz INPUT CHARACTERISTICS (SOGIN1, SOGIN2) VIH/VIL Input Threshold Voltage Programmable - See Register Listing for Details 0 to -0.3 V Hysteresis Centered around threshold voltage 40 mV Input capacitance 5p F INPUT CHARACTERISTICS (HSYNCIN1, HSYNCIN2) VIH/VIL Input Threshold Voltage Programmable - See Register Listing for Details 0.4 to 3.2 V Hysteresis Centered around threshold voltage 240 mV RIN Input impedance 1.2 k Ω Input capacitance 5p F X98027
4 FN8221.0 May 26, 2005 DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINVIN, RESET) VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage 0.8 V I Input leakage current RESET has a 70kΩ pullup to VD ±10 nA Input capacitance 5p F SCHMITT DIGITAL INPUT CHARACTERISTICS (SCL, VSYNCIN1, VSYNCIN2) VT+ Low to High Threshold Voltage 1.45 V VT- High to Low Threshold Voltage 0.95 V I Input leakage current ±10 nA Input capacitance 5p F DIGITAL OUTPUT CHARACTERISTICS (DATACLK, DATACLK) VOH Output HIGH Voltage, IO = 16mA 2.4 V VOL Output LOW Voltage, IO = -16mA 0.4 V DIGITAL OUTPUT CHARACTERISTICS (RP, GP, BP, RS, GS, BS, HSOUT, VSOUT, HSYNCOUT, VSYNCOUT) VOH Output HIGH Voltage, IO = 8mA 2.4 V VOL Output LOW Voltage, IO = -8mA 0.4 V RTRI Pulldown to GNDD when three-state R P, GP, BP, RS, GS, BS only 58 k Ω DIGITAL OUTPUT CHARACTERISTICS (SDA, XTALCLKOUT) VOH Output HIGH Voltage, IO = 4mA XTALCLK OUT only; SDA is open-drain 2.4 V VOL Output LOW Voltage, IO = -4mA 0.4 V POWER SUPPLY REQUIREMENTS VA Analog Supply Voltage 3 3.3 3.6 V VD Digital Supply Voltage 3 3.3 3.6 V VX Crystal Oscillator Supply Voltage 3 3.3 3.6 V IA Analog Supply Current Operating 190 200 mA ID Digital Supply Current Operating (grayscale) 170 180 mA IX Crystal Oscillator Supply Current 0.7 2 mA PD Total Power Dissipation Operating (average) 1.2 1.4 W Power-down Mode 50 80 mW ΘJA Thermal Resistance, Junction to Ambient 30 °C/W AC TIMING CHARACTERISTICS PLL Jitter 250 450 ps p-p Sampling Phase Steps 5.6° per step 64 Sampling Phase Tempco ±1 ps/°C Sampling Phase Differential Nonlinearity Degrees out of 360° ±3 ° HSYNC Frequency Range 10 150 kHz fXTAL Crystal Frequency Range 23 (Note 2) 25 27 MHz tSETUP DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load (Note 1) 1.3 ns Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, pixel rate = 275MHz, fXTAL = 25MHz, TA = 25°C, unless otherwise noted (Continued) SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT X98027
2 XTAL periods min 80 ns
- Setup and hold times are at a 140MHz DATACLK rate.
FIGURE 1. 2 WIRE INTERFACE TIMING FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
8.5 DATACLK Pipeline Latency
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. FIGURE 3. 24 BIT OUTPUT MODE The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. FIGURE 4. 24 BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
8 FN8221.0 May 26, 2005 Pinout X98027 (128-PIN MQFP) TOP VIEW NC NC GND A VBYPASS GND A VA R IN1 GND A VBYPASS GND A VA G IN1 RGB GND 1 SOG IN1 GND A VBYPASS GND A VA B IN1 VA GND A R IN2 GND A G IN2 RGB GND 2 SOG IN2 GND A B IN2 VA GND A VCOREADC GND D HSYNC IN1 HSYNC IN2 VA GND A GND X VX R S 5 R S 6 R S 7 VD GND D G P 0 G P 1 G P 2 G P 3 G P 4 G P 5 G P 6 G P 7 VD GND D G S 0 G S 1 G S 2 G S 3 G S 4 G S 5 G S 6 G S 7 VCORE GND D VD GND D B P 0 B P 1 B P 2 B P 3 B P 4 B P 5 B P 6 B P 7 VD GND D VREG IN 102 101 100 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 VSYNC OUT HSYNC OUT VS OUT HS OUT VD GND D DATACLK DATACLK GND D R P 0 R P 1 R P 2 R P 3 R P 4 R P 5 R P 6 R P 7 VD GND D VCORE GND D R S 0 R S 1 R S 2 R S 3 R S 4 XTAL IN XTAL OUT CLOCKINV IN VPLL GND D VSYNC IN1 VSYNC IN2 RESET XTALCLOCK OUT S ADDR SD A SCL GND D VCORE GND D VD B S 7 B S 6 B S 5 B S 4 B S 3 B S 2 B S 1 B S 0 NC VREG OUT X98027
9 FN8221.0 May 26, 2005 Pin Descriptions SYMBOL PIN DESCRIPTION RIN1 7 Analog input. Red channel 1. DC couple or AC couple through 0.1µF. GIN1 12 Analog input. Green channel 1. DC couple or AC couple through 0.1µF. BIN1 19 Analog input. Blue channel 1. DC couple or AC couple through 0.1µF. RGBGND1 13 Analog input. Ground reference for the R, G, and B i nputs of channel 1 in the DC coupled configuration. Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the AC-coupled configuration, but the pin should still be tied to GNDA. SOGIN1 14 Analog input. Sync on Green. Connect to G IN1 through a 0.01µF capacitor in series with a 500Ω resistor. HSYNCIN1 33 Digital input, 5V tolerant, 240mV hysteresis, 1.2k Ω impedance to GNDA. Connect to channel 1's HSYNC signal through a 680Ω series resistor. VSYNCIN1 44 Digital input, 5V tolerant, 500mV hyst eresis. Connect to channel 1's VSYNC signal. RIN2 22 Analog input. Red channel 2. DC couple or AC couple through 0.1µF. GIN2 24 Analog input. Green channel 2. DC couple or AC couple through 0.1µF. BIN2 28 Analog input. Blue channel 2. DC couple or AC couple through 0.1µF. RGBGND2 25 Analog input. Ground reference for the R, G, and B i nputs of channel 2 in the DC coupled configuration. Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the AC-coupled configuration, but the pin should still be tied to GNDA. SOGIN2 26 Analog input. Sync on Green. Connect to G IN1 through a 0.01µF capacitor in series with a 500Ω resistor. HSYNCIN2 34 Digital input, 5V tolerant, 240mV hysteresis, 1.2k Ω impedance to GNDA. Connect to channel 2's HSYNC signal through a 680Ω series resistor. VSYNCIN2 45 Digital input, 5V tolerant, 500mV hyst eresis. Connect to channel 2's VSYNC signal. CLOCKINVIN 41 Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame rate during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to DGND if unused. RESET 46 Digital input, 5V tolerant, active low, 70k Ω pull-up to VD. Take low for at least 1µs and then high again to reset the X98027. This pin is not necessary for normal use and may be tied directly to the VD supply. XTALIN 39 Analog input. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. XTALOUT 40 Analog output. Connect to external 23MHz to 27MHz crystal and load capacitor (see crystal spec for recommended loading). Typical oscillation amplitude is 1.0VP-P centered around 0.5V. XTALCLKOUT 47 3.3V digital output. Buffered crystal clock output at f XTAL or fXTAL/2. May be used as system clock for other system components. SADDR 48 Digital input, 5V tolerant. Address = 0x4C (0x98 including R/W bit) when tied low. Address = 0x4D (0x9A including R/W bit) when tied high. SCL 50 Digital input, 5V tolerant, 500mV hysteresis . Serial data clock for 2-wire interface. SDA 49 Bidirectional Digital I/O, open drain, 5V to lerant. Serial data I/O for 2-wire interface. RP[7:0] 112-119 3.3V digital output. Red channel, primar y pixel data. 58K pulldown when three-stated. RS[7:0] 100-107 3.3V digital output. Red channel, secondary pixel data. 58K pulldown when three-stated. GP[7:0] 90-97 3.3V digital output. Green channel, primar y pixel data. 58K pulldown when three-stated. GS[7:0] 80-87 3.3V digital output. Green channel, secondary pixel data. 58K pulldown when three-stated. BP[7:0] 68-75 3.3V digital output. Blue channel, primary pixel data. 58K pulldown when three-stated. BS[7:0] 55-62 3.3V digital output. Blue channel, sec ondary pixel data. 58K pulldown when three-stated. DATACLK 121 3.3V digital output. Data clock output. Equal to pi xel clock rate in 24 bit mode, one half pixel clock rate in 48 bit mode. DATACLK 122 3.3V digital output. Inverse of DATACLK. X98027
10 FN8221.0 May 26, 2005 HSOUT 125 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data. This output is always purely horizontal sync (without any composite sync signals) VSOUT 126 3.3V digital output.Artificial VSYNC output aligned with pixel data. VSYNC is generated 8 pixel clocks after the trailing edge of HSOUT. This signal is usually not needed - use VSYNCOUT as VSYNC source. HSYNCOUT 127 3.3V digital output. Buffered HSYNC (or SOG or CSYN C) output. This is typically used to measure HSYNC period. HSOUT should be used to detect the beginning of a line. This output will pass composite sync signals and Macrovision signals if present on HSYNCIN or SOGIN. VSYNCOUT 128 3.3V digital output. Buffered VSYNC output. For composit e sync signals, this output will be asserted for the duration of the disruption of the normal HSYNC pattern. This is typically used to detect the beginning of a frame and measure the VSYNC period. VA 6, 11, 18, 20, 29, 35 Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GNDA with 0.1µF. GNDA 3, 5, 8, 10, 15, 17, 21, 23, 27, 30, 36 Ground return for VA and VBYPASS. VD 54, 67, 77, 89, 99, 111, 124 Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GNDD with 0.1µF. GNDD 32, 43, 51, 53, 66, 76, 78, 88, 98, 108, 110, 120, 123 Ground return for VD, VCORE, VCOREADC, and VPLL. VX 38 Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND X with 0.1µF. GNDX 37 Ground return for V X. VBYPASS 4, 9, 16 Bypass these pins to GND A with 0.1µF. Do not connect these pins to each other or anything else. VREGOUT 64 Regulated output voltage for V PLL, VCOREADC and VCORE; typically 1.9V. Connect only to VPLL, VCOREADC and VCORE and bypass at input pins as instructed below. Do not connect to anything else - this output can only supply power to VPLL, VCOREADC and VCORE. VCOREADC 31 Internal power for the ADC’s digital logic. Connect to VREG OUT through a 10Ω resistor and bypass to GNDD with 0.1µF. VPLL 42 Internal power for the PLL’s digital logic. Connect to VREG OUT through a 10Ω resistor and bypass to GNDD with 0.1µF. VCORE 52, 79, 109 Internal power for core logic. Connect to VREG OUT and bypass each pin to GNDD with 0.1µF. NC 1, 2, 63 Reserved. Do not connect anything to these pins. Pin Descriptions (Continued) SYMBOL PIN DESCRIPTION X98027
11 FN8221.0 May 26, 2005 Register Listing ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME DESCRIPTION 0x01 SYNC Status (read only)
0 HSYNC1 Active 0: HSYNC1 is Inactive
1: HSYNC1 is Active
1 HSYNC2 Active 0: HSYNC2 is Inactive
1: HSYNC2 is Active
2 VSYNC1 Active 0: VSYNC1 is Inactive
1: VSYNC1 is Active
3 VSYNC2 Active 0: VSYNC2 is Inactive
1: VSYNC2 is Active
4 SOG1 Active 0: SOG1 is Inactive
1: SOG1 is Active
5 SOG2 Active 0: SOG2 is Inactive
1: SOG2 is Active
6 PLL Locked 0: PLL is unlocked
1: PLL is locked to incoming HSYNC
7 CSYNC Detected at
0: Composite Sync signal not detected 1: Composite Sync signal is detected 0x02 SYNC Polarity (read only)
0 HSYNC1
0: HSYNC1 is Active High 1: HSYNC1 is Active Low
1 HSYNC2
0: HSYNC2 is Active High 1: HSYNC2 is Active Low 2V S Y N C 1 Polarity 0: VSYNC1 is Active High 1: VSYNC1 is Active Low 3V S Y N C 2 Polarity 0: VSYNC2 is Active High 1: VSYNC2 is Active Low
4 HSYNC1
0: HSYNC1 is Standard Sync 1: HSYNC1 is Trilevel Sync
5 HSYNC2
0: HSYNC2 is Standard Sync 1: HSYNC2 is Trilevel Sync 7:6 N/A Returns 0 0x03 HSYNC Slicer (0x44) 2:0 HSYNC1 Threshold 000 = lowest (0.4V) All values referred to 100 = default (2.0V) voltage at HSYNC input 111 = highest (3.2V) pin, 240mV hysteresis
3 Reserved Set to 00
6:4 HSYNC2 Threshold See HSYNC1
7 Disable Glitch Filter 0: HSYNC/VSYNC Digital Glitch Filter Enabled (default)
1: HSYNC/VSYNC Digital Glitch Filter Disabled 0x04 SOG Slicer (0x08) 3:0 SOG1 and SOG2 Threshold 0x0 = lowest (0mV) 40mV hysteresis at 0x8 = default (160mV) all settings 0xF = highest (300mV) 20mV step size
4 SOG Filter
0: SOG low pass filter disabled (default) 1: SOG low pass filter enabled, 14MHz corner 5S O G H y s t e r e s i s Disable 0: 40mV SOG hysteresis enabled 1: 40mV SOG hysteresis disabled (default) 7:6 Reserved Set to 00. X98027
12 FN8221.0 May 26, 2005 0x05 Input configuration (0x00) 0 Channel Select 0: VGA1 1: VGA2
1 Input Coupling 0: AC coupled (positive input connected to clamp DAC
during clamp time, negative input disconnected from outside pad and always internally tied to appropriate clamp DAC) 1: DC coupled (+ and - inputs are brought to pads and never connected to clamp DACs). Analog clamp signal is turned off in this mode.
2 RGB/YUV 0: RGB inputs (Clamp DAC = 300mV for R, G, B, half scale
analog shift for R, G, and B, base ABLC™ target code = 0x00 for R, G, and B) 1: YUV inputs (Clamp DAC = 600mV for R and B, 300mV for G, half scale analog shift for G channel only, base ABLC™ target code = 0x00 for G, = 0x80 for R and B)
3 Sync Type 0: Separate HSYNC/VSYNC
1: Composite (from SOG or CSYNC on HSYNC)
4 Composite Sync
0: SOG IN 1: HSYNCIN Note: If Sync Type = 0, the multiplexer will pass HSYNCIN regardless of the state of this bit.
5 COAST CLAMP
0: DC restore clamping and ABLC™ suspended during COAST 1: DC restore clamping and ABLC™ continue during COAST 7:6 Reserved Set to 00. 0x06 Red Gain (0x55) 7:0 Red Gain Channel gain, where: 0x00: gain = 0.5 V/V (1.4VP-P input = full range of ADC) 0x55: gain = 1.0 V/V (0.7VP-P input = full range of ADC) 0xFF: gain = 2.0 V/V (0.35VP-P input = full range of ADC) 0x07 Green Gain (0x55) 7:0 Green Gain 0x08 Blue Gain (0x55) 7:0 Blue Gain 0x09 Red Offset (0x80) 7:0 Red Offset ABLC™ enabled: digital offset control. A 1 LSB change in this register will shift the ADC output by 1 LSB. ABLC™ disabled: analog offset control. These bits go to the upper 8 bits of the 10 bit offset DAC. A 1LSB change in this register will shift the ADC output approximately 1 LSB (Offset DAC range = 0) or 0.5LSBs (Offset DAC range = 1). 0x00 = min DAC value or -0x80 digital offset, 0x80 = mid DAC value or 0x00 digital offset, 0xFF = max DAC value or +0x7F digital offset 0x0A Green Offset (0x80) 7:0 Green Offset 0x0B Blue Offset (0x80) 7:0 Blue Offset 0x0C Offset DAC Configuration (0x00) 0 Offset DAC Ra nge 0: ±1/2 ADC fullscale (1 DAC LSB ~ 1 ADC LSB) 1: ±1/4 ADC fullscale (1 DAC LSB ~ 1/2 ADC LSB) 1 Reserved Set to 0. 3:2 Red Offset DAC LSBs These bits are the LSBs necessary for 10 bit manual offset DAC control. Combine with their respective MSBs in registers 0x09, 0x0A, and 0x0B to achieve 10 bit offset DAC control. 5:4 Green Offset DAC LSBs 7:6 Blue Offset DAC LSBs Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME DESCRIPTION X98027
13 FN8221.0 May 26, 2005 0x0D AFE Bandwidth (0x0E) 0 Unused Value doesn’t matter 3:1 AFE BW 3dB point for AFE lowpass filter 000: 100MHz 111: 780MHz (default) 7:4 Peaking 0000: Disabled (default) See Bandwidth and Peaking Control section for more information 0x0E PLL Htotal MSB (0x03) 5:0 PLL Htotal MSB 14 bit HTOTAL (number of active pixels) value The minimum HTOTAL value supported is 0x200. HTOTAL to PLL is updated on LSB write only.0x0F PLL Htotal LSB (0x20) 7:0 PLL Htotal LSB 0x10 PLL Sampling Phase (0x00) 5:0 PLL Sampling Phase Used to control the phase of the ADC’s sample point relative to the period of a pixel. Adjust to obtain optimum image quality. One step = 5.625° (1.56% of pixel period). 0x11 PLL Pre-coast (0x08) 7:0 Pre-coast Number of li nes the PLL will coast prior to the start of VSYNC. Applies only to internally generated COAST signals. 0x12 PLL Post-coast (0x00) 7:0 Post-coast Number of lines the PLL will coast after the end of VSYNC. Applies only to internally generated COAST signals. 0x13 PLL Misc (0x00) 0 PLL Lock Edge HSYNC1 0: Lock on trailing edge of HSYNC1 (default) 1: Lock on leading edge of HSYNC1
1 PLL Lock Edge
0: Lock on trailing edge of HSYNC2 (default) 1: Lock on leading edge of HSYNC2 2 Reserved Set to 0. 3C L K I N V IN Pin Disable 0: CLKINVIN pin enabled (default) 1: CLKINVIN pin disabled (internally forced low) 5:4 CLKINV IN Pin Function 00: CLKINV (default) 01: External CLAMP (see Note) 10: External COAST 11: External PIXCLK Note: the CLAMP pulse is used to - perform a DC restore (if enabled) - start the ABLC™ function (if enabled), and - update the data to the Offset DACs (always). When in the default internal CLAMP mode, the X98027 automatically generates the CLAMP pulse. If External CLAMP is selected, the Offset DAC values will only change on the leading edge of CLAMP. If there is no internal clamp signal, there will be up to a 100ms delay between when the PGA gain or offset DAC register is written to, and when the PGA or offset DAC is actually updated.
6 XTALCLKOUT
0: XTALCLK OUT= fCRYSTAL (default) 1: XTALCLKOUT= fCRYSTAL/2
7 Disable
0 = XTALCLKOUT enabled 1 = XTALCLKOUT is logic low 0x14 DC Restore and ABLC™ starting pixel MSB (0x00) 4:0 DC Restore and ABLC™ starting pixel (MSB) Pixel after HSYNCIN trailing edge to begin DC restore and ABLC™ functions. 13 bits. Set this register to the first stable black pixel following the trailing edge of HSYNCIN.0x15 DC Restore and ABLC™ starting pixel LSB (0x00) 7:0 DC Restore and ABLC™ starting pixel (LSB) 0x16 DC Restore Clamp Width (0x10) 7:0 DC Restore clamp width (pixels) Width of DC restore clamp used in AC-coupled configurations. Has no effect on ABLC™. Minimum value is 0x02 (a setting of 0x01 or 0x00 will not generate a clamp pulse). Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME DESCRIPTION X98027
14 FN8221.0 May 26, 2005 0x17 ABLC™ Configuration (0x40) 0 ABLC™ disable 0: ABLC™ enabled (default) 1: ABLC™ disabled 1 Reserved Set to 0. 3:2 ABLC™ pixel width Number of bla ck pixels averaged every line for ABLC™ function 00: 16 pixels [default] 01: 32 pixels 10: 64 pixels 11: 128 pixels 6:4 ABLC™ bandwidth ABLC™ Time constant (lines) = 2 (5+[6:4]) 000 = 32 lines 100 = 256 lines (default) 111 = 4096 lines 7 Reserved Set to 0. 0x18 Output Format (0x00) 0 Bus Width 0: 24 bits: Data output on R P, GP, BP only; RS, GS, BS are all driven low (default) 1: 48 bits: Data output on RP, GP, BP, RS, GS, BS
1 Interleaving
(48 bit mode only) 0: No interleaving: data changes on same edge of DATACLK (default) 1: Interleaved: Secondary databus data changes on opposite edge of DATACLK from primary databus 2B u s S w a p (48 bit mode only) 0: First data byte after trailing edge of HSOUT appears on RP, GP, BP (default) 1: First data byte after trailing edge of HSOUT appears on RS, GS, BS (primary and secondary busses are reversed) 3 Reserved Set to 0. 4 422 (24 bit mode only) 0: Data is formatted as 4:4:4 (RGB, default) 1: Data is decimated to 4:2:2 (YUV), blue channel is driven low 5D A T A C L K Polarity 0: HS OUT, VSOUT, and Pixel Data change on falling edge of DATACLK (default) 1: HS OUT, VSOUT, and Pixel Data change on rising edge of DATACLK
6 VSOUT Polarity 0: Active High (default)
1: Active Low
7 HSOUT Polarity 0: Active High (default)
1: Active Low 0x19 HSOUT Width (0x10) 7:0 HSOUT Width HSOUT widt h, in pixels. Minimum value is 0x01 for 24 bit modes, 0x02 for 48 bit modes. 0x1A Output Signal Disable (0x00) 0 Three-state R P[7:0] 0 = Output byte enabled 1 = Output byte three-stated These bits override all other I/O settings Output data pins have 58kΩ pulldown resistors to GNDD.
1 Three-state R S[7:0]
2 Three-state G P[7:0]
3 Three-state G S[7:0]
4 Three-state B P[7:0]
5 Three-state B S[7:0]
6 Three-state
0 = DATACLK enabled 1 = DATACLK three-stated
7 Three-state
0 = DATACLK enabled 1 = DATACLK three-stated Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME DESCRIPTION X98027
15 FN8221.0 May 26, 2005 Technical Highlights The X98027 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels. DPLL All video AFEs must phase lock to an HSYNC signal, supplied either directly or embedded in the video stream (Sync On Green). Historically this function has been implemented as a traditional analog PLL. At SXGA and lower resolutions, an analog PLL solution has proven adequate, if somewhat troublesome (due to the need to adjust charge pump currents, VCO ranges and other parameters to find the optimum trade-off for a wide range of pixel rates). As display resolutions and refresh rates have increased, however, the pixel period has decreased. An XGA pixel at a 60Hz refresh rate has 15.4ns to change and settle to its new value. But at UXGA 75Hz, the pixel period is 4.9ns. Most consumer graphics cards spend most of that time slewing to the new pixel value. The pixel may settle to its final value with 1ns or less before it begins slewing to the next pixel. In many cases it never settles at all. So precision, low-jitter sampling is a fundamental requirement at these speeds, and a difficult one for an analog PLL to meet. The X98027's DPLL has less than 250ps of jitter, peak to peak, and independent of the pixel rate. The DPLL generates 64 phase steps per pixel (vs. the industry standard 32), for fine, accurate positioning of the sampling point. The crystal-locked NCO inside the DPLL completely eliminates drift due to charge pump leakage, so there is inherently no frequency or phase change across a line. An intelligent all-digital loop filter/controller eliminates the need for the user to have to program or change anything (except for the number of pixels) to lock over a range from interlaced video (10MHz or higher) to QXGA 60Hz (275MHz). The DPLL eliminates much of the performance limitations and complexity associated with noise-free digitization of high speed signals. Automatic Black Level Compensation (ABLC™) and Gain Control Traditional video AFEs have an offset DAC prior to the ADC, to both correct for offsets on the incoming video signals and add/subtract an offset for user “brightness control”. This solution is adequate, but it places significant requirements on the system's firmware, which must execute a loop that detects the black portion of the signal and then servos the offset DACs until that offset is nulled (or produces the desired ADC output code). Once this has been accomplished, the offset (both the offset in the AFE and the offset of the video card generating the signal) is subject to drift - the temperature inside a monitor or projector can 0x1B Power Control (0x00) 0 Red Power-down 0 = Red ADC operational (default) 1 = Red ADC powered down
1 Green
0 = Green ADC operational (default) 1 = Green ADC powered down 2B l u e Power-down 0 = Blue ADC operational (default) 1 = Blue ADC powered down 3P L L Power-down 0 = PLL operational (default) 1 = PLL powered down 7:4 Reserved Set to 0 0x1C Reserved (0x47) 7:0 Reserved Set to 0x49 for best performance with NTSC and PAL video 0x23 DC Restore Clamp (0x08) 3:0 Reserved Set to 1000 6:4 DC Restore Clamp Impedance DC Restore clamp's ON resistance. Shared for all three channels 0: Infinite (clamp disconnected) (default) 1: 1600Ω 2: 800Ω 3: 533Ω 4: 400Ω 5: 320Ω 6: 267Ω 7: 228Ω
7 Reserved Set to 0
0x2B Crystal Compensation (0x14) 7:0 XTALCOMP See Table 8 on page 25. Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) BIT(s) FUNCTION NAME DESCRIPTION X98027
and the monitor's environment have reached steady state. once the monitor has warmed up. eliminated with 10 bit (1/4 of an 8 bit ADC LSB) accuracy. with 10 bit offset DACs under the firmware's control. features fully-independent gain and offset adjustment. YCbCr video inputs typically generated by DVD players. we will call these non-RGB signals YUV. enables the YUV signal processing mode of operation. 0x18[4] = 1) as shown in Table 2. TABLE 1. YUV MAPPING (4:4:4) TABLE 2. YUV MAPPING (4:2:2)
equalization pulses, or Macrovision signals. typically 0.3V below the video black level. FIGURE 7. VIDEO FLOW (INCLUDING ABLC™)
firmware determine which sync source is available. nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB). should take this into account when adjusting gains. in normal operation with RGB and YUV signals. minimum bandwidth setting that passes sharp edges. FIGURE 8. SYNC FLOW
harmonics lost due to excessive EMI filtering, cable losses, etc. or as an advanced user adjustment. Offset DAC (controlling “brightness”). significant bits in register 0x0C[7:2]. both ABLC™ and manual modes. potentially adding a small error in the ABLC accumulator. by the number of pixels specified in registers 0x14 and 0x15. is then used to generate a 10 bit DAC value. TABLE 3. BANDWIDTH CONTROL TABLE 4. PEAKING CORNER FREQUENCIES
programmed into registers 0x0E and 0x0F. sampling can be made accurately. sampling point. The sampling phase register is 0x10. any HSYNC transitions within 100ns of the initial transition. AFE to perform well even with pathological HSYNC signals. step size will be 400mV*5V/3.3V = 600mV per step. (110b) when locking on the falling edge. threshold lowered slightly to accommodate weak sync tips). in the X980xx are correct under all conditions. in the SYNC Status register. Trilevel Sync Detect section for more details. frequency peaking often seen on video signals. TABLE 5. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT
10 BIT
1 ADC LSB
1.0 ADC LSB
0.25 ADC LSB
0.5 ADC LSB
0.125 ADC LSB
SOG activity bit is also set. repetitive pattern that creates a waveform similar to SOG. the HSYNC and the SOG activity bits will be set, and valid. Detect = 0 and SOG Activity Detect = 1. may be significantly smaller, sometimes 300mVp-p or less. likelihood there is trilevel sync. being received is a reliable composite sync source. signals should be used for mode detection. TABLE 6. SYNC SOURCE DETECTION TABLE and confirm that CSYNC detect bit is set. likely to have trilevel sync, and set clamp start, width values appropriately if it is. 0 0 1 1 Sync is composite sync on SOG. Sync is likely to be trilevel. 0 0 0 X No valid sync sources on any input.
the VSYNC signal extracted by the X98027’s sync slicer. pulse plus pre- and post-equalization pulses (if present). and even/odd field detection. start of a new line of pixels. (1 DATACLK) increments (see Table 7). encoded YUV video if the source is an NTSC DVD. PLL during the VSYNC and Macrovision period. ADCs, the DPLL, and most of the internal clocks.
- Serial interface (including the crystal oscillator) to enable register read/write activity
- Activity and polarity detect functions (registers 0x01 and 0x02)
- The HSYNC OUT and VSYNCOUT pins (for mode detection)
TABLE 7. HS OUT WIDTH
24 BIT MODE,
- Crystal oscillator. The EMI from the crystal oscillator is negligible. This is due to an amplitude-regulated, low voltage sine wave oscillator circuit, instead of the typical high-gain square wave inverter-type oscillator, so there are no harmonics. The crystal oscillator is not a significant source of EMI.
- Digital output switching. This is the largest potential source of EMI. However, the EMI is determined by the PCB+ layout and the loading on the databus. The way to control this is to put series resistors on the output of all the digital pins. These resistor values should be adjusted to optimize signal quality on the bus. Intersil recommends starting with 22Ω and adjusting as necessary for the particular PCB layout and device loading. Recommendations for minimizing EMI are:
- Minimize the databus trace length
- Minimize the databus capacitive loading. If EMI is a problem in the final design, increase the value of the digital output series resistors to reduce slew rates on the bus. This can only be done as long as the scaler’s setup and hold timing requirements continue to be met. Alternate Pixel Sampling Two X98027s (AFEA and AFEB) may be used simultaneously to achieve effective sample rates greater than 275MHz. Each AFE is programmed with an HTOTAL value equal to one-half of the total number of pixels in a line. The CLOCKINV IN pin for AFEA is tied to ground, AFEB is tied to VD. Both AFEs are otherwise programmed identically, though some minor phase adjustment may be needed to compensate for any propagation delay mismatch between the two AFEs. The CLOCKINV IN setting shifts the phase of AFEB by 180 degrees from AFEA. AFEA now samples the even pixels on the rising edge of its DATACLK, while AFEB samples the odd pixels on the rising edge of its clock. With each AFE in 24 bit mode, two 24 bit data streams are generated (Figure 9). With both AFEs configured for 48 bit mode, a 96 bit datastream is generated (Figure 10). In both cases, AFE A and AFEB are on different DATACLK domains. In 24 bit mode, the data from each AFE must be latched on the rising edge of that AFE’s DATACLK. In 48 bit mode, the frequencies are low enough that the rising edge of AFE B can be used to capture both AFE B and AFEA data. HSYNCIN (to A and B) DATACLK (A) DATA (A) HSOUT (A) DATACLK (B) DATA (B) HSOUT (B) DPLL Lock Edge ½ DATACLK Delay CLKINVIN (A) = GNDD CLKINVIN (B) = VD D0 D2 D3DN D1 DN-3 DN-1 DN-2 P1 P2 P3 P4 P5 P6 P7 P8P0 P9 P10 P11 P12PN-3 PN-2 PN-1 PN Analog Video In (to A and B)
FIGURE 9. ALTERNATE PIXEL SAMPLING (24 BIT MODE)
- Register 0x1C should be set to 0x49 to improve DPLL performance in video modes
- Register 0x23 should be set to 0x78 to enable the DC Restore function
- Write the correct crystal compensation value to Register 0x2B (see below). Power Dissipation at QXGA Speeds Because of the very high speed of the X98027, power consumption is a concern. There are several things that can be done to reduce power consumption: Internal Clock Frequency The internal clock frequencies need to be tightly controlled to minimize power consumption. Register 0x2B should be set to 1 + the integer portion of (2*fPIXELCLOCKMAX/fCRYSTAL). For example, if the maximum pixel clock is 263MHz, and the crystal frequency is 24MHz, then register 0x2B should be set to 1 + INT(2*263/24) = 1 + INT(21.917) = 1 + 21 = 22 = 0x16. The following table illustrates the compensation values required to operate the X98027 at its maximum speed of 275MHz. If lower maximum Pixel Clock frequencies are needed, using the formula above will minimize power consumption. HSYNCIN (to A and B) PIXELCLK (A) (Internal) DATAPRI (A) HSOUT (A) DPLL Lock Edge ½ PIXELCLK = ¼ DATACLK Delay CLKINVIN (A) = GNDD P1 P2 P3 P4 P5 P6 P7 P8P0 P9 P10 P11 P12PN-3 PN-2 PN-1 PN Analog Video In (to A and B) DATASEC (A) DATACLK (A) DN-3 DN-1 CLKINVIN (B) = GNDD DN-2 DN PIXELCLK (B) (Internal) DATAPRI (B) HSOUT (B) DATASEC (B) DATACLK (B)
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
indicating next transaction will be a write. indicating next transaction(s) will be a read. This is the data read from the X98027’s configuration register. sequential bytes of data from the Configuration Register. Address written in the two steps previous. FIGURE 16. CONFIGURATION REGISTER READ
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