X96012_08 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Two Programmable Current Generators -± 3 . 2 m A M a x - 8-bit (256 Step) Resolution - Internally Programmable Full Scale Current Outputs - External Resistor Pin to Set Full Scale Current Outputs
  • Integrated 8-bit A/D Converter
  • Internal Voltage Reference with Output/Input
  • Temperature Compensation - Internal or External Sensor - -40°C to +100°C Range - +2.2°C/step Resolution - EEPROM Look-up Tables
  • Hot Pluggable
  • 2176-bit EEPROM - 17 Pages - 16 Bytes per Page
  • Write Protection Circuitry - Intersil BlockLock™ - Logic Controlled Protection - 2-wire Bus with 3 Slave Address Bits
  • 3V to 5.5V, Single Supply Operation
  • Package - 14 Ld TSSOP
  • Pb-Free Available (RoHS Compliant)

Applications

  • PIN Diode Bias Control
  • RF PA Bias Control
  • Temperature Compensated Process Control
  • Laser Diode Bias Control
  • Fan Control
  • Motor Control
  • Sensor Signal Conditioning
  • Data Aquisition Applications
  • Gain vs Temperature Control
  • High Power Audio
  • Open Loop Temperature Compensation
  • Closed Loop Current, Voltage, Pressure, Temperature, Speed, Position Programmable Voltage Sources, Electronic Loads, Output Amplifiers or Function Generator

Ordering Information

RANGE (°C) PACKAGE PKG. DWG. # X96012V14I X9601 2VI -40 to +100 14 Ld TSSOP M14.173 X96012V14IZ* (Note) X9601 2VIZ -40 to +100 14 Ld TSSOP (Pb-free) M14.173 *Add “-T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free pl astic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VSS I 2 VCC SCL WP VREF VSENSE I1SDA Data Sheet February 20, 2008

2 FN8216.3 February 20, 2008 Block Diagram Pin Descriptions SDA SCL WP 2-WIRE I2VREF VSENSE INTERFACE A2, A1, A0 DAC 2 ADC LOOK-UP TABLE 1 LOOK-UP TABLE 2 CONTROL AND STATUS GENERAL PURPOSE MEMORY MUX MUX DAC 1 MUX MUX TEMPERATURE SENSOR VOLTAGE REFERENCE PIN NUMBER PIN NAME PIN DESCRIPTION 1A 0 Device Address Select Pin 0. This pin determines the LSB of the device address required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor. 2A 1 Device Address Select Pin 1. This pin determines the intermediate bit of the device address required to communicate using the 2-wire interface. The A1 pin has an on-chip pull-down resistor. 3A 2 Device Address Select Pin 2. This pin determines the MSB of the device address required to communicate using the 2-wire interface. The A2 pin has an on-chip pull-down resistor. 4V CC Supply Voltage. 5W P Write Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection is enabled preventing any “Write” operation. When HIGH, various areas of the memory can be protected using the Block Lock bits BL1 and BL0. The WP pin has an on-chip pull-down resistor, which enables the Write Protection when this pin is left floating. 6S C L Serial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data input and output at the SDA pin. 7S D A Serial Data. This pin is the 2-wire interface data into or out of the device. It is TTL compatible when used as an input, and it is Open Drain when used as an output. This pin requires an external pull-up resistor. 8I 1 Current Generator 1 Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. 9R 1 Current Programming Resistor 1. A resistor between this pin and VSS can set the maximum output current available at pin I1. If no resistor is used, the maximum current must be selected using control register bits. 10 R 2 Current Programming Resistor 2. A resistor between this pin and VSS can set the maximum output current available at pin I2. If no resistor is used, the maximum current must be selected using control register bits. 11 V SS Ground. 12 V SENSE Sensor Voltage Input. This voltage input may be used to drive the input of the on-chip A/D converter. 13 V REF Reference Voltage Input or Output. This pin can be configured as either an Input or an Output. As an Input, the voltage at this pin is provided by an external source. As an Output, the voltage at this pin is a buffered output voltage of the on-chip bandgap reference circuit. In both cases, the voltage at this pin is the reference for the A/D converter and the two D/A converters. 14 I2 Current Generator 2 Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. X96012

3 FN8216.3 February 20, 2008 Absolute Maximum Ratings Thermal Information All Voltages are Referred to VSS DC Output Current at Pins R1, R2, VREF and VSENSE Thermal Resistance (Typical, Note 1) θ JA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Voltage on V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Conditions are as follows, unless otherwise specified. All typical values are for TA = +25°C and 5V at pin VCC. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin VSS. All bits in control registers are “0”. 255Ω, 0.1%, resistor connected between R1 and VSS, and another between R2 and VSS. 400kHz TTL input at SCL. SDA pulled to VCC through an external 2kΩ resistor. 2-wire interface in “standby” (see Notes 9 and 10 on page 5). WP, A0, A1, and A2 floating. VREF pin unloaded. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT Iccstby Stand-by Current into V CC Pin R 1 and R2 floating, VREF unloaded. 2 mA Iccfull Full Operation Current into V CC Pin 2-wire interface reading from memory, I1 and I2 both connected to VSS, DAC input bytes: FFh, VREF unloaded. 15 mA Iccwrite Nonvolatile Write Current into VCC Pin Average from START condition until tWP after the STOP condition WP: VCC, R1 and R2 Floating, VREF unloaded. 4m A IPLDN On-chip Pull-down Current at WP, A0, A1, and A2 V(WP), V(A0), V(A1), and V(A2) from 0V to VCC 01 2 0 µ A VILTTL SCL and SDA, Input Low Voltage 0.8 V VIHTTL SCL and SDA, Input High Voltage 2.0 V IINTTL SCL and SDA Input Current Pin voltage between 0 and V CC, and SDA as an input. -1 10 µA VOLSDA SDA Output Low Voltage I(SDA) = 2mA 0 0.4 V IOHSDA SDA Output High Current V(SDA) = V CC 0 100 µA VILCMOS WP, A0, A1, and A2 Input Low Voltage 0 0.2 x V CC V VIHCMOS WP, A0, A1, and A2 Input High Voltage 0.8 x VCC VCC V VRefout Output Voltage at V REF at +25°C -20µA ≤ I(VREF) ≤ 20µA 1.205 1.21 1.215 V RVREF VREF Pin Input Resistance VRM bit = “1”, +25°C 20 40 k Ω TCOref Temperature Coefficient of V REF Output Voltage Notes 2 and 8 -100 +100 ppm/°C VRef Range Voltage Range when V REF is an Input Note 6 1 1.3 V TSenseRange Temperature Sensor Range Note 2 -40 100 °C TSenseAccuracy Temperature Sensor Accuracy +/-2 °C X96012

4 FN8216.3 February 20, 2008 IR Current from pin R1 or R2 to VSS 0 3200 µA VPOR Power-on Reset Threshold Voltage 1.5 2.8 V VCCRamp V CC Ramp Rate 0.2 50 mV/µs VADCOK ADC Enable Minimum Voltage Figure 11 2.6 2.8 V NOTES: 2. These parameters are periodically sampled and not 100% tested. 3. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 4. The device goes into Standby: 200ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby t WC after a STOP that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address Byte. 5. t WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 6. For this range of V(V REF) the full scale sink mode current at I1 and I2 follows V(VREF) with a linearity error smaller than 1%. 7. These parameters are periodically sampled and not 100% tested. 8. TCO ref = [Max V(VREF) - Min V(VREF)] x 106/(1.21V x +140°C). Electrical Specifications Conditions are as follows, unless otherwise specified. All typical values are for TA = +25°C and 5V at pin VCC. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin VSS. All bits in control registers are “0”. 255Ω, 0.1%, resistor connected between R1 and VSS, and another between R2 and VSS. 400kHz TTL input at SCL. SDA pulled to VCC through an external 2kΩ resistor. 2-wire interface in “standby” (see Notes 9 and 10 on page 5). WP, A0, A1, and A2 floating. VREF pin unloaded. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT D/A Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions). SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT IFS00 I1 or I2 Full Scale Current, with External Resistor Setting (Notes 9, 12) 1.56 1.58 1.6 mA (Notes 2, 9, 13) 3.2 mA IFS01 I1 or I2 Full Scale Current, with Internal Low Current Setting Option DAC input Byte = FFh, Source or sink mode, V(I1) and V(I2) are V CC - 1.2V in source mode and 1.2V in sink mode. (Notes 10, 11) 0.3 0.4 0.5 mA IFS10 I1 or I2 Full Scale Current, with Internal Middle Current Setting Option 0.64 0.85 1.06 mA IFS11 I1 or I2 Full Scale Current, with Internal High Current Setting Option 11 . 3 1 . 6 m A OffsetDAC I1 or I2 D/A Converter Offset Error 1 1 LSB FSErrorDAC I1 or I2 D/A Converter Full Scale Error -2 2 LSB DNLDAC I1 or I2 D/A Converter Differential Nonlinearity -0.5 0.5 LSB INLDAC I1 or I2 D/A Converter Integral Nonlinearity with Respect to a Straight Line Through 0 and the Full Scale Value -1 1 LSB V ISink I1 or I2 Sink Voltage Compliance (Note 12) 1.2 V CC V (Notes 2, 13) 2.5 V CC V VISource I1 or I2 Source Voltage Compliance (Note 12) 0 V CC - 1.2 V (Notes 2, 13) 0 V CC - 2.5 V X96012

5 FN8216.3 February 20, 2008 IOVER I1 or I2 Overshoot on D/A Converter Data Byte Transition DAC input byte changing from 00h to FFh and vice versa, V(I1) and V(I2) are VCC - 1.2V in source mode and 1.2V in sink mode. (Note 2) 0µ A IUNDER I1 or I2 Undershoot on D/A Converter Data Byte Transition 0µ A trDAC I1 or I2 Rise Time on D/A Converter Data Byte Transition; 10% to 90% 53 0 µ s TCOI1I2 Temperature Coefficient of Output Current I1 or I2 when Using Internal Resistor Setting Bits I1FSO[1:0] ¦ 002 or Bits I2FSO[1:0] ¦ 002, VRMbit = “1” See Figure 8 ±200 ppm/°C NOTES: 9. DAC input Byte = FFh, Source or sink mode. 10. LSB is defined as divided by the resistance between R 1 or R2 to VSS. 11. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in LSB. FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNLDAC. INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB. 13. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum VCC = 4.5V. The compliance voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%. D/A Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions). (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT V(VRef) 255x[] A/D Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions). SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT ADCTIME A/D Converter Conversion Time Proportional to A/D converter input voltage. This value is maximum at full scale input of A/D converter. ADCfiltOff = “1” 9m s RINADC VSense Pin Input Resistance VSense as an input, ADCIN bit = “1” 100 k Ω CINADC VSense Pin Input Capacitance VSens e as an input, ADCIN bit = “1”, Frequency = 1 MHz. (Note 2) 17 p F VINADC VSense Input Signal Range This is the A/D Converter Dynamic Range. ADCIN bit = “1” 0V ( V R e f ) V THE ADC IS MONOTONIC OffsetADC A/D Converter Offset Error (Notes 2, 14) ±1 LSB FSErrorADC A/D Converter Full Scale Error ±1 LSB DNLADC A/D Converter Differential Nonlinearity ±0.5 LSB INLADC A/D Converter Integral Nonlinearity ±1 LSB TempStepADC Temperature Step Causing One Step Increment of ADC Output (Note 2) 0.52 0.55 0.58 °C Out25ADC ADC Output at +25°C 01110101 2 X96012

6 FN8216.3 February 20, 2008 NOTES: 14. LSB” is defined as V(VRef)/255, “Full-Scale” is defined as V(VRef). 15. Offset ADC: For an ideal converter, the first transition of its transfer curve occurs at above zero. Offset error is the amount of deviation between the measured first transition point and the ideal point. FSErrorADC: For an ideal converter, the last transition of its transfer curve occurs at . Full-Scale Error is the amount of deviati on between the measured last transition point and the ideal point, after subtracting the Offset from the measured curve. DNLADC: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Full-scale errors before calculating DNL. INLADC: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured transfer curve is adjusted for Offset and Full scale errors before calculating INL. A/D Converter Characteristics (See “Electrical Specifications” table starting on page 3 for standard conditions). SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT 0.5 x V(VRef) 255[] 254.5 x V(VRef) 255[] 2-Wire Interface AC Characteristics SYMBOL PARAMETER TEST CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNITS fSCL SCL Clock Frequency See “2-Wire Interface Test Conditions” on page 6 See Figures 1, 2, 3. (Note 18) 400 kHz tIN (Note 2) Pulse width Suppression Time at Inputs 50 ns tAA (Note 2) SCL Low to SDA Data Out Valid 900 ns tBUF (Note 2) Time the Bus Free Before Start of New Transmission 1300 ns tLOW Clock Low Time 1.3 1200 (Note 18) µs tHIGH Clock High Time 0.6 1200 (Note 18) µs tSU:STA Start Condition Set-up Time 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:DAT Data In Set-up Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Set-up Time 600 ns tDH Data Output Hold Time 50 ns tR (Note 2) SDA and SCL Rise Time 20 +0.1Cb (Note 16) 300 ns tF (Note 2) SDA and SCL Fall Time 20 +0.1Cb (Note 16) 300 ns tSU:WP (Note 2) WP Set-up Time 600 ns tHD:WP (Note 2) WP Hold Time 600 ns Cb (Note 2) Capacitive Load for Each Bus Line 400 pF 2-Wire Interface Test Conditions Input Pulse Levels 10% to 90% of VCC Input Rise and Fall Times, between 10% and 90% 10ns Input and Output Timing Threshold Level 1.4V External Load at Pin SDA 2.3k Ω to V CC and 100pF to VSS X96012

increases reliability, and reduces board space requirements. independently programmed to either sink or source current. to an absolute resolution of 0.39% (256 steps/8-bit). 64 bytes from each nonvolatile look-up table (LUT). FIGURE 3. NON-VOLATILE WRITE CYCLE TIMING Intersil Sensor Conditioner Product Family FSO = Full Scale Output, Ext = External, Int = Internal.

9 FN8216.3 February 20, 2008 Principles of Operation Control and Status Registers The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X96012. The X96012 contains seven Control, one Status, and several Reserved registers, each being one Byte wide. (Figure 4). The Control registers 0 through 6 are located at memory addresses 80h through 86h respectively. The Status register is at memory address 87h, and the Reserved registers at memory address 88h through 8Fh. All bits in Control register 6 always power-up to the logic state “0”. All bits in Control registers 0 through 5 power-up to the logic state value kept in their corresponding nonvolatile memory cells. The nonvolatile bits of a register retain their stored values even when the X96012 is powered down, then powered back up. The nonvolatile bits in Control 0 through Control 5 registers are all preprogrammed to the logic state “0” at the factory. Bits indicated as “Reserved” are ignored when read, and must be written as “0”, if any Write operation is performed to their registers. A detailed description of the function of each of the Control and Status register bits follows: Control Register 0 This register is accessed by performing a Read or Write operation to address 80h of memory. BL1, BL0: BLOCK LOCK PROTECTION BITS (NON-VOLATILE) These two bits are used to inhibit any write operation to certain addresses within the memory array. The protected region of memory is determined by the values of the two bits, as shown in Table 1. If the user attempts to perform a write operation to a protected region of memory, the operation is aborted without changing any data in the array. Notice that if the Write Protect (WP ) input pin of the X96012 is active (LOW), then any write operation to the memory is inhibited, irrespective of the Block Lock bit settings. VRM: VOLTAGE REFERENCE PIN MODE (NON-VOLATILE) The VRM bit configures the Voltage Reference pin (VREF) as either an input or an output. When the VRM bit is set to “0” (default), the voltage at pin VREF is an output from the X96012’s internal voltage reference. When the VRM bit is set to “1”, the voltage reference for the VREF pin is external. See Figure 5. ADCIN: A/D CONVERTER INPUT SELECT (NON-VOLATILE) The ADCIN bit selects the input of the on-chip A/D converter. When the ADCIN bit is set to “0” (default), the output of the on-chip temperature sensor is the input to the A/D converter. When the ADCIN bit is set to “1”, the input to the A/D converter is the voltage at the VSENSE pin. See Figure 7. ADCFILTOFF: ADC FILTERING CONTROL (NON-VOLATILE) When this bit is “1”, the status register at 87h is updated after every conversion of the ADC. When this bit is “0” (default), the status register is updated after four consecutive conversions with the same result, on the 6 MSBs. NV1234: CONTROL REGISTERS 1, 2, 3 AND 4 VOLATILITY MODE SELECTION BIT (NON-VOLATILE) When the NV1234 bit is set to “0” (default), bytes written to Control registers 1, 2, 3, and 4 are stored in volatile cells, and their content is lost when the X96012 is powered down. When the NV1234 bit is set to “1”, bytes written to Control registers 1, 2, 3, and 4 are stored in both volatile and nonvolatile cells, and their value doesn’t change when the X96012 is powered down and powered back up. See “Writing to Control Registers” on page 20. I1DS: CURRENT GENERATOR 1 DIRECTION SELECT BIT (NON-VOLATILE) The I1DS bit sets the polarity of Current Generator 1, DAC1. When this bit is set to “0” (default), the Current Generator 1 of the X96012 is configured as a Current Source. Current Generator 1 is configured as a Current Sink when the I1DS bit is set to “1”. See Figure 8. I2DS: CURRENT GENERATOR 2 DIRECTION SELECT BIT (NON-VOLATILE) The I2DS bit sets the polarity of Current Generator 2, DAC2. When this bit is set to “0” (default), the Current Generator 2 of the X96012 is configured as a Current Source. Current Generator 2 is configured as a Current Sink when the I2DS bit is set to “1”. See Figure 8. Control Register 1 This register is accessed by performing a Read or Write operation to address 81h of memory. This byte’s volatility is determined by bit NV1234 in Control register 0. TABLE 1. BL1 BL0 PROTECTED ADDRESSES (SIZE) PARTITION OF ARRAY LOCKED 0 0 None (Default) None (Default) 0 1 00h to 7Fh (128 bytes) GPM 1 0 00h to 7Fh and 90h to CFh (192 bytes) GPM, LUT1 1 1 00h to 7Fh and 90h to 10Fh (256 bytes) GPM, LUT1, LUT2 X96012

REGISTERS IN BYTE ADDRESSES 88h THROUGH 8Fh ARE RESERVED. FIGURE 4. CONTROL AND STATUS REGISTER FORMAT

12 FN8216.3 February 20, 2008 Control Register 4 This register is accessed by performing a Read or Write operation to address 84h of memory. This byte’s volatility is determined by bit NV1234 in Control register 0. D2DA7 - D2DA0: D/A 2 DIRECT ACCESS BITS When bit D2DAS (bit 7 in Control register 5) is set to “1”, the input to the D/A converter 1 is the content of bits D2DA-D2DA0, and it is not a row of LUT2. When bit D2DAS is set to “0” (default) these eight bits are ignored by the X96012. See Figure 9. Control Register 5 This register is accessed by performing a Read or Write operation to address 85h of memory. I1FSO1 - I1FSO0: CURRENT GENERATOR 1 FULL SCALE OUTPUT SET BITS (NON-VOLATILE) These two bits are used to set the full scale output current at the Current Generator 1 pin, I1. If both bits are set to “0” (default), an external resistor connected between pin R 1 and VSS, determines the full scale output current available at pin I1. The other three options are indicated in Table 2. The direction of this current is set by bit I1DS in Control register 0. See Figure 8. I2FSO1 - I2FSO0: CURRENT GENERATOR 2 FULL SCALE OUTPUT CURRENT SET BITS (NON-VOLATILE) These two bits are used to set the full scale output current at the Current Generator 2 pin, I2. If both bits are set to “0” (default), an external resistor connected between pin R 2 and Vss, determines the full scale output current available at pin I2. The other three options are indicated Table 3. The direction of this current is set by bit I2DS in Control Register 0. L1DAS: LUT1 DIRECT ACCESS SELECT BIT (NON-VOLATILE) When bit L1DAS is set to “0” (default), LUT1 is addressed by the output of the on-chip A/D converter. When bit L1DAS is set to “1”, LUT1 is addressed by bits L1DA5 - L1DA0. D1DAS: D/A 1 DIRECT ACCESS SELECT BIT (NON-VOLATILE) When bit D1DAS is set to “0” (default), the input to the D/A converter 1 is a row of LUT1. When bit D1DAS is set to “1”, that input is the content of the Control register 3. L2DAS: LUT2 DIRECT ACCESS SELECT BIT (NON-VOLATILE) When bit L2DAS is set to “0” (default), LUT2 is addressed by the output of the on-chip A/D converter. When bit L2DAS is set to “1”, LUT2 is addressed by bits L2DA5 - L2DA0. D2DAS: D/A 2 DIRECT ACCESS SELECT BIT (NONVOLATILE) When bit D2DAS is set to “0” (default), the input to the D/A converter 2 is a row of LUT2. When bit D2DAS is set to “1”, that input is the content of the Control register 4. Control Register 6 This register is accessed by performing a Read or Write operation to address 86h of memory. WEL: WRITE ENABLE LATCH (VOLATILE) The WEL bit controls the Write Enable status of the entire X96012 device. This bit must be set to “1” before any other Write operation (volatile or nonvolatile). Otherwise, any proceeding Write operation to memory is aborted and no ACK is issued after a Data Byte. The WEL bit is a volatile latch that powers up in the “0” state (disabled). The WEL bit is enabled by writing 10000000 2 to Control register 6. Once enabled, the WEL bit remains set to “1” until the X96012 is powered down, and then up again, or until it is reset to “0” by writing 00000000 2 to Control register 6. A Write operation that modifies the value of the WEL bit will not cause a change in other bits of Control register 6. Status Register - ADC Output This register is accessed by performing a Read operation to address 87h of memory. AD7 - AD0: A/D CONVERTER OUTPUT BITS (READ ONLY) These eight bits are the binary output of the on-chip A/D converter. The output is 00000000 2 for minimum input and 111111112 for full scale input. The six MSBs select a row of the LUTs. TABLE 2. I1FSO1 I1FSO0 I1 FULL SCALE OUTPUT CURRENT 0 0 Set externally via pin R 1 (Default) 01 ± 0 . 4 m A * 1 0 ±0.85mA* 11 ± 1 . 3 m A * NOTE: *No external resistor should be connected in these cases between R 1 and VSS. TABLE 3. I2FSO1 I2FSO2 I2 FULL SCALE OUTPUT CURRENT 0 0 Set externally via pin R2 (Default) 0 1 ±0.4mA* 10 ± 0 . 8 5 m A * 1 1 ±1.3mA* NOTE: *No external resistor should be connected in these cases between R 2 and VSS. X96012

LUT2) and the appropriate row selection bits. See Figure 9. on page 9, and “Control Register 2” on page 10. independent current mode D/A converters. “polarity select” circuit block.

6 OR 7 IN CONTROL

3 AND 2 IN CONTROL

FIGURE 8. D/A CONVERTER BLOCK DIAGRAM

changing the data byte at the D/A converter input. input byte to the corresponding D/A converter. ±3.2mA, which is obtained using a resistance of 255Ω for Rx. X96012, or may be selected from one of three internal values. on page 9 and “Control and Status Registers” on page 9). transition is monotonic and glitchless. directly setting the D/A converter input byte. The options are summarized in Tables 5 and 6. FIGURE 9. LOOK-UP TABLE (LUT) OPERATION TABLE 5. D/A CONVERTER 1 ACCESS SUMMARY TABLE 6. D/A CONVERTER 2 ACCESS SUMMARY

parts, namely: (Refer to Figure 15).

  • General Purpose Memory (GPM)
  • Look-up Table 1 (LUT1)
  • Look-up Table 2 (LUT2)
  • Control and Status Registers The GPM is all nonvolatile EEPROM, located at memory addresses 00h to 7Fh. The Control and Status registers of the X96012 are used in the test and setup of the device in a system. These registers are realized as a combination of both volatile and nonvolatile memory. These registers reside in the memory locations 80h through 8Fh. The reserved bits within registers 80h through 86h, must be written as “0” if writing to them, and should be ignored when reading. The reserved registers, from 88h through 8Fh, must not be written, and their content should be ignored. Both look-up tables LUT1 and LUT2 are realized as non-volatile EEPROM, and extend from memory locations 90h - CFh and D0h - 10Fh respectively. These look-up tables are dedicated to storing data solely for the purpose of setting the outputs of Current Generators I1 and I2 respectively. All bits in both look-up tables are preprogrammed to “0” at the factory. Addressing Protocol Overview All Serial Interface operations must begin with a START, followed by a Slave Address Byte. The Slave address selects the X96012, and specifies if a Read or Write operation is to be performed. It should be noted that the Write Enable Latch (WEL) bit must first be set in order to perform a Write operation to any other bit. See “WEL: Write Enable Latch (Volatile)” on page 12. Also, all communication to the X96012 over the 2-wire serial bus is conducted by sending the MSB of each byte of data first. Even though the 2176 bit memory consists of four differing functions, it is physically realized as one contiguous array, organized as 17 pages of 16 bytes each. The X96012 2-wire protocol provides one address byte, therefore, only 256 bytes can be addressed directly. The next few sections explain how to access the different areas for reading and writing. SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER 81 9 START ACK SCL FROM MASTER

FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER

64 BYTES

16 BYTES

128 BYTES

FIGURE 15. X96012 MEMORY MAP FIGURE 16. SLAVE ADDRESS (SA) FORMAT

a STOP condition, which initiates the nonvolatile write cycle. completion of the internal write cycle. special cases within that page. first data byte of such operation is written to location 100h. FIGURE 18. BYTE WRITE SEQUENCE FIGURE 19. PAGE WRITE OPERATION

5 BYTES7 BYTES

5 BYTES

FIGURE 20. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11

Status Registers” on page 9. the last Data Byte. See Figure 22. increments by one during transmission of each Data Byte. Status Registers” on page 9. FIGURE 21. WRITING TO CONTROL REGISTERS 1, 2, 3 AND 4

22 FN8216.3 February 20, 2008 Data Protection There are four levels of data protection designed into the X96012: 1- Any Write to the device first requires setting of the WEL bit in Control 6 register; 2- The Block Lock can prevent Writes to certain regions of memory; 3- The Write Protection pin disables any writing to the X96012; 4- The proper clock count, data bit sequence, and STOP condition is required in order to start a nonvolatile write cycle, otherwise the X96012 ignores the Write operation. WP: Write Protection Pin When the Write Protection (WP) pin is active (LOW), any Write operations to the X96012 is disabled, except the writing of the WEL bit. X96012

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8216.3 February 20, 2008 X96012 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06