X96011 INTERSIL | Alldatasheet

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FN8215.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X96011 Temperature Sensor with Look Up Table Memory and DAC

FEATURES

  • Single Programmable Current Generator —±1.6 mA max. —8-bit (256 Step) Resolution —Internally Programmabl e full scale Current Outputs
  • Integrated 8-bit A/D Converter
  • Internal Voltage Reference
  • Temperature Compensation —Internal Sensor —-40°C to +100°C Range —2.2°C / step resolution —EEPROM Look-up Table
  • Hot Pluggable
  • Write Protection Circuitry —Intersil BlockLock™ —Logic Controlled Protection
  • 2-wire Bus with 3 Slave Address Bits
  • 3V to 5.5V, Single Supply Operation
  • Package —14 Ld TSSOP
  • Pb-Free Plus Anneal Available (RoHS Compliant)

APPLICATIONS

  • PIN Diode Bias Control
  • RF PA Bias Control
  • Temperature Compensated Process Control
  • Laser Diode Bias Control
  • F a n C o n t r o l
  • Motor Control
  • Sensor Signal Conditioning
  • Data Aquisition Applications
  • Gain vs. Temperature Control
  • High Power Audio
  • Open Loop Temperature Compensation
  • Close Loop Current, Voltage, Pressure, Temper- ature, Speed, Position Programmable Voltage sources, electronic loads, output amplifiers, or function generator

DESCRIPTION

The X96011 is a highly integrated bias controller which incorporates a digitally controlled Programmable Cur- rent Generator, and temperature compensation using one look-up table. All functi ons of the device are con- trolled via a 2-wire digital serial interface. The temperature compensated Programmable Current Generator varies the output current with temperature according to the contents of the associated nonvolatile look-up table. The look-up table may be programmed with arbitrary data by the user, via the 2-wire serial port, and an internal temperature sensor is used to control the output current response. PIN CONFIGURATION

Ordering Information

RANGE (°C) PACKAGE X96011V14I X96011V I -40 to 100 14 Ld TSSOP X96011V14IZ (Note) X96011VI Z -40 to 100 14 Ld TSSOP (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Vss A2 3 NC NC NC Vcc A0 1 7 8 SCL 6 A1 2 WP 5 NC NC IOUTSDA TSSOP 14L Data Sheet October 25, 2005

2 FN8215.1 October 25, 2005 BLOCK DIAGRAM PIN ASSIGNMENTS TSSOP Pin Pin Name Pin Description 1A 0 Device Address Select Pin 0. This pin determines the LSB of the device address required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor. 2A 1 Device Address Select Pin 1. This pin determines the intermediate bit of the device address re- quired to communicate using the 2-wire interface. The A1 pin has an on-chip pull-down resistor. 3A 2 Device Address Select Pin 2. This pin determines the MSB of the device address required to com- municate using the 2-wire interface. The A2 pin has an on-chip pull-down resistor. 4V c c Supply Voltage. 5W P Write Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection is enabled preventing any “Write” operation. When HIGH, various areas of the memory can be pro- tected using the Block Lock bits BL1 and BL0. The WP pin has an on-chip pull-down resistor, which enables the Write Protection when this pin is left floating. 6S C L Serial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data input and output at the SDA pin. 7S D A Serial Data. This pin is the 2-wire interface data into or out of the device. It is TTL compatible when used as an input, and it is Open Drain when used as an output. This pin requires an external pull up resistor. OUT Current Generator Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. 9N C No Connect. 10 NC No Connect. 11 Vss Ground. 12 NC No Connect. 13 NC No Connect. 14 NC No Connect. SDA SCL WP 2-Wire IOUT Interface A2, A1, A0 DAC ADC Look-up Table Control & Status Mux Mux Temperature Sensor Voltage Reference X96011

3 FN8215.1 October 25, 2005 ABSOLUTE MAXIMUM RATINGS All voltages are referred to Vss. COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Min. Max. Units Temperature -40 +100 °C Temperature while writing to memory 0 +70 °C Voltage on Vcc Pin 35 . 5 V Voltage on any other Pin -0.3 Vcc + 0.3 V X96011

4 FN8215.1 October 25, 2005 ELECTRICAL CHARACTERISTICS (Conditions are as follows, unless otherwise specified) All typical values are for 25°C ambient temperature and 5 V at pin Vcc. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss. Bit 7 in control register 0 is “1”, while other bits in control registers are “0”. 400kHz TTL input at SCL. SDA pulled to Vcc through an external 2kΩ resistor. 2-wire interface in “standby” (see notes 1 and 2 below). WP, A0, A1, and A2 floating. Notes: 1. The device goes into Standby: 200 ns a fter any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby tWC after a STOP that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the cor- rect Slave Address Byte. 2. t WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. This parameter is periodically sampled and not 100% tested. Symbol Parameter Min Typ Max Unit Test Conditions / Notes Iccstby Standby current into Vcc pin 2 mA Iout floating, sink mode Iccfull Full operation current into Vcc pin 6 mA 2-wire interface reading from memory, Iout connected to Vss, DAC input bytes: FFh Iccwrite Nonvolatile Write current into Vcc pin 4 mA Average from START condition until t WP after the STOP condition WP: Vcc, Iout floating, sink mode VRef unloaded. IPLDN On-chip pull down current at WP, A0, A1,and A2 01 2 0 µAV ( W P ), V(A0), V(A1), and V(A2) from 0V to Vcc VILTTL SCL and SDA, input Low voltage 0.8 V VIHTTL SCL and SDA, input High voltage 2.0 V IINTTL SCL and SDA input current -1 10 µA Pin voltage between 0 and Vcc, and SDA as an input. VOLSDA SDA output Low voltage 0 0.4 V I(SDA) = 2 mA IOHSDA SDA output High current 0 100 µA V(SDA) = Vcc VILCMOS WP, A0, A1, and A2 input Low voltage 00 . 2 x V c c V VIHCMOS WP, A0, A1, and A2 input High voltage 0.8 x Vcc Vcc V TSenseRange Temperature sensor range -40 100 °C See note 3. VPOR Power-on reset threshold voltage 1.5 2.8 V VccRamp Vcc Ramp Rate 0.2 50 mV / µs VADCOK ADC enable minimum voltage 2.6 2.8 V See Figure 8. X96011

5 FN8215.1 October 25, 2005 D/A CONVERTER CHARACTERISTICS (See pg. 5 for standard conditions) Notes: 1. LSB is defined as divided by the resistance between R1 or R2 to Vss. 2. Offset DAC: The Offset of a DAC is defined as t he deviation between the measured and ideal out put, when the DAC input is 01h. It is expressed in LSB. FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC. DNLDAC: The Differential Non-Linearity of a DAC is defined as th e deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNLDAC. INLDAC: The Integral Non-Linearity of a DAC is defined as the deviati on between the measured and ideal transfer curves, after adjust- ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB. 3. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min Typ Max Unit Test Conditions / Notes IFS Iout full scale current 1.56 1.58 1.6 mA DAC input Byte = FFh, Source or sink mode, V(Iout) is Vcc–1.2V in source mode and 1.2V in sink mode. See notes 1 and 2. Offset DAC Iout D/A converter offset error 1 1 LSB FSErrorDAC Iout D/A converter full scale error -2 2 LSB DNLDAC Iout D/A converter Differential Nonlinearity -0.5 0.5 LSB INLDAC Iout D/A converter Integral Nonlinearity with respect to a straight line through 0 and the full scale value -1 1 LSB VISink I1 Sink Voltage Compliance 1.2 Vcc V In this range the current at I1 vary < 1% VISource I1 Source Voltage Compliance 0 Vcc - 1.2 V In this range the current at I1 vary < 1% I OVER I1 overshoot on D/A Converter data byte transition 0 µA DAC input byte changing from 00h to FFh and vice versa, V(I1) is Vcc - 1.2V in source mode and 1.2V in sink mode. See note 3. I UNDER I1 undershoot on D/A Converter data byte transition 0 µA trDAC I1 rise time on D/A Converter data byte transition; 10% to 90% 53 0 µs TCOI1I2 Temperature coefficient of output current Iout ±200 ppm/°C See Figure 5. V(VRef) 255x[] X96011

6 FN8215.1 October 25, 2005 A/D CONVERTER CHARACTERISTICS (See pg. 5 for standard conditions) Notes: 1. “LSB” is defined as V(VRef)/255, “Full Scale” is defined as V(VRef). 2. Offset ADC: For an ideal converter, the first transition of its transfer curve occurs at above zero. Offset error is the amount of deviation between the measured first transition point and the ideal point. FSErrorADC: For an ideal converter, the last transition of its transfer curve occurs at . Full Scale Error is the amount of deviation between the measured last transition point and the ideal point, after subtracting the Offset from the measured curve. DNLADC: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating DNL. INLADC: The deviation of the measured transfer function of an A/D conver ter from the ideal transfer function. The INL error is also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans- fer curve is adjusted for Offset and Fullscale errors before calculating INL. 3. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min Typ Max Unit Test Conditions / Notes ADCTIME A/D converter conversion time 9 ms Proportional to A/D converter input voltage. This value is maximum at full scale input of A/D converter. ADCfiltOff = “1” The ADC is monotonic Offset ADC A/D converter offset error ±1 LSB See notes 1 and 2 FSErrorADC A/D converter full scale error ±1 LSB DNLADC A/D Converter Differential Nonlinearity ±0.5 LSB INLADC A/D converter Integral Nonlinearity ±1 LSB TempStepADC Temperature step causing one step increment of ADC output 0.52 0.55 0.58 °C See note 3 Out25 ADC ADC output at 25°C 01110101 2 0.5 x V(VRef) 255[] 254.5 x V(VRef) 255[] X96011

7 FN8215.1 October 25, 2005 2-WIRE INTERFACE A.C. CHARACTERISTICS 2-WIRE INTERFACE TEST CONDITIONS NONVOLATILE WRITE CYCLE TIMING Notes: 1. Cb = total capacitance of one bus line (SDA or SCL) in pF. 2. t WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. The minimum frequency requirement applie s between a START and a STOP condition. 4. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min Typ Max Units Test Conditions / Notes fSCL SCL Clock Frequency 1 (3) 400 kHz See “2-Wire Interface Test Conditions” (below), See Figure 1, Figure 2 and Figure 3. tIN(4) Pulse width Suppression Time at inputs 50 ns tAA(4) SCL Low to SDA Data Out Valid 900 ns tBUF(4) Time the bus free before start of new transmission 1300 ns tLOW Clock Low Time 1.3 1200 (3) µs tHIGH Clock High Time 0.6 1200 (3) µs tSU:STA Start Condition Setup Time 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 600 ns tDH Data Output Hold Time 50 ns tR(4) SDA and SCL Rise Time 20 +0.1Cb(1) 300 ns tF(4) SDA and SCL Fall Time 20 +0.1Cb(1) 300 ns tSU:WP(4) WP Setup Time 600 ns tHD:WP(4) WP Hold Time 600 ns Cb(4) Capacitive load for each bus line 400 pF Input Pulse Levels 10 % to 90 % of Vcc Input Rise and Fall Times, between 10% and 90% 10 ns Input and Output Timing Threshold Level 1.4V External Load at pin SDA 2.3k Ω to Vcc and 100 pF to Vss Symbol Parameter Min Typ Max Units Test Conditions / Notes tWC(2) Nonvolatile Write Cycle Time 5 10 ms See Figure 3 X96011

9 FN8215.1 October 25, 2005 INTERSIL SENSOR CONDITIONER PRODUCT FAMILY FSO = Full Scale Output, Ext = External, Int = Internal DEVICE DESCRIPTION The combination of the X96011 functionality and Inter- sil’s QFN package lowers system cost, increases reli- ability, and reduces board space requirements. The on-chip Programmable Current Generator may be independently programmed to either sink or source current. The maximum current generated is deter- mined by using an externally connected programming resistor, or by selecting one of three predefined val- ues. Both current generators have a maximum output of ±1.6 mA, and may be controlled to an absolute res- olution of 0.39% (256 steps / 8 bit). The current generator is driven using either an on- board temperature sensor or Control Registers. The internal temperature sensor operates over a very broad temperature range (-40 °C to +100°C). The sen- sor output drives an 8-bit A/D converter. The six MSBs of the ADC output select one of 64 bytes from the non- volatile look-up table (LUT). The contents of the selected LUT row (8-bit wide) drives the input of an 8-bit D/A converter, which gener- ates the output current. All control and setup parameters of the X96011, including the look-up table, are programmable via the 2-wire serial port. Device Title Features / Functions Internal Temperature Sensor External Sensor Input Internal Voltage Reference VREF Input / Ouput General Purpose EEPROM Look Up Table Organi- zation # of DACs FSO Current DAC Setting Resistors X96010 Sensor Conditioner with Dual Look-Up Table Memory and DACs No Yes Yes Yes No Dual Bank Dual Ext X96011 Temperature Sensor with Look-Up Table Memory and DAC Yes No Yes No No Single Bank Single Int X96012 Universal Sensor Conditioner with Dual Look-Up Table Memory and DACs Yes Yes Yes Yes Yes Dual Bank Dual Ext / Int X96011

10 FN8215.1 October 25, 2005 PRINCIPLES OF OPERATION CONTROL AND STATUS REGISTERS The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X96011. The X96011 contains five Control, one Status, and several Reserved registers, each being one Byte wide (See Figure 4). The Control registers 0 through 6 are located at memory addresses 80h through 86h respectively. The Status register is at memory address 87h, and the Reserved registers at memory address 82h, 84h, and 88h through 8Fh. All bits in Control register 6 always power-up to the logic state “0”. All bits in Control registers 0 through 5 power- up to the logic state value kept in their corresponding nonvolatile memory cells. The nonvolatile bits of a reg- ister retain their stored values even when the X96011 is powered down, then powered back up. The nonvolatile bits in Control 0 through Control 5 registers are all pre- programmed to the logic state “0” at the factory, except the cases that indicate “1” in Figure 1. Bits indicated as “Reserved” are ignored when read, and must be written as “0”, if any Write operation is performed to their registers. A detailed description of the function of each of the Control and Status register bits follows: Control Register 0 This register is accessed by performing a Read or Write operation to address 80h of memory. ADC FILTOFF: ADC F ILTERING CONTROL (NON- VOLATILE ) When this bit is “1”, the status register at 87h is updated after every conversion of the ADC. When this bit is “0” (default), the status register is updated after four consecutive conversions with the same result, on the 6 MSBs. NV13: C ONTROL REGISTERS 1 AND 3 VOLATILITY MODE SELECTION BIT (NON-VOLATILE) When the NV13 bit is set to “0” (default), bytes written to Control registers 1 and 3 are stored in volatile cells, and their content is lost when the X96011 is powered down. When the NV13 bit is set to “1”, bytes written to Control registers 1 and 3 are stored in both volatile and nonvolatile cells, and their value doesn’t change when the X96011 is powered down and powered back up. See “Writing to Control Registers” on page 21. IDS: C URRENT GENERATOR DIRECTION SELECT BIT (NON-VOLATILE) The IDS bit sets the polarity of the Current Generator. When this bit is set to “0” (default), the Current Gener- ator of the X96011 is configured as a Current Source. The Current Generator is configured as a Current Sink when the IDS bit is set to “1”. See Figure 5. X96011

Figure 4. Control and Status Register Format Registers in byte addresses 82h, 84h, and 88h through 8Fh are reserved. Registers bits shown as 0 or 1 should always use these values for proper operation.

12 FN8215.1 October 25, 2005 Control Register 1 This register is accessed by performing a Read or Write operation to address 81h of memory. This byte’s volatility is determined by bit NV13 in Control register 0. LDA5 - LDA0: LUT D IRECT ACCESS BITS When bit LDAS (bit 4 in Control register 5) is set to “1”, the LUT is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. When bit LDAS is set to “0”, these six bits are ignored by the X96011. See Figure 7. A value between 00h (00 10) and 3Fh (6310) may be writ- ten to these register bits, to select the corresponding row in the LUT. The written value is added to the base address of the LUT (90h). Control Register 3 This register is accessed by performing a Read or Write operation to address 83h of memory. This byte’s volatility is determined by bit NV13 in Control register 0. DDA7 - DDA0: D/A D IRECT ACCESS BITS When bit DDAS (bit 5 in Control register 5) is set to “1”, the input to the D/A converter is the content of bits DDA7 - DDA0, and it is not a row of LUT. When bit DDAS is set to “0” (default) these eight bits are ignored by the X96011. See Figure 6. Control Register 5 This register is accessed by performing a Read or Write operation to address 85h of memory. IFSO1 - IFSO0: C URRENT GENERATOR FULL SCALE OUTPUT SET BITS (NON-VOLATILE) These two bits are used to set the full scale output cur- rent at the Current Generator pin, Iout, according to the following table. The direct ion of this current is set by bit IDS in Control register 0. See Figure 5. LDAS: LUT D IRECT ACCESS SELECT BIT (NON- VOLATILE ) When bit LDAS is set to “0” (default), the LUT is addressed by the output of the on-chip A/D converter. When bit LDAS is set to “1”, LUT is addressed by bits LDA5 - LDA0. DDAS: D/A D IRECT ACCESS SELECT BIT (NON- VOLATILE ) When bit DDAS is set to “0” (default), the input to the D/A converter is a row of the LUT. When bit DDAS is set to “1”, that input is the content of the Control register 3. Control Register 6 This register is accessed by performing a Read or Write operation to address 86h of memory. I1FSO1 I1FSO0 I1 Full Scale Output Current 0 0 Reserved (Don’t Use) 01 ±0.4mA 10 ±0.85 mA 11 ±1.3 mA (Default) X96011

13 FN8215.1 October 25, 2005 WEL: WRITE ENABLE LATCH (VOLATILE) The WEL bit controls the Wr ite Enable status of the entire X96011 device. This bit must be set to “1” before any other Write operation (volatile or nonvolatile). Oth- erwise, any proceeding Write operation to memory is aborted and no ACK is issued after a Data Byte. The WEL bit is a volatile latch that powers up in the “0” state (disabled). The WEL bit is enabled by writing 10000000 2 to Control register 6. Once enabled, the WEL bit remains set to “1” until the X96011 is powered down, and then up again, or until it is reset to “0” by writing 00000000 2 to Control register 6. A Write operation that modifies the value of the WEL bit will not cause a change in other bits of Control register 6. Status Register - ADC Output This register is accessed by performing a Read opera- tion to address 87h of memory. AD7 - AD0: A/D CONVERTER OUTPUT BITS (READ ONLY) This byte is the binary output of the on-chip digital thermometer. The output is 00000000 2 for -40°C and 111111112 for 100°C. The six MSBs select a row of the LUT. LOOK-UP TABLE The X96011 memory array contains a 64-byte look-up table. The look-up table is associated to pin Iout’s out- put current generator through the D/A converter. The output of the look-up table is the byte contained in the selected row. By default this byte is the input to the D/A converter driving pin Iout. The byte address of the selected row is obtained by adding the look-up table base address 90h, and the appropriate row selection bits. See Figure 6. By default the look-up table selection bits are the 6 MSBs of the digital thermometer output. Alter- natively, the A/D conver ter can be bypassed and the six row selection bits are the six LSBs of Control Register 1 for the LUT. The selection between these options is illustrated in Figure 6. CURRENT GENERATOR BLOCK The Current Generator pin Iout is the output of the cur- rent mode D/A converter. D/A Converter Operation The Block Diagram for the D/A converter is shown in Figure 5. The input byte of the D/A converter selects a voltage on the non-inverting input of an operational amplifier. The output of the amplifier drives the gate of a FET. This node is also fed back to the inverting input of the amplifier. The drain of the FET is connected to the out- put current pin (Iout) via a “polarity select” circuit block. X96011

to the corresponding D/A converter. put current that the D/A converter may sink or source. (Ix + ∆Ix). The transition is monotonic and glitchless. Figure 7. Look-Up Table Addressing

17 FN8215.1 October 25, 2005 SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The mast er always initiates data transfers, and provides the clock for both transmit and receive operations. The X96011 operates as a slave in all applications. Serial Clock and Data Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP condi- tions. See Figure 10. On power-up of the X96011, the SDA pin is in the input mode. Serial Start Condition All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device contin uously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met. See Figure 9. Serial Stop Condition All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus. See Figure 9. Serial Acknowledge An ACK (Acknowledge), is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data. See Figure 11. The device responds with an ACK after recognition of a START condition followed by a valid Slave Address byte. A valid Slave Address byte must contain the Device Type Identifier 1010, and the Device Address bits matching the logic state of pins A2, A1, and A0. See Figure 13. If a write operation is selected, the device responds with an ACK after the receipt of each subsequent eight-bit word. In the read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device cont inues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state. The X96011 acknowledges all incoming data and address bytes except: 1) The “Slave Address Byte” when the “Device Identifier ” or “Device Address” are wrong; 2) All “Data Bytes” when the “WEL” bit is “0”, with the exception of a “Data Byte” addresses to loca- tion 86h; 3) “Data Bytes” following a “Data Byte” addressed to locations 80h, 85h, or 86h. X96011

Figure 12. X96011 Memory Map used in the test and setup of the device in a system. Write operation is to be performed. sending the MSB of each byte of data first. array, organized as 5 pages of 16 bytes each. different areas for reading and writing. Figure 13. Slave Address (SA) Format

64 Bytes

16 Bytes

X96011 initiates an internal high voltage write cycle. mine whether a high voltage write cycle is completed. START condition followed by a Slave Address Byte. can then proceed with a new Read or Write operation. master. The SDA output is at high impedance. described in the section “Writing to Control Registers” . Figure 14. Acknowledge Polling Sequence

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8215.1 October 25, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Code V14 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X96011