X96010V14I

X96010 INTERSIL | Alldatasheet

Document overview

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Technical content

FN8214.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X96010 Sensor Conditioner with Dual Look Up Table Memory and DACs

FEATURES

Two Programmable Current Generators —±3.2 mA max. —8-bit (256 Step) Resolution —External Resistor Pins to Set Full Scale Cur- rent Output
External Sensor Input (Single Ended)
Integrated 8-bit A/D Converter
Internal Voltage Reference with Output/Input
Temperature Compensation
EEPROM Look-up Tables
Hot Pluggable
Write Protection Circuitry —Intersil BlockLock™ —Logic Controlled Protection
2-wire Bus with 3 Slave Address Bits
3V to 5.5V, Single Supply Operation
Package —14 Ld TSSOP
Pb-Free Plus Anneal Available (RoHS Compliant)

APPLICATIONS

PIN Diode Bias Control
RF PA Bias Control
Temperature Compensated Process Control
Laser Diode Bias Control
F a n C o n t r o l
Motor Control
Sensor Signal Conditioning
Data Aquisition Applications
Gain vs. Temperature Control
High Power Audio
Open Loop Temperature Compensation
Close Loop Current, Voltage, Pressure, Temper- ature, Speed, Position Programmable Voltage sources, electronic loads, output amplifiers, or function generator

DESCRIPTION

The X96010 is a highly integrated bias controller which incorporates two digitally controlled Programmable Cur- rent Generators and temperature compensation with dedicated look-up tables. All functions of the device are controlled via a 2-wire digital serial interface. Two temperature compensated Programmable Cur- rent Generators, vary the output current with tempera- ture according to the contents of the associated nonvolatile look-up table. The look-up table may be programmed with arbitrary data by the user via the 2- wire serial port, and an external temperature sensor may be used to control the output current response. PIN CONFIGURATION

Ordering Information

RANGE (°C) PACKAGE X96010V14I X96010V I -40 to 100 14 Ld TSSOP X96010V14IZ (Note) X96010VI Z -40 to 100 14 Ld TSSOP (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Vss A2 3 Vcc A0 1 7 8 SCL 6 A1 2 WP 5 VRef VSense I1SDA TSSOP 14L Data Sheet October 25, 2005

2 FN8214.1 October 25, 2005 BLOCK DIAGRAM PIN ASSIGNMENTS SDA SCL WP 2-Wire I2VRef VSense Interface A2, A1, A0 DAC 2 ADC Look-up Table 1 Look-up Table 2 Control & Status Mux Mux DAC 1 Mux Mux Voltage Reference TSSOP Pin Pin Name Pin Description 1A 0 Device Address Select Pin 0. This pin determines the LSB of the device address required to com- municate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor. 2A 1 Device Address Select Pin 1. This pin determines the intermediate bit of the device address re- quired to communicate using the 2-wire interface. The A1 pin has an on-chip pull-down resistor. 3A 2 Device Address Select Pin 2. This pin determines the MSB of the device address required to com- municate using the 2-wire interface. The A2 pin has an on-chip pull-down resistor. 4V c c Supply Voltage. 5W P Write Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection is enabled preventing any “Write” operation. When HIGH, various areas of the memory can be protect- ed using the Block Lock bits BL1 and BL0. The WP pin has an on-chip pull-down resistor, which en- ables the Write Protection when this pin is left floating. 6S C L Serial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data input and output at the SDA pin. 7S D A Serial Data. This pin is the 2-wire interface data into or out of the device. It is TTL compatible when used as an input, and it is Open Drain when used as an output. This pin requires an external pull up resistor. 8I 1 Current Generator 1 Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. 9R 1 Current Programming Resistor 1. A resistor between this pin and Vss can set the maximum output current available at pin I1. If no resistor is used, the maximum current must be selected using control register bits. 10 R2 Current Programming Resistor 2. A resistor between this pin and Vss can set the maximum output current available at pin I2. If no resistor is used, the maximum current must be selected using control register bits. 11 Vss Ground. 12 VSense Sensor Voltage Input. This voltage input may be used to drive the input of the on-chip A/D converter. 13 VRef Reference Voltage Input or Output. This pin can be configured as either an Input or an Output. As an Input, the voltage at this pin is provided by an external source. As an Output, the voltage at this pin is a buffered output voltage of the on-chip bandgap reference circuit. In both cases, the voltage at this pin is the reference for the A/D converter and the two D/A converters. 14 I2 Current Generator 2 Output. This pin sinks or sources current. The magnitude and direction of the current is fully programmable and adaptive. The resolution is 8 bits. X96010

3 FN8214.1 October 25, 2005 ABSOLUTE MAXIMUM RATINGS All voltages are referred to Vss. D.C. Output Current at pins R1, R2, and COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Min. Max. Units Temperature -40 +100 °C Temperature while writing to memory 0 +70 °C Voltage on Vcc Pin 35 . 5 V Voltage on any other Pin -0.3 Vcc + 0.3 V ELECTRICAL CHARACTERISTICS (Conditions are as follows, unless otherwise specified) All typical values are for 25°C ambient temperature and 5V at pin Vcc. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss. Bit 3 in Control register 0 is “1”, while all other bits in control registers are “0”. 255Ω, 0.1%, resistor connected between R1 and Vss, and another between R2 and Vss. 400kHz TTL input at SCL. SDA pulled to Vcc through an external 2kΩ resistor. 2-wire interface in “standby” (see notes 1 and 2 on page 5). WP, A0, A1, and A2 floating. VRef pin unloaded. Symbol Parameter Min Typ Max Unit Test Conditions / Notes Iccstby Standby current into Vcc pin 2 mA R1 and R2 floating, VRef unloaded. Iccfull Full operation current into Vcc pin 15 mA 2-wire interface reading from memory, I1 and I2 both connected to Vss, DAC input bytes: FFh, VRef unloaded. Iccwrite Nonvolatile Write current into Vcc pin 4 mA Average from START condition until t WP after the STOP condition WP: Vcc, R1 and R2 floating, VRef unloaded. IPLDN On-chip pull down current at WP, A0, A1, and A2 01 2 0 µAV ( W P ), V(A0), V(A1), and V(A2) from 0V to Vcc VILTTL SCL and SDA, input Low voltage 0.8 V VIHTTL SCL and SDA, input High voltage 2.0 V IINTTL SCL and SDA input current -1 10 µA Pin voltage between 0 and Vcc, and SDA as an input. VOLSDA SDA output Low voltage 0 0.4 V I(SDA) = 2 mA IOHSDA SDA output High current 0 100 µA V(SDA) = Vcc VILCMOS WP, A0, A1, and A2 input Low voltage 0 0.2 x Vcc V X96010

4 FN8214.1 October 25, 2005 Notes: 1. The device goes into Standby: 200 ns a fter any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby tWC after a STOP that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the cor- rect Slave Address Byte. 2. t WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. For this range of V(VRef) the full scale sink mode current at I1 and I2 follows V(VRef) with a linearity error smaller than 1%. 4. This parameter is periodically sampled and not 100% tested. 5. TCO ref = [Max V(VREF) - Min V(VREF)] x 106/(1.21V x 140°C) VIHCMOS WP, A0, A1, and A2 input High voltage 0.8 x Vcc Vcc V VRefout Output Voltage at VRef at 25°C 1.205 1.21 1.215 V -20 µA ≤ I(VRef) ≤ 20 µA RVref VRef pin input resistance 20 40 k Ω VRM bit = “1”, 25°C TCOref Temperature coefficient of VRef output voltage -100 +100 ppm/° C See note 4 and 5. VRef Range Voltage range when VRef is an input 1 1.3 V See note 3. IR Current from pin R1 or R2 to Vss 0 3200 µA VPOR Power-on reset threshold voltage 1.5 2.8 V VccRamp Vcc Ramp Rate 0.2 50 mV / µs VADCOK ADC enable minimum voltage 2.6 2.8 V See Figure 10. ELECTRICAL CHARACTERISTICS (Continued) (Conditions are as follows, unless otherwise specified) All typical values are for 25°C ambient temperature and 5V at pin Vcc. Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin Vss. Bit 3 in Control register 0 is “1”, while all other bits in control registers are “0”. 255Ω, 0.1%, resistor connected between R1 and Vss, and another between R2 and Vss. 400kHz TTL input at SCL. SDA pulled to Vcc through an external 2kΩ resistor. 2-wire interface in “standby” (see notes 1 and 2 on page 5). WP, A0, A1, and A2 floating. VRef pin unloaded. Symbol Parameter Min Typ Max Unit Test Conditions / Notes X96010

5 FN8214.1 October 25, 2005 D/A CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions) Notes: 1. DAC input Byte = FFh, Source or sink mode. 2. LSB is defined as divided by the resistance between R1 or R2 to Vss. 3. Offset DAC: The Offset of a DAC is defined as t he deviation between the measured and ideal out put, when the DAC input is 01h. It is expressed in LSB. FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC. DNLDAC: The Differential Non-Linearity of a DAC is defined as th e deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNLDAC. INLDAC: The Integral Non-Linearity of a DAC is defined as the deviati on between the measured and ideal transfer curves, after adjust- ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB. 4. These parameters are periodically sampled and not 100% tested. 6. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum VCC = 4.5V. The compliance volt- age changes to 2.5V from the sourcing rail, and the current variation is <1%. Symbol Parameter Min Typ Max Unit Test Conditions / Notes IFS I1 or I2 full scale current 1.56 1.58 1.6 mA See note 1, 5, R = 510 Ω 3.2 mA See note 1, 4, 6, R = 255 Ω OffsetDAC I1 or I2 D/A converter offset error 1 1 LSB See notes 2 and 3. FSErrorDAC I1 or I2 D/A converter full scale error -2 2 LSB DNLDAC I1 or I2 D/A converter Differential Nonlinearity -0.5 0.5 LSB INLDAC I1 or I2 D/A converter Integral Nonlin- earity with respect to a straight line through 0 and the full scale value -1 1 LSB V ISink I1 or I2 Sink Voltage Compliance 1.2 Vcc V See note 5

2.5 Vcc V See note 4, 6

VISource I1 or I2 Source Voltage Compliance 0 Vcc-1.2 V See note 5 0 Vcc-2.5 V See note 4, 6 IOVER I1 or I2 overshoot on D/A Converter data byte transition 0 µA DAC input byte changing from 00h to FFh and vice versa, V(I1) and V(I2) are Vcc - 1.2V in source mode and 1.2V in sink mode. See note 4. I UNDER I1 or I2 undershoot on D/A Converter data byte transition 0 µA trDAC I1 or I2 rise time on D/A Converter data byte transition; 10% to 90% 53 0 µs TCOIout Temperataure coefficient of output current due to internal parameters -100 +100 ppm/ See Figure 7. VRMbit = “0” V(VRef) 255x[] X96010

6 FN8214.1 October 25, 2005 A/D CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions) Notes: 1. “LSB” is defined as V(VRef)/255, “Full Scale” is defined as V(VRef). 2. Offset ADC: For an ideal converter, the first transition of its transfer curve occurs at above zero. Offset error is the amount of deviation between the measured first transition point and the ideal point. FSErrorADC: For an ideal converter, the last transition of its tr ansfer curve occurs at . Full Scale Error is the amount of deviation between the measured last transition point and the ideal point, after subtracting the Offset from the measured curve. DNLADC: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs expressed in LSBs. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating DNL. INLADC: The deviation of the measured transfer function of an A/D conver ter from the ideal transfer function. The INL error is also defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans- fer curve is adjusted for Offset and Fullscale errors before calculating INL. 3. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min Typ Max Unit Test Conditions / Notes ADCTIME A/D converter conversion time 9 ms Proportional to A/D converter input voltage. This value is maximum at full scale input of A/D converter. ADCfiltOff = “1” RIN ADC VSense pin input resistance 100 k Ω VSense as an input, ADCIN bit = “1” CINADC VSense pin input capacitance 1 7 pF VSense as an input, ADCIN bit = “1”, Frequency = 1 MHz See note 3. VIN ADC VSense input signal range 0 V(VRef) V This is the A/D Converter Dynamic Range. ADCIN bit = “1” The ADC is monotonic Offset ADC A/D converter offset error ±1 LSB See notes 1 and 2 FSErrorADC A/D converter full scale error ±1 LSB DNLADC A/D Converter Differential Nonlinearity ±0.5 LSB INLADC A/D converter Integral Nonlinearity ±1 LSB 0.5 x V(VRef) 255[] 254.5 x V(VRef) 255[] X96010

7 FN8214.1 October 25, 2005 2-WIRE INTERFACE A.C. CHARACTERISTICS 2-WIRE INTERFACE TEST CONDITIONS NONVOLATILE WRITE CYCLE TIMING Notes: 1. Cb = total capacitance of one bus line (SDA or SCL) in pF. 2. t WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 3. The minimum frequency requirement applie s between a START and a STOP condition. 4. These parameters are periodically sampled and not 100% tested. Symbol Parameter Min Typ Max Unit s Test Conditions / Notes fSCL SCL Clock Frequency 1 (3) 400 kHz See “2-Wire Interface Test Conditions” (below), See Figure 1, Figure 2 and Figure 3. tIN(4) Pulse width Suppression Time at inputs 50 ns tAA(4) SCL Low to SDA Data Out Valid 900 ns tBUF(4) Time the bus free before start of new transmission 1300 ns tLOW Clock Low Time 1.3 1200 (3) µs tHIGH Clock High Time 0.6 1200 (3) µs tSU:STA Start Condition Setup Time 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 600 ns tDH Data Output Hold Time 50 ns tR(4) SDA and SCL Rise Time 20 +0.1Cb(1) 300 ns tF(4) SDA and SCL Fall Time 20 +0.1Cb(1) 300 ns tSU:WP(4) WP Setup Time 600 ns tHD:WP(4) WP Hold Time 600 ns Cb(4) Capacitive load for each bus line 400 pF Input Pulse Levels 10 % to 90 % of Vcc Input Rise and Fall Times, between 10% and 90% 10 ns Input and Output Timing Threshold Level 1.4V External Load at pin SDA 2.3k Ω to Vcc and 100 pF to Vss Symbol Parameter Min Typ Max Units Test Conditions / Notes tWC(2) Nonvolatile Write Cycle Time 5 10 ms See Figure 3 X96010

9 FN8214.1 October 25, 2005 INTERSIL SENSOR CONDITIONER PRODUCT FAMILY FSO = Full Scale Output, Ext = External, Int = Internal DEVICE DESCRIPTION The X96010 contains two independent Programmable Current Generators in one package. The combination of the X96010 functionality and Intersil’s QFN package lowers system cost, increa ses reliability, and reduces board space requirements. Two on-chip Programmable Current Generators may be independently programmed to either sink or source current. The maximum current generated is deter- mined by using an externally connected programming resistor. Both current generators have a maximum output of ±3.2 mA, and ma y be controlled to an abso- lute resolution of 0.39% (256 steps / 8 bit). Both current generators may be driven using an exter- nal sensor or Control Regi sters. The external sensor output drives a 8-bit A/D converter. The six MSBs of the ADC output select one of 64 bytes from each non- volatile look-up table (LUT). The contents of the selected LUT row (8-bit wide) drives the input of an 8-bit D/A converter, which gener- ates the output current. All control and setup parameters of the X96010, including the look-up tables, are programmable via the 2-wire serial port. Device Title Features / Functions Internal Temperature Sensor External Sensor Input Internal Voltage Reference VREF Input / Ouput General Purpose EEPROM Look Up Table Organi- zation # of DACs FSO Current DAC Setting Resistors X96010 Sensor Conditioner with Dual Look-Up Table Memory and DACs No Yes Yes Yes No Dual Bank Dual Ext X96011 Temperature Sensor with Look-Up Table Memory and DAC Yes No Yes No No Single Bank Single Int X96012 Universal Sensor Conditioner with Dual Look-Up Table Memory and DACs Yes Yes Yes Yes Yes Dual Bank Dual Ext / Int X96010

10 FN8214.1 October 25, 2005 PRINCIPLES OF OPERATION CONTROL AND STATUS REGISTERS The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X96010. The X96010 contains seven Control, one Status, and several Reserved registers, each being one Byte wide (See Figure 4). The Control registers 0 through 6 are located at memory addresses 80h through 86h respectively. The Status register is at memory address 87h, and the Reserved registers at memory address 88h through 8Fh. All bits in Control register 6 always power-up to the logic state “0”. All bits in Control registers 0 through 5 power- up to the logic state value kept in their corresponding nonvolatile memory cells. The nonvolatile bits of a reg- ister retain their stored values even when the X96010 is powered down, then powered back up. The nonvolatile bits in Control 0 through Control 5 registers are all pre- programmed to the logic state “0” at the factory, except the cases that indicate “1” in Figure 4. Bits indicated as “Reserved” are ignored when read, and must be written as “0”, if any Write operation is performed to their registers. A detailed description of the function of each of the Control and Status register bits follows: Control Register 0 This register is accessed by performing a Read or Write operation to address 80h of memory. VRM: V OLTAGE REFERENCE PIN MODE (NON- VOLATILE ) The VRM bit configures the Voltage Reference pin (VRef) as either an input or an output. When the VRM bit is set to “0” (default), the voltage at pin VRef is an output from the X96010’s internal voltage reference. When the VRM bit is set to “1”, the voltage reference for the VRef pin is external. See Figure 5. ADC FILTOFF: ADC F ILTERING CONTROL (NON- VOLATILE ) When this bit is“1”, the status register at 87h is updated after every conversion of the ADC. When this bit is “0” (default), the status register is updated after four consecutive conversions with the same result, on the 6 MSBs. NV1234: C ONTROL REGISTERS 1, 2, 3, AND 4 VOLA- TILITY MODE SELECTION BIT (NON-VOLATILE) When the NV1234 bit is set to “0” (default), bytes writ- ten to Control registers 1, 2, 3, and 4 are stored in vol- atile cells, and their content is lost when the X96010 is powered down. When the NV1234 bit is set to “1”, bytes written to Control regi sters 1, 2, 3, and 4 are stored in both vo latile and nonvolatile cells, and their value doesn’t change when the X96010 is powered down and powered back up. See “Writing to Control Registers” on page 23. I1DS: C URRENT GENERATOR 1 DIRECTION SELECT BIT (NON-VOLATILE) The I1DS bit sets the polarity of Current Generator 1, DAC1. When this bit is set to “0” (default), the Current Generator 1 of the X96010 is configured as a Current Source. Current Generator 1 is configured as a Cur- rent Sink when the I1DS bit is set to “1”. See Figure 7. X96010

Figure 4. Control and Status Register Format Registers in byte addresses 88h through 8Fh are reserved. Register bits shown as 0 or 1 should always use those values for proper operation.

12 FN8214.1 October 25, 2005 I2DS: CURRENT GENERATOR 2 DIRECTION SELECT BIT (NON-VOLATILE) The I2DS bit sets the polarity of Current Generator 2, DAC2. When this bit is set to “0” (default), the Current Generator 2 of the X96010 is configured as a Current Source. Current Generator 2 is configured as a Cur- rent Sink when the I2DS bit is set to “1”. See Figure 7. Control Register 1 This register is accessed by performing a Read or Write operation to address 81h of memory. This byte’s volatility is determined by bit NV1234 in Control register 0. L1DA5 - L1DA0: LUT1 D IRECT ACCESS BITS When bit L1DAS (bit 4 in Control register 5) is set to “1”, LUT1 is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. When bit L1DAS is set to “0”, these six bits are ignored by the X96010. See Figure 9. A value between 00h (00 10) and 3Fh (6310) may be writ- ten to these register bits, to select the corresponding row in LUT1. The written value is added to the base address of LUT1 (90h). Control Register 2 This register is accessed by performing a read or write operation to address 82h of memory. This byte’s vola- tility is determined by bit NV1234 in Control register 0. L2DA5 - L2DA0: LUT2 D IRECT ACCESS BITS When bit L2DAS (bit 6 in Control register 5) is set to “1”, LUT2 is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. When bit L2DAS is set to “0”, these six bits are ignored by the X96010. See Figure 9. A value between 00h (00 10) and 3Fh (6310) may be writ- ten to these register bits, to select the corresponding row in LUT2. The written value is added to the base address of LUT2 (D0h). Control Register 3 This register is accessed by performing a Read or Write operation to address 83h of memory. This byte’s volatility is determined by bit NV1234 in Control register 0. D1DA7 - D1DA0: D/A 1 D IRECT ACCESS BITS When bit D1DAS (bit 5 in Control register 5) is set to “1”, the input to the D/A converter 1 is the content of bits D1DA7 - D1DA0, and it is not a row of LUT1. When bit D1DAS is set to “0” (default) these eight bits are ignored by the X96010. See Figure 8. Control Register 4 This register is accessed by performing a Read or Write operation to address 84h of memory. This byte’s volatil- ity is determined by bit NV1234 in Control register 0. D2DA7 - D2DA0: D/A 2 D IRECT ACCESS BITS When bit D2DAS (bit 7 in Control register 5) is set to “1”, the input to the D/A converter 1 is the content of bits D2DA7 - D2DA0, and it is not a row of LUT2. When bit D2DAS is set to “0” (default) these eight bits are ignored by the X96010. (See Figure 8). Control Register 5 This register is accessed by performing a Read or Write operation to address 85h of memory. L1DAS: LUT1 D IRECT ACCESS SELECT BIT (NON- VOLATILE) When bit L1DAS is set to “0” (default), LUT1 is addressed by the output of the on-chip A/D converter. When bit L1DAS is set to “1”, LUT1 is addressed by bits L1DA5 - L1DA0. D1DAS: D/A 1 D IRECT ACCESS SELECT BIT (NON- VOLATILE) When bit D1DAS is set to “0” (default), the input to the D/A converter 1 is a row of LUT1. When bit D1DAS is set to “1”, that input is the content of the Control register 3. X96010

13 FN8214.1 October 25, 2005 L2DAS: LUT2 DIRECT ACCESS SELECT BIT (NON- VOLATILE) When bit L2DAS is set to “0” (default), LUT2 is addressed by the output of the on-chip A/D converter. When bit L2DAS is set to “1”, LUT2 is addressed by bits L2DA5 - L2DA0. D2DAS: D/A 2 D IRECT ACCESS SELECT BIT (NON- VOLATILE) When bit D2DAS is set to “0” (default), the input to the D/A converter 2 is a row of LUT2. When bit D2DAS is set to “1”, that input is the content of the Control register 4. Control Register 6 This register is accessed by performing a Read or Write operation to address 86h of memory. WEL: W RITE ENABLE LATCH (VOLATILE) The WEL bit controls the Wr ite Enable status of the entire X96010 device. This bit must be set to “1” before any other Write operation (volatile or nonvolatile). Oth- erwise, any proceeding Write operation to memory is aborted and no ACK is issued after a Data Byte. The WEL bit is a volatile latch that powers up in the “0” state (disabled). The WEL bit is enabled by writing 10000000 2 to Control register 6. Once enabled, the WEL bit remains set to “1” until the X96010 is powered down, and then up again, or until it is reset to “0” by writing 00000000 2 to Control register 6. A Write operation that modifies the value of the WEL bit will not cause a change in other bits of Control register 6. Status Register - ADC Output This register is accessed by performing a Read opera- tion to address 87h of memory. AD7 - AD0: A/D CONVERTER OUTPUT BITS (READ ONLY) These eight bits are the binary output of the on-chip A/D converter. The output is 00000000 2 for minimum input and 11111111 2 for full scale input. The six MSBs select a row of the LUTs. X96010

15 FN8214.1 October 25, 2005 A/D Converter Range From Figure 6 we can see that the operating range of the A/D converter input depends on the voltage reference. The table below summarizes the voltage range restrictions on the VSense and VRef pins in different configurations : VSense and VRef ranges LOOK-UP TABLES The X96010 memory array contains two 64-byte look- up tables. One is associated to pin I1’s output current generator and the other to pin I2’s output current gen- erator, through their corresponding D/A converters. The output of each look-up table is the byte contained in the selected row. By default these bytes are the inputs to the D/A converters driving pins I1 and I2. The byte address of the selected row is obtained by adding the look-up table base address (90h for LUT1, and D0h for LUT2) and the appropriate row selection bits. See Figure 8. By default the look-up table selection bits are the 6 MSBs of the A/D converter output. Alternatively, the A/D converter can be bypassed and the six row selection bits are the six LSBs of Control Registers 1 and 2, for the LUT1 and LUT2 respectively. The selection between these opti ons is illustrated in Fig- ure 9, and described in “I2DS: Current G enerator 2 Direction Select Bit (Non-volatile)” on page 12, and “Control Register 2” on page 12. CURRENT GENERATOR BLOCK The Current Generator pins I1 and I2 are outputs of two independent current mode D/A converters. D/A Converter Operation The Block Diagram for each of the D/A converters is shown in Figure 7. The input byte of the D/A converter selects a voltage on the non-inverting input of an operational amplifier. The output of the amplifier drives the gate of a FET, whose source is connected to ground via resistor R1 or R2. This node is also fed back to the inverting input of the amplifier. The drain of the FET is connected to the output current pin (I1 or I2) via a “polarity select” circuit block. VRef A/D Converter Input Ranges Internal VSense Pin 0 ≤ V(VSense) ≤ V(VRef) External VSense Pin 0 ≤ V(VRef) ≤ 1.3 V 0 ≤ V(VSense) ≤ V(VRef) All voltages referred to Vss. X96010

the input byte to the corresponding D/A converter. nected externally to pin Rx of the X96010. Status Register Format” on page 11). (Ix + ∆Ix). The transition is monotonic and glitchless. Figure 9. Look-Up Table Addressing

18 FN8214.1 October 25, 2005 D/A Converter 1 Access Summary D/A Converter 2 Access Summary The A/D converter is shared between the two current generators but the look-up tables, D/A converters, control bits, and selection bits can be set completely independently. Bits D1DAS and D2DAS are used to bypass the A/D converter and look-up tables, allowing direct access to the inputs of the D/A conver ters with the bytes in con- trol registers 3 and 4 respectively. See Figure 8, and the descriptions of the control bits. Bits I1DS and I2DS in Control Register 0 select the direction of the currents through pins I1 and I2 inde- pendently See Figure 7, and the descriptions of the control bits. POWER-ON RESET When power is applied to the Vcc pin of the X96010, the device undergoes a strict sequence of events before the current outputs of the D/A converters are enabled. When the voltage at Vcc becomes larger than the power-on reset threshold voltage (V POR), the device recalls all control bits from non-volatile memory into volatile registers. Next, the analog circuits are pow- ered up. When the voltage at Vcc becomes larger than a second voltage threshold (V ADCOK), the ADC is enabled. In the default case, after the ADC performs four consecutive conversions with the same exact result, the ADC output is used to select a byte from each look-up table. Those bytes become the input of the DACs. During all the previous sequence the input of both DACs are 00h. If bi t ADCfiltOff is “1”, only one ADC conversion is necessa ry. Bits D1DAS, D2DAS, L1DAS, and L2DAS, also modify the way the two DACs are accessed the first time after power- uppower-up, as described in “Control Register 5” on page 12. The X96010 is a hot pluggable device. Voltage dis- trubances on the Vcc pin are handled by the power-on reset circuit, allowing proper operation during hot plug- in applications. SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. The X96010 operates as a slave in all applications. L1DAS D1DAS Control Source 0 0 A/D converter through LUT1 (Default) 1 0 Bits L1DA5 - L1DA0 through LUT1 X 1 Bits D1DA7 - D1DA0 “X” = Don’t Care Condition (May be either “1” or “0”) L2DAS D2DAS Control Source 0 0 A/D converter through LUT2 (Default) 1 0 Bits L2DA5 - L2DA0 through LUT2 X 1 Bits D2DA7 - D2DA0 “X” = Don’t Care Condition (May be either “1” or “0”) X96010

SDA pin is in the input mode. reception of the eight bits of data. See Figure 13. bits matching the logic state of pins A2, A1, and A0. addressed to locations 80h, 85h, or 86h. Figure 10. D/A Converter Power-on Reset Response

Figure 14. X96010 Memory Map used in the test and setup of the device in a system. tors I1 and I2 respectively. Write operation is to be performed. sending the MSB of each byte of data first. array, organized as 9 pages of 16 bytes each. access the different areas for reading and writing.

64 Bytes

16 Bytes

X96010 initiates an internal high voltage write cycle. mine whether a high voltage write cycle is completed. START condition followed by a Slave Address Byte. can then proceed with a new Read or Write operation. written using a “Page Write” operation. described in the section “Writing to Control Registers” . Figure 16. Acknowledge Polling Sequence

7Fh, the output bytes are unpredictable. starts at location 100h if the Address Byte is FFh. (See “Control and Status Register Format”). Figure 21. Read Sequence

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8214.1 October 25, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Code V14 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X96010

Summary

Sensor Conditioner with Dual Look Up Table Memory and DACs October 25, 2005

Description