X9520V20IZ-AT1

X9520_06 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

Three Digitally Controlled Potentiometers (DCPs) - 64 Tap - 10k Ω - 100 Tap - 10k Ω - 256 Tap - 100k Ω - Nonvolatile - Write Protect Function
2kbit EEPROM Memory with Write Protect & Block Lock
2-Wire Industry Standard Serial Interface - Complies to the Gigabit Interface Converter (GBIC) specification
Power-on Reset (POR) Circuitry - Programmable Threshold Voltage - Software Selectable Reset Timeout - Manual Reset
Two Supplementary Voltage Monitors - Programmable Threshold Voltages
Single Supply Operation - 2.7V to 5.5V
Hot Pluggable
20 Ld Packages - CSP (Chip Scale Package) -T S S O P
Pb-Free Plus Anneal Available (RoHS Compliant)

Ordering Information

TEMP . RANGE (°C) PACKAGE X9520B20I-A -40 to +85 20 Ld CSP X9520B20I-AT1 -40 to +85 20 Ld CSP X9520B20I-BT1 -40 to +85 20 Ld CSP X9520V20I-A X9520V IA -40 to +85 20 Ld TSSOP X9520V20I-AT1 X9520V IA -40 to +85 20 Ld TSSOP X9520V20I-B X9520V IB -40 to +85 20 Ld TSSOP X9520V20I-BT1 X9520V IB -40 to +85 20 Ld TSSOP X9520V20IZ-A X9520V ZIA -40 to +85 20 Ld TSSOP (Pb-free) X9520V20IZ-AT1 X9520V ZIA -40 to +85 20 Ld TSSOP (Pb-free) X9520V20IZ-B X9520V ZIB -40 to +85 20 Ld TSSOP (Pb-free) X9520V20IZ-BT1 X9520V ZIB -40 to +85 20 Ld TSSOP (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet January 3, 2006

2 FN8206.1 January 3, 2006 Block Diagram Detailed Device Description The X9520 combines three Intersil Digitally Controlled Potentiometer (DCP) devices, V1/Vcc power-on reset control, V1/Vcc low voltage reset control, two supplementary voltage monitors, and integrated EEPROM with Block Lock™ protection, in one pa ckage. These functions are suited to the control, support, and monitoring of various system parameters in Fiber Channel/Gigabit Ethernet fiber optic modules, such as in Gigabit Interface Converter (GBIC) applications. The combination of the X9520 fucntionality lowers system cost, increases reliability, and reduces board space requirements using Intersil’s unique XBGA™ packaging. Two high resolution DCPs allow for the “set-and-forget” adjustment of Laser Driver IC parameters such as Laser Diode Bias and Modulation Currents. One lower resolution DCP may be used for setting sundry system parameters such as maximum laser output power (for eye safety requirements). Applying voltage to V CC activates the Power-on Reset circuit which allows the V1RO output to go HIGH, until the supply the supply voltage stabilizes for a period of time (selectable via software). The V1RO output then goes LOW. The Low Voltage Reset circuitry allows the V1RO output to go HIGH when V CC falls below the minimum VCC trip point. V1RO remains HIGH until VCC returns to proper operating level. A Manual Reset (MR) input allows the user to externally trigger the V1RO output (HIGH). Two supplementary Voltage Monitor circuits continuously compare their inputs to individual trip voltages. If an input voltage exceeds it’s associated trip level, a hardware output (V3RO, V2RO) are allowed to go HIGH. If the input voltage becomes lower than it’s associated trip level, the corresponding output is driven LOW. A corresponding binary representation of the two monitor circuit outputs (V2RO and V3RO) are also stored in latched, volatile (CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial port. An application of the V1RO output may be to drive the “ENABLE ” input of a Laser Driver IC, with MR as a “TX_DISABLE” input. V2RO and V3RO may be used to monitor “TX_FAULT” and “RX_LOS” conditions respectively. Intersil’s unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. This gives the designer great flexibility in changing system parameters, either at the time of manufacture, or in the field. The memory portion of the device is a CMOS serial EEPROM array with Intersil’s Block Lock™ protection. This memory may be used to store fiber optic module manufacturing data, serial numbers, or various other system parameters. The EEPROM array is internally organized as x 8, and utilizes Intersil’s proprietary Direct Write™ cells, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. The device features a 2-Wire interface and software protocol allowing operation on an I 2C™ compatible serial bus. DATA REGISTER COMMAND DECODE & CONTROL LOGIC SDA SCL POWER-ON / LOW VOLTAGE CONSTAT REGISTER PROTECT LOGIC EEPROM THRESHOLD RESET LOGIC GENERATION RESET VTRIP V1/Vcc VTRIP 2kbit V1RO RH2 RW2 RL2 MR 6 - BIT NONVOLATILE MEMORY RH0 RW0 RL0 WIPER REGISTER RH1 RW1 RL1 COUNTER V2RO WP V3RO 7 - BIT NONVOLATILE MEMORY NONVOLATILE MEMORY WIPER REGISTER COUNTER WIPER REGISTER COUNTER ARRAY 8 - BIT2 VTRIP X9520

3 FN8206.1 January 3, 2006 Pin Configuration RL2 RH0 V1/Vcc SCL RW0 RL0 RW1 RH1 VSS 10 RL1 RH2 1 MR 6 RW2 2 SDA 9 V3RO 5 WP V1RO V2RO NOT TO SCALE 2 3 4 A B C D E Top View – Bumps Down CSP20 Pin TSSOP RL2RW2 RH2V2 WPV3RO SCLRH0 SDARL1 V2RO V1/Vcc V3V1RO RW0 RL0 RH1 MR VSS RW1 Pin Descriptions TSSOP CSP NAME FUNCTION 1B 3 R H2 Connection to end of resistor array for (the 256 Tap) DCP 2. 2A 3 R w2 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2. 3A 4 R L2 Connection to other end of resistor array for (the 256 Tap) DCP 2. 4 B4 V3 V3 Voltage Monitor Input. V3 is the input to a non-invert ing voltage comparator circuit. When the V3 input is higher than the VTRIP3 threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to VSS when not used. 5 C3 V3RO V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than V TRIP3 and goes LOW when V3 is less than VTRIP3. There is no delay circuitry on this pin. The V3RO pin requires the use of an external “pull-up” resistor. 6 D3 MR Manual Reset. MR is a TTL level compatible input. Pulling t he MR pin active (HIGH) initiates a reset cycle to the V1RO pin (V1/Vcc RESET Output pin). V1RO will remain HIGH for time tpurst after MR has returned to it’s normally LOW state. The reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external “pull-down” resistor. 7 C4 WP Write Protect Control Pin. WP pin is a TTL level comp atible input. When held HIGH, Write Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled. 8 D4 SCL Serial Clock. This is a TTL level compatible input pin us ed to control the serial bus timing for data input and output. 9 E4 SDA Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 10 E1 Vss Ground. 11 E3 R L1 Connection to other end of resistor for (the 100 Tap) DCP 1. 12 E2 R w1 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1. 13 D1 R H1 Connection to end of resistor array for (the 100 Tap) DCP 1. 14 D2 R H0 Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0. 15 C1 R W0 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0. 16 C2 R L0 Connection to the other end of resistor array for (the 64 Tap) DCP 0. 17 B1 V2 V2 Voltage Monitor Input. V2 is the input to a non-invert ing voltage comparator circuit. When the V2 input is greater than the VTRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to VSS when not used. X9520

bits of data. Refer to Figure 3. place the device into a known state.

Three Digitally Controll ed Potentiometers (DCPs)
EEPROM array
Control and Status (CONSTAT) Register Depending upon the operation to be performed on each of these individual parts, a 1, 2 or 3 Byte protocol is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X9520 to be addressed, and specifies if a Read or Write operation is to be performed. It should be noted that in order to perform a write operation to either a DCP or the EEPROM array, the Write Enable Latch (WEL) bit must first be set (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” on page 13.) Slave Address Byte Following a START condition, the master must output a Slave Address Byte (Refer to Figure 4.). This byte consists of three parts:
The Device Type Identifier which consists of the most significant four bits of the Slave Address (SA7 - SA4). The Device Type Identifier must always be set to 1010 in order to select the X9520.
The next three bits (SA3 - SA1) are the Internal Device Address bits. Setting these bits to 000 internally selects the EEPROM array, while setting these bits to 111 selects the DCP structures in the X9520. The CONSTAT Register may be selected using the Internal Device Address 010.
The Least Significant Bit of the Slave Address (SA0) Byte is the R/W bit. This bit defines the operation to be performed on the device being addressed (as defined in the bits SA3 - SA1). When the R/W bit is “1”, then a READ operation is selected. A “0” selects a WRITE operation (Refer to Figure 4.) SCL from Master Data Output from Transmitter Data Output from Receiver 81 9 Start Acknowledge

FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER

proceed with a read or write operation (Refer to Figure 5.). The X9520 includes three independent resistor arrays.

000 EEPROM Array

010 CONSTAT Register

111 DCP

1 READ

FIGURE 4. SLAVE ADDRESS FORMAT FIGURE 5. ACKNOWLEDGE POLLING SEQUENCE FIGURE 6. DCP INTERNAL STRUCTURE

determines the Write Type (WT) performed. using a nonvolatile write operation. byte command sequence shown in Figure 9. ACKNOWLEDGE is then returned by the X9520. which DCP is being addressed (see Table below).

0 Select a Volatile Write operation to be performed on the

1 Select a Nonvolatile Write operation to be performed on

†This bit has no effect when a Read operation is being performed. FIGURE 8. INSTRUCTION BYTE FORMAT

11 R e s e r v e d

FIGURE 9. DCP WRITE COMMAND SEQUENCE

all bits of the data byte are relevant (See Figure 10). EEPROM, an Address Byte may also need to be specified. This Address Byte can contain the values 00h to FFh. ACKNOWLEDGE, and awaits the next eight bits of data. suppresses the ACKNOWLEDGE bit after the Address Byte. “rolls over” and goes back to ‘0’ on the same page. one byte at a time (See Figure 13). EEPROM array does not change. FIGURE 12. EEPROM PAGE WRITE OPERATION

powers down, and then up again. the CONSTAT Write command sequence (See Figure 18). bit that powers up in the disabled, LOW (“0”) state.

After a successful write operation to any bits of the CONSTAT register has been completed (See Figure 18).
When the X9520 is powered down.
When attempting to write to a Block Lock protected region of the EEPROM memory (See "BL1, BL0: Block Lock protection bits - (Nonvolatile)"). BL1, BL0: BLOCK LOCK PROTECTION BITS - (NONVOLATILE) The Block Lock protection bits (BL1 and BL0) are used to:
Inhibit a write operation from being performed to certain addresses of the EEPROM memory array
Inhibit a DCP write operation (changing the “wiper position”) The region of EEPROM memory which is protected/locked is determined by the combination of the BL1 and BL0 bits written to the CONSTAT register. It is possible to lock the regions of EEPROM memory shown in the table below: If the user attempts to perform a write operation on a protected region of EEPROM memory, the operation is aborted without changing any data in the array. When the Block Lock bits of the CONSTAT register are set to something other than BL1 = 0 and BL0 = 0, then the “wiper position” of the DCPs cannot be changed - i.e. DCP write operations cannot be conducted: The factory default setting for these bits are BL1 = 0, BL0 = 0. IMPORTANT NOTE: If the Write Protect (WP) pin of the X9520 is active (HIGH), then all nonvolatile write operations to both the EEPROM memory and DCPs are inhibited, irrespective of the Block Lock bit settings (See "WP: Write Protection Pin"). POR1, POR0: POWER-ON RESET BITS – (NONVOLATILE) Applying voltage to V CC activates the Power-on Reset circuit which holds V1RO output HIGH, until the supply voltage stabilizes above the VTRIP1 threshold for a period of time, tPURST (See Figure 30). The Power-on Reset bits, POR1 and POR0 of the CONSTAT register determine the tPURST delay time of the Power-on Reset circuitry (See "Voltage Monitoring Functions"). These bits of the CONSTAT register are nonvolatile, and therefore power-up to the last written state. BIT(S) DESCRIPTION WEL Write Enable Latch bit RWEL Register Write Enable Latch bit V2OS V2 Output Status flag V3OS V3 Output Status flag BL1 - BL0 Sets the Block Lock partition POR1 - POR0 Sets the Power-on Reset time POR1 WEL POR0 CS5CS6CS7 CS4 CS3 CS2 CS1 CS0 V3OSV2OS BL0BL1 RWEL

FIGURE 17. CONSTAT REGISTER FORMAT NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).

01 N O

10 N O

11 N O

The default for these bits are POR1 = 0, POR0 = 1. Monitor reset output pins V2RO and V3RO. At power-up the VxOS (x = 2,3) bits default to the value “0”. be set to a “1” when the corresponding VxRO output is HIGH.

The device is powered down, then back up
The corresponding VxRO output becomes LOW CONSTAT Register Write Operation The CONSTAT register is accessed using the Slave Address set to 1010010 (Refer to Figure 4.). Following the Slave Address Byte, access to the CONSTAT register requires an Address Byte which must be set to FFh. Only one data byte is allowed to be written for each CONSTAT register Write operation. The user must issue a STOP, after sending this byte to the register, to initiate the nonvolatile cycle that stores the BP1, BP0, POR1 and POR0 bits. The X9520 will not ACKNOWLEDGE any data bytes written after the first byte is entered (Refer to Figure 18.). Prior to writing to the CONSTAT register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps.
Write a 02H to the CONSTAT Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceded by a START and ended with a STOP).
Write a 06H to the CONSTAT Register to set the Register Write Enable Latch (RWEL) AND the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceded by a START and ended with a STOP).
Write a one byte value to the CONSTAT Register that has all the bits set to the desired state. The CONSTAT register can be represented as qxyst01r in binary, where xy are the Voltage Monitor Output Status (V2OS and V3OS) bits, st are the Block Lock Protection (BL1 and BL0) bits, and qr are the Power-on Reset delay time (t PUV1RO) control bits (POR1 - POR0). This operation is proceeded by a START and ended with a STOP bit. Since this is a nonvolatile write cycle, it will typically take 5ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (qxys t11r) then the RWEL bit is set, but the V2OS, V3OS, POR1, POR0, BL1 and BL0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and the X9520 does not return an ACKNOWLEDGE. For example, a sequence of writes to the device CONSTAT register consisting of [02H, 06H, 02H] will reset all of the nonvolatile bits in the CONSTAT Register to “0”. It should be noted that a write to any nonvolatile bit of CONSTAT register will be ignored if the Write Protect pin of the X9520 is active (HIGH) (See "WP: Write Protection Pin"). CONSTAT Register Read Operation The contents of the CONSTAT Register can be read at any time by performing a random read (See Figure 19). Using the Slave Address Byte set to 10100101, and an Address Byte of FFh. Only one byte is read by each register read operation. The X9520 resets itself after the first byte is read. The master should supply a STOP condition to be consistent with the bus protocol. After setting the WEL and/or the RWEL bit(s) to a “1”, a CONSTAT register read operation may occur, without interrupting a proceeding CONSTAT register write operation. POR1 POR0 POWER-ON RESET DELAY (T PUV1RO) 0 0 50ms 0 1 100ms (Default) 1 0 200ms 1 1 300ms S T A R T 1 010 010R / W A C K 11 1 1 1 1 11 A C K SCL SDA S T O P A C K CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 SLAVE ADDRESS BYTE ADDRESS BYTE CONSTAT REGISTER DATA IN

FIGURE 18. CONSTAT REGISTER WRITE COMMAND SEQUENCE

form of the Write Protection pin. disables nonvolatile write operations to the X9520. the write permission status of the device.

The proper clock count and data bit sequence is required prior to the STOP bit in order to start a nonvolatile write cycle. Voltage Monitoring Functions V1/Vcc Monitoring The X9520 monitors the supply voltage and drives the V1RO output HIGH (using an external “pull up” resistor) if V1/Vcc is lower than VTRIP1 threshold. The V1RO output will remain HIGH until V1/Vcc exceeds VTRIP1 for a minimum time of tPURST. After this time, the V1RO pin is driven to a LOW state. See Figure 30. For the Power-on/Low Voltage Reset function of the X9520, the V1RO output may be driven HIGH down to a V1/Vcc of 1V (V RVALID). See Figure 30. Another feature of the X9520, is that the value of tPURST may be selected in software via the CONSTAT register (See “POR1, POR0: Power-on Reset bits – (Nonvolatile)” on page 13.). It is recommended to stop communication to the device while V1R0 is HIGH. Also, setting the Manual Reset (MR) pin HIGH overrides the Power-on/Low Voltage circuitry and forces the V1RO output pin HIGH (See "MR: Manual Reset"). MR: Manual Reset The V1RO output can be forced HIGH externally using the Manual Reset (MR) input. MR is a de-bounced, TTL compatible input, and so it may be operated by connecting a push-button directly from V1/Vcc to the MR pin. V1RO remains HIGH for time tPURST after MR has returned to its LOW state (See Figure 20). An external “pull down” resistor is required to hold this pin (normally) LOW. Slave Address Address Byte A C K A C K S t a r t S t o p Slave Address Data A C K S t a r t SDA Bus Signals from the Slave Signals from the Master

FIGURE 19. CONSTAT REGISTER READ COMMAND SEQUENCE

0 Volts

FIGURE 20. MANUAL RESET RESPONSE

adjusted by the user, using the steps detailed below. before setting the new value. CONSTAT register before performing this write sequence. procedure described in “Setting a Higher VTRIPx Voltage”. Resetting the VTRIPx Voltage (x = 1,2,3). (Vp) to the WP pin before a START condition is set up on SDA. FIGURE 21. VOLTAGE MONITOR RESPONSE

calculated that the programming error is 3.09 - 3.0 = 0.09 V. plus the absolute value of the calculated error. pin V2 and execute the programming sequence. FIGURE 24. V TRIPx SETTING/RESET SEQUENCE (X = 1,2,3)

19 FN8206.1 January 3, 2006 Absolute Maximum Ratings Recommended Operating Conditions | Voltage on RHx– Voltage on RLx | Supply Voltage Limits CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Operating Characteristics SYMBOL PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT ICC1 (Note 1) Current into V CC Pin (X9520: Active) Read memory array (Note 3) Write nonvolatile memory f SCL = 400kHz 0.4 1.5 mA ICC2 (Note 2) Current into V CC Pin (X9520:Standby) With 2-Wire bus activity (Note 3) No 2-Wire bus activity V SDA = VCC MR = Vss WP = Vss or Open/Floating V SCL= VCC (when no bus activity else fSCL = 400kHz) µA ILI Input Leakage Current (SCL, SDA, MR) V IN (Note 4) = GND to VCC. 0.1 10 µA Input Leakage Current (WP) 10 µA Iai Analog Input Leakage V IN = VSS to VCC with all other analog inputs floating 1 10 µA ILO Output Leakage Current (SDA, V1RO, V2RO, V3RO) VOUT (Note 5) = GND to VCC. X9520 is in Standby (Note 2) 0.1 10 µA VTRIP1PR VTRIP1 Programming Range 2.75 4.70 V VTRIPxPR VTRIPx Programming Range (x = 2,3) 1.8 4.70 V VTRIP1 (Note 6) Pre - programmed VTRIP1 threshold Factory shipped default option A Factory shipped default option B 2.85 4.55 3.0 4.7 3.05 4.75 V VTRIP2 (Note 6) Pre - programmed VTRIP2 threshold Factory shipped default option A Factory shipped default option B 1.65 2.85 1.8 3.0 1.85 3.05 V VTRIP3 (Note 6) Pre - programmed VTRIP3 threshold Factory shipped default option A Factory shipped default option B 1.65 2.85 1.8 3.0 1.85 3.05 V IVx V2 Input leakage current V3 Input leakage current VSDA = VSCL = VCC Others = GND or VCC µA V IL (Note 7) Input LOW Voltage (SCL, SDA, WP, MR) -0.5 0.8 V VIH (Note 7) Input HIGH Voltage (SCL,SDA, WP, MR) 2.0 V CC +0.5 V VOLx V1RO, V2RO, V3RO, SDA Output Low Voltage ISINK = 2.0mA 0.4 V NOTES: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a STOP ending a read operation; or tWC after a STOP ending a write operation. 2. The device goes into Standby: 200ns after any STOP, except those that initiate a high voltage write cycle; tWC after a STOP that initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address Byte. 3. Current through external pull up resistor not included. VIN = Voltage applied to input pin. 5. VOUT = Voltage applied to output pin. 6. See Ordering Information Table. 7. V IL Min. and VIH Max. are for reference only and are not tested. X9520

20 FN8206.1 January 3, 2006 AC TEST CONDITIONS AC Characteristics (See Figure 27, Figure 28, Figure 29) SYMBOL PARAMETER 400kHz UNITSMIN MAX fSCL SCL Clock Frequency 0 400 kHz tIN (Note 5) Pulse width Suppression Time at inputs 50 ns tAA (Note 5) SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH (Note 5) Data Output Hold Time 50 ns tR (Note 5) SDA and SCL Rise Time 20 +.1Cb (Note 2) 300 ns tF (Note 5) SDA and SCL Fall Time 20 +.1Cb (Note 2) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb (Note 5) Capacitive load for each bus line 400 pF Input Pulse Levels 0.1VCC to 0.9VCC Input Rise and Fall Times 10ns Input and Output Timing Levels 0.5V CC Output Load See Figure 25 Nonvolatile Write Cycle Timing SYMBOL PARAMETER MIN TYP (Note 1) MAX UNITS tWC (Note 4) Nonvolatile Write Cycle Time 5 10 ms Capacitance (TA = 25°C, f = 1.0MHz, VCC = 5V) SYMBOL PARAMETER MAX UNITS TEST CONDITIONS COUT (Note 5) Output Capacitance (SDA, V1RO, V2RO, V3RO) 8 pF V OUT = 0V CIN (Note 5) Input Capacitance (SCL, WP , MR) 6 pF V IN = 0V NOTES: 1. Typical values are for TA = 25°C and VCC = 5.0V. 2. Cb = total capacitance of one bus line in pF. 3. Over recommended operating conditi ons, unless otherwise specified. 4. t WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 5. This parameter is not 100% tested. X9520

21 FN8206.1 January 3, 2006 Potentiometer Characteristics SYMBOL PARAMETER TEST CONDITIONS/NOTES LIMITS MIN TYP MAX UNITS RTOL End to End Resistance Tolerance -20 +20 % VRHx RH Terminal Voltage (x = 0,1,2) Vss V CC V VRLx RL Terminal Voltage (x = 0,1,2) Vss V CC V PR Power Rating (Note 1) (Note 6) R TOTAL = 10kΩ (DCP0, DCP1) 10 mW RTOTAL = 100kΩ (DCP2) 5 mW RW DCP Wiper Resistance I W = 1mA, VCC = 5 V, VRHx =V c c , VRLx = Vss (x = 0,1,2). 200 400 Ω IW = 1mA, VCC = 2.7 V, VRHx = Vcc, VRLx = Vss (x = 0,1,2) 400 1200 Ω IW Wiper Current (Note 6) 4.4 mA Noise R TOTAL = 10kΩ (DCP0, DCP1) mV/ √(Hz) RTOTAL = 100kΩ (DCP2) mV/ √(Hz) Absolute Linearity (Note 2) R w(n)(actual) - Rw(n)(expected) -1 +1 MI (4) Relative Linearity (Note 3) R w(n+1) - [Rw(n)+MI]- 1 + 1 M I (4) RTOTAL Temperature Coefficient R TOTAL = 10kΩ (DCP0, DCP1) ±300 ppm/°C RTOTAL = 100kΩ (DCP2) ±300 ppm/°C CH/CL/CW Potentiometer Capacitances (Note 6) See Figure 26. 10/10/25 pF twr Wiper Response time (Note 6) See Figure 34. 200 µs NOTES: 1. Power Rating between the wiper terminal R WX(n) and the end terminals RHX or RLX - for ANY tap position n, (x = 0,1,2). 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (Rwx(n)(actual) - Rwx(n)(expected)) = ±1 Ml Maximum (x = 0,1,2). 3. Relative Linearity is a measure of the error in step size between taps = R Wx(n+1) - [Rwx(n) + Ml] = ±1 Ml (x = 0,1,2) 4. 1 Ml = Minimum Increment = R TOT/(Number of taps in DCP - 1). 5. Typical values are for TA = 25°C and nominal supply voltage. 6. This parameter is periodically sampled and not 100% tested. VTRIPX (x = 1,2,3) Programming Parameters (See Figure 33) PARAMETER DESCRIPTION MIN TYP MAX UNITS tVPS VTRIPx Program Enable Voltage Setup time 10 µs tVPH VTRIPx Program Enable Voltage Hold time 10 µs tTSU VTRIPx Setup time 10 µs tTHD VTRIPx Hold (stable) time 10 µs tVPO VTRIPx Program Enable Voltage Off time (Between successive adjustments) 1 ms twc VTRIPx Write Cycle time 51 0 m s VP Programming Voltage 10 15 V Vta VTRIPx Program Voltage accuracy (Programmed at 25°C.) -100 +100 mV Vtv VTRIP Program variation after programming (-40 - 85°C). (Programmed at 25°C.) -25 +10 +25 mV NOTE: The above parameters are not 100% tested. X9520

26 FN8206.1 January 3, 2006 Appendix 1 DCP1 (100 Tap) Tap Position to Data Byte Translation Table TAP POSITION DATA BYTE DECIMAL BINARY 0 0 0000 0000 1 1 0000 0001 23 23 0001 0111 24 24 0001 1000 25 56 0011 1000 26 55 0011 0111 48 33 0010 0001 49 32 0010 0000 50 64 0100 0000 51 65 0100 0001 73 87 0101 0111 74 88 0101 1000 75 120 0111 1000 76 119 0111 0111 98 97 0110 0001 99 96 0110 0000 X9520

27 FN8206.1 January 3, 2006 Appendix 2 DCP1 (100 Tap) Tap Position to Data Byte Translation Algorithm Example. (Example 1) unsigned DCP1_TAP_Position(int tap_pos) int block; int i; int offset; int wcr_val; offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); case (2): wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val); case (3): wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); return((unsigned)01100000); X9520

28 FN8206.1 January 3, 2006 APPENDIX 2 DCP1 (100 TAP) TAP POSITION TO DATA BYTE TRANSLATION ALGORITHM EXAMPLE. (EXAMPLE 2) unsigned DCP100_TAP_Position(int tap_pos) /* optional range checking */ if (tap_pos < 0) return ((unsigned)0); /* set to min val */ else if (tap_pos >99) return ((unsigned) 96); /* set to max val */ /* 100 Tap DCP encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos); X9520

29 FN8206.1 January 3, 2006 Ball Matrix: 43 2 1 AR L 2R W 2 V c c V 2 R O B V3 RH2 V1RO V2 CW P V 3 R OR L 0 R W 0 D SCL MR RH0 RH1 E SDA RL1 RW1 Vss Package Dimensions Symbol Millimeters Inches Min Nominal Max Min Nominal Max Package Width a 2.542 2.572 2.602 Package Length b 3.812 3.842 3.872 Package Height c 0.644 0.677 0.710 Body Thickness d 0.444 0.457 0.470 Ball Height e 0.220 0.240 0.260 Ball Diameter f 0.310 0.330 0.350 Ball Pitch – Width j 0.5 Ball Pitch – Length k 0.5 Ball to Edge Spacing – Width l 0.511 0.536 0.561 Ball to Edge Spacing – Length m 0.896 0.921 0.946 9520RR YWW IA LOT # 20-Bump Chip Scale Package (CSP B20) Package Outline Drawing f j l k b a Top View (Marking Side) Botto m View (Bumped Side) Side View m e A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 E4 E3 E2 E1 Side View c e d X9520

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8206.1 January 3, 2006 Packaging Information NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V .169 (4.3) .025 (.65) BSC .252 (6.4) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) 0° - 8 ° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) ALL MEASUREMENTS ARE TYPICAL X9520

Summary

Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors January 3, 2006

Description