X9520

X9520 INTERSIL | Alldatasheet

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Technical content

FN8206.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. ©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. PRELIMINARY X9520 Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

FEATURES

• Three Digitally Controlled Potentiometers (DCPs) —64 Tap - 10k Ω —100 Tap - 10k Ω —256 Tap - 100k Ω —Nonvolatile —Write Protect Function
• 2kbit EEPROM Memory with Write Protect & Block Lock TM
• 2-Wire industry standard Serial Interface —Complies to the Gigabit Interface Converter (GBIC) specification
• Power-on Reset (POR) Circuitry —Programmable Threshold Voltage —Software Selectable reset timeout —Manual Reset
• Two Supplementary Voltage Monitors —Programmable Threshold Voltages
• Single Supply Operation —2.7V to 5.5V
• Hot Pluggable
• 20 Pin packages —CSP (Chip Scale Package) —TSSOP

DESCRIPTION

The X9520 combines three Digitally Controlled Potenti- ometers (DCPs), V1 / Vcc Power-on Reset (POR) cir- cuitry, two programmable voltage monitor inputs with software and hardware indicators, and integrated EEPROM with Block Lock™ pr otection. All functions of the X9520 are accessed by an industry standard 2-Wire serial interface. Two of the DCPs of the X9520 may be utilized to control the bias and modulation currents of the laser diode in a Fiber Optic module. The third DCP may be used to set other various reference quantities, or as a coarse trim for one of the other two DC Ps. The 2kbit integrated EEPROM may be used to store module definition data. The programmable POR circuit may be used to ensure that V1 / Vcc is stable before power is applied to the laser diode / module. The programmable voltage moni- tors may be used for monitoring various module alarm levels. The features of the X9520 are ideally suited to simplify- ing the design of fiber optic modules which comply to the Gigabit Interface Converter (GBIC) specification. The integration of these functions into one package sig- nificantly reduces board ar ea, cost and increases reli- ability of laser diode modules. BLOCK DIAGRAM DATA REGISTER COMMAND DECODE & CONTROL LOGIC SDA SCL POWER-ON / LOW VOLTAGE CONSTAT REGISTER PROTECT LOGIC EEPROM THRESHOLD RESET LOGIC GENERATION RESET VTRIP V1 / Vcc VTRIP 2kbit V1RO RH2 RW2 RL2 MR 6 - BIT NONVOLATILE MEMORY RH0 RW0 RL0 WIPER REGISTER RH1 RW1 RL1 COUNTER V2RO WP V3RO 7 - BIT NONVOLATILE MEMORY NONVOLATILE MEMORY WIPER REGISTER COUNTER WIPER REGISTER COUNTER ARRAY 8 - BIT2 VTRIP Data Sheet March 8, 2005

2 FN8206.0 March 8, 2005 DETAILED DEVICE DESCRIPTION The X9520 combines three Intersil Digitally Controlled Potentiometer (DCP) devices, V1 / Vcc power-on reset control, V1 / Vcc low voltage reset control, two supple- mentary voltage monitors, and integrated EEPROM with Block Lock™ protection, in one package. These func- tions are suited to the control, support, and monitoring of various system parameters in Fiber Channel / Gigabit Ethernet fiber optic modules, such as in Gigabit Interface Converter (GBIC) applications. The combination of the X9520 fucntionality lowers system cost, increases reli- ability, and reduces board space requirements using Intersil’s unique XBGA™ packaging. Two high resolution DCPs allow for the “set-and-forget” adjustment of Laser Driver IC parameters such as Laser Diode Bias and Modulation Currents. One lower resolu- tion DCP may be used for setting sundry system param- eters such as maximum laser output power (for eye safety requirements). Applying voltage to V CC activates the Power-on Reset circuit which allows the V1RO output to go HIGH, until the supply the supply voltage stabilizes for a period of time (selectable via softwar e). The V1RO output then goes LOW. The Low Voltage Reset circuitry allows the V1RO output to go HIGH when V CC falls below the mini- mum V CC trip point. V1RO remains HIGH until V CC returns to proper operating level. A Manual Reset (MR) input allows the user to externally trigger the V1RO out- put (HIGH). Two supplementary Voltage Monitor circuits continuously compare their inputs to individual trip voltages. If an input voltage exceeds it’s associated trip level, a hardware output (V3RO, V2RO) are allowed to go HIGH. If the input voltage becomes lower than it’s associated trip level, the corresponding output is driven LOW. A corresponding binary representation of the two monitor circuit outputs (V2RO and V3RO) are also stored in latched, volatile (CONSTAT) register bits. The status of these two monitor outputs can be read out via the 2-wire serial port. An application of the V1RO output may be to drive the “ENABLE ” input of a Laser Driver IC, with MR as a “TX_DISABLE” input. V2RO and V3RO may be used to monitor “TX_FAULT” and “RX_LOS” conditions respec- tively. Intersil’s unique circuits allow for all internal trip voltages to be individually programmed with high accuracy. This gives the designer great flexibility in changing system parameters, either at the time of manufacture, or in the field. The memory portion of the device is a CMOS serial EEPROM array with Intersil’s Block Lock™ protection. This memory may be used to store fiber optic module manufacturing data, serial numbers, or various other sys- tem parameters. The EEPROM array is internally orga- nized as x 8, and utilizes Intersil’s proprietary Direct Write™ cells, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. The device features a 2-Wire interface and software protocol allowing operation on an I 2C™ compatible serial bus. PIN CONFIGURATION RL2 RH0 V1 / Vcc SCL RW0 RL0 RW1 RH1 VSS 10 RL1 RH2 1 MR 6 RW2 2 SDA 9 V3RO 5 WP V1RO V2RO NOT TO SCALE 2 3 4 A B C D E Top View – Bumps Down CSP20 Pin TSSOP RL2RW2 RH2V2 WPV3RO SCLRH0 SDARL1 V2RO V1 / Vcc V3V1RO RW0 RL0 RH1 MR VSS RW1 X9520

3 FN8206.0 March 8, 2005 PIN ASSIGNMENT TSSOP CSP Name Function 1B 3 RH2 Connection to end of resistor array for (the 256 Tap) DCP 2. 2A 3 Rw2 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2. 3A 4 RL2 Connection to other end of resistor array for (the 256 Tap) DCP 2. 4B 4V 3 V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3 input is higher than the VTRIP3 threshold voltage, V3RO makes a transition to a HIGH level. Connect V3 to VSS when not used. 5C 3 V 3 R O V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than VTRIP3 and goes LOW when V3 is less than VTRIP3. There is no delay cir- cuitry on this pin. The V3RO pin requires the use of an external “pull-up” resistor. 6D 3 M R Manual Reset. MR is a TTL level compatible input. Pulling the MR pin active (HIGH) initiates a reset cycle to the V1RO pin (V1 / Vcc RESET Output pin). V1RO will remain HIGH for time tpurst after MR has returned to it’s normally LOW state. The reset time can be selected using bits POR1 and POR0 in the CONSTAT Register. The MR pin requires the use of an external “pull-down” resistor. 7C 4 W P Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Pro- tection is enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Al- so, when the Write Protection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations can be per- formed in the device (including the wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-down” resistor, thus if left floating the write protection feature is disabled. 8D 4 S C L Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input and output. 9E 4 S D A Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor. 10 E1 Vss Ground.

11 E3 R

L1 Connection to other end of resistor for (the 100 Tap) DCP 1. 12 E2 Rw1 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1. 13 D1 RH1 Connection to end of resistor array for (the 100 Tap) DCP 1. 14 D2 RH0 Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0. 15 C1 RW0 Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0. 16 C2 RL0 Connection to the other end of resistor array for (the 64 Tap) DCP 0.

17 B1 V2

V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2 input is greater than the VTRIP2 threshold voltage, V2RO makes a transition to a HIGH level. Connect V2 to VSS when not used.

18 A1 V2RO

V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than VTRIP2, and goes LOW when V2 is less than VTRIP2. There is no power-up reset delay circuitry on this pin. The V2RO pin requires the use of an external “pull-up” re- sistor.

19 B2 V1RO

V1 / Vcc RESET Output. This is an active HIGH, open drain output which becomes active whenever V1 / Vcc falls below VTRIP1. V1RO becomes active on power-up and remains active for a time tpurst after the power supply stabilizes (tpurst can be changed by varying the POR0 and POR1 bits of the internal control register). The V1RO pin requires the use of an external “pull-up” resistor. The V1RO pin can be forced active (HIGH) using the manual reset (MR) input pin. 20 A2 V1 / Vcc Supply Voltage. X9520

condition to place the device into a known state. of these individual parts, a 1, 2 or 3 Byte protocol is used. significant four bits of the Slave Address (SA7 - SA4). in order to select the X9520. Figure 3. Acknowledge Response From Receiver

000 EEPROM Array

010 CONSTAT Register

111 DCP

1 READ

Figure 4. Slave Address Format

the DCP using a nonvolatile write operation. three byte command sequence shown in Figure 9. been issued on SDA (See Figure 34). upon which DCP is being addressed (see Table below).

1. The mapping of the Data Byte to “wiper position” data

Byte (binary) for DCP1, is given in “APPENDIX 2” .

0 Select a Volatile Write operation to be performed

1 Select a Nonvolatile Write operation to be per-

†This bit has no effect when a Read operation is being performed. Figure 8. Instruction Byte Format Figure 9. DCP Write Command Sequence

11 R e s e r v e d

ACKNOWLEDGE, and awaits the next eight bits of data. ACKNOWLEDGE bit after the Address Byte. previous data, one byte at a time (See Figure 13). EDGE, and data transfer sequence. and receiving the subsequent ACKNOWLEDGE signal. contents of the EEPROM array does not change. Figure 12. EEPROM Page Write Operation

the “wiper position” of the DCPs cannot be changed - i.e. period of time, tPURST (See Figure 30). The default for these bits are POR1 = 0, POR0 = 1. Voltage Monitor reset output pins V2RO and V3RO. sponding VxRO output is HIGH. —The corresponding VxRO output becomes LOW.

01 N O

10 N O

11 N O

Figure 18. CONSTAT Register Write Command Sequence

ter requires an Address Byte which must be set to FFh. by a START and ended with a STOP). ister Write Enable Latch (RWEL) AND the WEL bit. PUV1RO) control bits (POR1 - POR0). of the nonvolatile bits in the CONSTAT Register to “0”. any time by performing a random read (See Figure 19). to be consistent with the bus protocol. Figure 19. CONSTAT Register Read Command Sequence

requires setting of the WEL bit in the CONSTAT register. rated in the form of the Write Protection pin. disables nonvolatile write operations to the X9520. write permission status of the device. V1RO pin is driven to a LOW state. See Figure 30. ing a push-button directly from V1 / Vcc to the MR pin.

0 Volts

Figure 20. Manual Reset Response

0 NO NO Not in locked region YES YES

“1” after system initilization). “1” after system initilization). to be stored is higher or lower than the present value. Figure 22. Setting V TRIPx to a higher level (x=1,2,3). Figure 21. Voltage Monitor Response

increase the accuracy of the threshold voltage. value of the calculated error. Figure 24. V TRIPx Setting / Reset Sequence (x=1,2,3)

Figure 30. Power-Up and Power-Down Timing Figure 31. Manual Reset Timing Diagram Figure 32. V2, V3 Timing Diagram

24 FN8206.0 March 8, 2005 D.C. OPERATING CHARACTERISTICS Notes: 1. The device enters the Active state after any START, an d remains active until: 9 clock cy cles later if the Device Sele ct Bits in the Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or tWC after a STOP ending a write operation. Notes: 2. The device goes into Standby: 200nS after any STOP, ex cept those that initiate a high voltage write cycle; t WC after a STOP that ini- tiates a high voltage cycle; or 9 clock cycles after any START that is not follow ed by the correct Device Select Bits in the Sl ave Address Byte. Notes: 3. Current through external pull up resistor not included. Notes: 4. VIN = Voltage applied to input pin. Notes: 5. VOUT = Voltage applied to output pin. Notes: 6. See “ORDERING INFORMATION” on page 33. Notes: 7. V IL Min. and VIH Max. are for reference only and are not tested Symbol Parameter Min Typ Max Unit Test Conditions / Notes ICC1(1) Current into VCC Pin (X9520: Active) Read memory array (3) Write nonvolatile memory 0.4 1.5 mA fSCL = 400kHz ICC2(2) Current into VCC Pin (X9520:Standby) With 2-Wire bus activity (3) No 2-Wire bus activity µA VSDA = VCC MR = Vss WP = Vss or Open/Floating VSCL= VCC (when no bus activity else fSCL = 400kHz) ILI Input Leakage Current (SCL, SDA, MR) 0.1 10 µA VIN (4) = GND to VCC. Input Leakage Current (WP) 10 µA Iai Analog Input Leakage 1 10 µA VIN = VSS to VCC with all other analog inputs floating ILO Output Leakage Current (SDA, V1RO, V2RO, V3RO) 0.1 10 µA VOUT (5) = GND to VCC. X9520 is in Standby(2) VTRIP1PR VTRIP1 Programming Range 2.75 4.70 V VTRIPxPR VTRIPx Programming Range (x=2,3) 1.8 4.70 V VTRIP1 (6) Pre - programmed VTRIP1 threshold 2.85 4.55 3.0 4.7 3.05

4.75 V Factory shipped default option A

Factory shipped default option B VTRIP2 (6) Pre - programmed VTRIP2 threshold 1.65 2.85 1.8 3.0 1.85

3.05 V Factory shipped default option A

Factory shipped default option B VTRIP3 (6) Pre - programmed VTRIP3 threshold 1.65 2.85 1.8 3.0 1.85 Factory shipped default option B IVx V2 Input leakage current V3 Input leakage current 1 µA VSDA = VSCL = VCC Others=GND or VCC VIL (7) Input LOW Voltage (SCL, SDA, WP, MR) -0.5 0.8 V VIH (7) Input HIGH Voltage (SCL,SDA, WP, MR) 2.0 VCC +0.5 V VOLx V1RO, V2RO, V3RO, SDA Output Low Voltage 0.4 V ISINK = 2.0mA X9520

25 FN8206.0 March 8, 2005 A.C. CHARACTERISTICS (See Figure 27, Figure 28, Figure 29) A.C. TEST CONDITIONS NONVOLATILE WRITE CYCLE TIMING CAPACITANCE (TA = 25°C, F = 1.0 MHZ, VCC = 5V) Notes: 1. Typical values are for TA = 25°C and VCC = 5.0V Notes: 2. Cb = total capacitance of one bus line in pF. Notes: 3. Over recommended operating c onditions, unless otherwise specified Notes: 4. t WC is the time from a valid STOP condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Notes: 5. This parameter is not 100% tested. Symbol Parameter 400kHz Min Max Units fSCL SCL Clock Frequency 0 400 kHz tIN (5) Pulse width Suppression Time at inputs 50 ns tAA (5) SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH (5) Data Output Hold Time 50 ns tR (5) SDA and SCL Rise Time 20 +.1Cb (2) 300 ns tF (5) SDA and SCL Fall Time 20 +.1Cb (2) 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb (5) Capacitive load for each bus line 400 pF Input Pulse Levels 0.1VCC to 0.9VCC Input Rise and Fall Times 10ns Input and Output Timing Levels 0.5VCC Output Load See Figure 25 Symbol Parameter Min. Typ.(1) Max. Units tWC(4) Nonvolatile Write Cycle Time 5 10 ms Symbol Parameter Max Units Test Conditions COUT (5) Output Capacitance (SDA, V1RO, V2RO, V3RO) 8 pF VOUT = 0V CIN (5) Input Capacitance (SCL, WP, MR) 6 pF VIN = 0V X9520

26 FN8206.0 March 8, 2005 POTENTIOMETER CHARACTERISTICS Notes: 1. Power Rating between the wiper terminal RWX(n) and the end terminals RHX or RLX - for ANY tap position n, (x = 0,1,2). Notes: 2. Absolute Linearity is utilized to determine ac tual wiper resistance versus, expected resistance = (Rwx(n)(actual) - Rwx(n)(expected)) = ±1 Ml Maximum (x = 0,1,2). Notes: 3. Relative Linearity is a measure of the error in step size between taps = RWx(n+1) - [Rwx(n) + Ml] = ±1 Ml (x = 0,1,2) Notes: 4. 1 Ml = Minimum Increment = RTOT / (Number of taps in DCP - 1). Notes: 5. Typical values are for T A = 25°C and nominal supply voltage. Notes: 6. This parameter is periodically sampled and not 100% tested. Symbol Parameter Limits Test Conditions/NotesMin. Typ. Max. Units RTOL End to End Resistance Tolerance -20 +20 % VRHx RH Terminal Voltage (x = 0,1,2) Vss VCC V VRLx RL Terminal Voltage (x = 0,1,2) Vss VCC V PR Power Rating (1)(6) 10 mW RTOTAL = 10kΩ (DCP0, DCP1) 5m W RTOTAL = 100kΩ (DCP2) RW DCP Wiper Resistance 200 400 Ω IW = 1mA, VCC = 5 V, VRHx = Vcc, VRLx = Vss (x = 0,1,2). 400 1200 Ω IW = 1mA, VCC = 2.7 V, VRHx = Vcc, VRLx = Vss (x = 0,1,2) IW Wiper Current (6) 4.4 mA Noise mV/ sqt(Hz) RTOTAL = 10kΩ (DCP0, DCP1) mV/ sqt(Hz) RTOTAL = 100kΩ (DCP2) Absolute Linearity (2) -1 +1 MI(4) Rw(n)(actual) - Rw(n)(expected) Relative Linearity (3) -1 +1 MI(4) Rw(n+1) - [Rw(n)+MI] RTOTAL Temperature Coefficient ±300 ppm/°C RTOTAL = 10kΩ (DCP0, DCP1) ±300 ppm/°C RTOTAL = 100kΩ (DCP2) CH/CL/CW Potentiometer Capacitances (6) 10/10/25 pF See Figure 26. twr Wiper Response time (6) 200 µs See Figure 34. X9520

27 FN8206.0 March 8, 2005 VTRIPX (X=1,2,3) PROGRAMMING PARAMETERS (See Figure 33) Notes: The above parameters are not 100% tested. V1RO, V2RO, V3RO OUTPUT TIMING. (See Figure 30, Figure 31, Figure 32) Notes: 1. See Figure 31 for timing diagram. Notes: 2. See Figure 25 for equivalent load. Notes: 3. This parameter describes the lowest possible V1 / Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with respect to their inputs (V1 / Vcc, V2, V3). Notes: 4. From MR rising edge crossing V IH, to V1RO rising edge crossing VOH. Notes: 5. The above parameters are not 100% tested. Parameter Description Min Typ Max Units tVPS VTRIPx Program Enable Voltage Setup time 10 µs tVPH VTRIPx Program Enable Voltage Hold time 10 µs tTSU VTRIPx Setup time 10 µs tTHD VTRIPx Hold (stable) time 10 µs tVPO VTRIPx Program Enable Voltage Off time (Between successive adjustments) 1m s twc VTRIPx Write Cycle time 51 0 m s VP Programming Voltage 10 15 V Vta VTRIPx Program Voltage accuracy (Programmed at 25oC.) -100 +100 mV Vtv VTRIP Program variation after programming (-40 - 85oC). (Programmed at 25oC.) -25 +10 +25 mV Symbol Description Condition Min. Typ. Max. Units tPURST (5) Power On Reset delay time POR1 = 0, POR0 = 0 25 50 75 ms POR1 = 0, POR0 = 1 50 100 150 ms POR1 = 1, POR0 = 0 100 200 300 ms POR1 = 1, POR0 = 1 150 300 450 ms t MRD (31)(2)(5) MR to V1RO propagation delay See (1)(2)(4) 5 µs tMRDPW(5) MR pulse width 500 ns tRPDx (5) V1 / Vcc, V2, V3 to V1RO, V2RO, V3RO propagation delay (respectively) 20 µs t Fx (5) V1 / Vcc, V2, V3 Fall Time 20 mV/ µs tRx (5) V1 / Vcc, V2, V3 Rise Time 20 mV/ µs VRVALID (5) V1 / Vcc for V1RO, V2RO, V3RO Valid (3). 1V X9520

28 FN8206.0 March 8, 2005 APPENDIX 1 DCP1 (100 Tap) Tap position to Data Byte translation Table Tap Position Data Byte Decimal Binary 0 0 0000 0000 1 1 0000 0001 23 23 0001 0111 24 24 0001 1000 25 56 0011 1000 26 55 0011 0111 48 33 0010 0001 49 32 0010 0000 50 64 0100 0000 51 65 0100 0001 73 87 0101 0111 74 88 0101 1000 75 120 0111 1000 76 119 0111 0111 98 97 0110 0001 99 96 0110 0000 X9520

29 FN8206.0 March 8, 2005 APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1) unsigned DCP1_TAP_Position(int tap_pos) int block; int i; int offset; int wcr_val; offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); else if (block <= 3) { switch(block) { case (0): return ((unsigned)tap_pos) ; case (1): wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); case (2): wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val); case (3): wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); return((unsigned)01100000); X9520

30 FN8206.0 March 8, 2005 APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2) unsigned DCP100_TAP_Position(int tap_pos) /* optional range checking */ if (tap_pos < 0) return ((unsigned)0); /* set to min val */ else if (tap_pos >99) return ((unsigned) 96); /* set to max val */ /* 100 Tap DCP encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos); X9520

31 FN8206.0 March 8, 2005 Ball Matrix: 43 2 1 A RL2 RW2 Vcc V2RO B V3 RH2 V1RO V2 C WP V3RO RL0 RW0 D SCL MR RH0 RH1 E SDA RL1 RW1 Vss Package Dimensions Symbol Millimeters Inches Min Nominal Max Min Nominal Max Package Width a 2.542 2.572 2.602 Package Length b 3.812 3.842 3.872 Package Height c 0.644 0.677 0.710 Body Thickness d 0.444 0.457 0.470 Ball Height e 0.220 0.240 0.260 Ball Diameter f 0.310 0.330 0.350 Ball Pitch – Width j 0.5 Ball Pitch – Length k 0.5 Ball to Edge Spacing – Width l 0.511 0.536 0.561 Ball to Edge Spacing – Length m 0.896 0.921 0.946 9520RR YWW IA LOT # 20-Bump Chip Scale Package (CSP B20) Package Outline Drawing f j l k b a Top View (Marking Side) Botto m View (Bumped Side) Side View m e A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 E4 E3 E2 E1 Side View c e d X9520

32 FN8206.0 March 8, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V .169 (4.3) .025 (.65) BSC .252 (6.4) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) 0° - 8 ° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) ALL MEASUREMENTS ARE TYPICAL X9520

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8206.0 March 8, 2005

ORDERING INFORMATION

† For details of preset threshold values, See "D.C. OPERATING CHARACTERISTICS" Preset (Factory Shipped) VTRIPx Threshold Levels (x=1,2,3) A = Optimized for 3.3 V system monitoring † B = Optimized for 5 V system monitoring † Temperature Range I = Industrial -40°C to +85°C Package V20 = 20-Lead TSSOP B20 = 20-Lead CSP X9520