X9408WS24-2.7

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Document overview

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• PDF pages: 20

Technical content

Features

• Four Potentiometers in One Package
• 64 Resistor Taps per Potentiometer
• 2-wire Serial Interface
• Wiper Resistance, 40 Typical at 5V
• Four Nonvolatile Data Registers for Each Pot
• Nonvolatile Storage of Wiper Position
• Standby Current < 1µA max (Total Package) CC = 2.7V to 5.5V Operation V+ = 2.7V to 5.5V V- = -2.7V to -5.5V
• 1 0 k, 2.5k End to End Resistances
• High reliability
• Endurance–100,000 Data Changes Per Bit Per Register
• Register Data Retention–100 years
• 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP Packages
• Pb-Free (RoHS Compliant) Block Diagram INTERFACE AND CONTROL CIRCUITRY SCL SDA R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 1 VH1/RH1 VL1/RL1 R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) VH0/RH0 VL0/RL0 DATA VW0/RW0 VW1/RW1 R0 R1 R2 R3 RESISTOR ARRAY VH2/RH2 VL2/RL2 VW2/RW2 R0 R1 R2 R3 RESISTOR ARRAY VH3/RH3 VL3/RL3 VW3/RW3 WIPER COUNTER REGISTER (WCR) WIPER COUNTER REGISTER (WCR) POT 3 POT 2 WP POT 0VCC VSS

FN8191 Rev.4.00 Page 2 of 20 January 15, 2009

Ordering Information

PART NUMBER PART MARKING V CC LIMITS (V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (°C) PACKAGE X9408YS24* X9408YS 5 ±10% 2.5 0 to +70 24 Ld SOIC (300 mil) X9408YS24I* X9408YS I -40 to +85 24 Ld SOIC (300 mil) X9408YV24* X9408YV 0 to +70 24 Ld TSSOP (4.4mm) X9408YV24Z* (Note) X9408YV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-Free ) X9408YV24I* X9408YV I -40 to +85 24 Ld TSSOP (4.4mm) X9408YV24IZ* (Note) X9408YV Z I -40 to +85 24 Ld TSSOP (4.4mm) (Pb -Free) X9408WS24* X9408WS 10 0 to +70 24 Ld SOIC (300 mil) X9408WS24I* X9408WS I -40 to +85 24 Ld SOIC (300 mil) X9408WV24* X9408WV 0 to +70 24 Ld TSSOP (4.4mm) X9408WV24Z* (Note) X9408WV Z 0 to +70 24 Ld TSSOP (4.4mm) (Pb-Free ) X9408WV24I* X9408WV I -40 to +85 24 Ld TSSOP (4.4mm) X9408WV24IZ* (Note) X9408WV Z I -40 to +85 24 Ld TSSOP (4.4mm) (Pb -Free) X9408YS24-2.7* X9408YS F 2.7 to 5.5 2.5 0 to +70 24 Ld SOIC (300 mil ) X9408YS24I-2.7* X9408YS G -40 to +85 24 Ld SOIC (300 mil) X9408YV24-2.7* X9408YV F 0 to +70 24 Ld TSSOP (4.4mm) X9408YV24Z-2.7* (Note) X9408YV Z F 0 to +70 24 Ld TSSOP (4.4mm) (P b-Free) X9408YV24I-2.7* X9408YV G -40 to +85 24 Ld TSSOP (4.4mm) X9408YV24IZ-2.7T1 (Note) X9408YV Z G -40 to +85 24 Ld TSSOP (4.4mm ) Tape and Reel (Pb-Free) X9408WS24-2.7* X9408WS F 10 0 to +70 24 Ld SOIC (300 mil) X9408WS24I-2.7* X9408WS G -40 to +85 24 Ld SOIC (300 mil) X9408WS24IZ-2.7* (Note) X9408WS Z G -40 to +85 24 Ld SOIC (300 mil ) (Pb-Free) X9408WV24-2.7* X9408WV F 0 to +70 24 Ld TSSOP (4.4mm) X9408WV24Z-2.7* (Note) X9408WV Z F 0 to +70 24 Ld TSSOP (4.4mm) (P b-Free) X9408WV24I-2.7* X9408WV G -40 to +85 24 Ld TSSOP (4.4mm) X9408WV24IZ-2.7* (Note) X9408WV Z G -40 to +85 24 Ld TSSOP (4.4mm) (Pb-Free) *Add "T1" suffix for tape and reel. **Add "T1" suffix for tape and reel.Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8191 Rev.4.00 Page 3 of 20 January 15, 2009 Pin Descriptions Host Interface Pins SERIAL CLOCK (SCL) The SCL input is used to clock data into and out of the X9408. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. DEVICE ADDRESS (A0 - A3) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9408. A maximum of 16 devices may occupy the 2-wire serial bus. Potentiometer Pins VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0 – VW3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. ANALOG SUPPLIES V+, V- The Analog Supplies V+, V- are the supply voltages for the XDCP analog section. Pin Assignments Pinouts X9408 (24 LD DIP/SOIC) TOP VIEW X9408 (24 LD TSSOP) TOP VIEW SYMBOL DESCRIPTION SCL Serial Clock SDA Serial Data A0-A3 Device Address V H0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 Potentiometer Pins (terminal equivalent) VW0/RW0 - VW3/RW3 Potentiometer Pins (wiper equivalent) WP Hardware Write Protection V+,V- Analog Supplies V CC System Supply Voltage VSS System Ground NC No Connection VCC VL0/RL0 VH0/RH0 VW0/RW0 WP SDA VL1/RL1 VH1/RH1 VW1/RW1 VSS VH3/RH3 VW3/R/RH1 NC SCL VH2/RH2 VW2/RW2 VL3/RL3 VL2/RL2 SDA VL1/RL1 VH1/RH1 VW1/RW1 VSS VW2/RW2 VH2/RH2 VL2/RL2 SCL WP VW0/RW0 VH0/RH0 VL0/RL0 VCC VL3/RL3 VW3/RW3 NC VH3/RH3

between the host and the XDCP potentiometers. reserved for indicating start and stop conditions. command until this condition is met. which is a LOW to HIGH transition of SDA while SCL is HIGH. select, and enable, one of sixty-four switches. can be read and written by the host system. below). For the X9408 this is fixed as 0101[B]. The next four bits of the slave address are the device address. bits is required for the X9408 to respond with an acknowledge. signals or tied to VCC or VSS. master can then proceed with the next operation.

100 A3 A2 A1 A0

FIGURE 1. SLAVE ADDRESS

registers. The format is shown in Figure 2. be affected by the instruction. Figure 3. These two-byte instructions exchange data between potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. directly between the host and the Wiper Counter Register. operations is shown in Figure 4. FIGURE 2. INSTRUCTION BYTE FORMAT

0101 A 3 A 2 A 1 A 0

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE

wiper will move one resistor segment towards the RL terminal. operation are shown in Figures 5 and 6 respectively. TABLE 1. INSTRUCTION SET

1 R0 P1 P0 Transfer the contents of the Data Register pointed to by P1 - P0

1110 R 1 R0 P1 P0 Transfer the contents of the Wiper Counter Register pointed to by

0001 R 1 R0 0 0 Transfer the contents of the Data Registers pointed to by R 1 - R0

1000 R 1 R0 0 0 Transfer the contents of both Wiper Counter Registers to thei r

FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE

its data register zero (DR0) upon power-up. automatically moved to the wiper counter register on power-up. FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM TABLE 2. DATE REGISTERS, (6-BIT), NONVOLATILE

directly. The contents of the WCR can be saved in a DR.

1. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
2. “A3 ~ A0”: stands for the device addresses sent by the master.
3. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
4. “I”: stands for the increment operation, SDA held high during active
5. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

TABLE 3. WIPER COUNTER REGISTER, (6-BIT), VOLATILE

0101 A 3 A 2 A 1 A 0 1 1 0 1 R 1R 0P 1P 0

FN8191 Rev.4.00 Page 10 of 20 January 15, 2009 Write Wiper Counter Register (WCR) to Data Register (DR) Increment/Decrement Wiper Counter Register (WCR) Global XFR Data Register (DR) to Wiper Counter Register (WCR) Global XFR Wiper Counter Register (WCR) to Data Register (DR) Symbol Table Guidelines for Calculating Typical Values of Bus Pull-Up Resistors S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE DR AND WCR ADDRESSES S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 A3 A2 A1 A0 1 1 1 0 R1 R0 P1 P0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE WCR ADDRESSES S A C K INCREMENT/DECREMENT (SENT BY MASTER ON SDA) S T O P 0101 A 3 A 2 A 1 A 0 0 0 1 000 P 1 P 0 I / D I / D . . . . I / D I / D S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE DR ADDRESSES S A C K S T O P 0 1 0 1 A 3A 2A 1A 0 0 0 0 1 R 1R 0 0 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE DR ADDRESSES S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 A 3A 2A 1A 0 1 0 0 0 R 1R 0 0 0 WAVEFORM INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM LO W TO HIGH WILL CHANGE FROM LOW TO HIGH MAY CHANGE FROM HIGH TO LOW WILL CHANGE FROM HIGH TO LOW DON’T CARE: CHANGES ALLO WED CHANGING: STATE NOT KNO WN N/A CENTER LINE IS HIGH IMPEDANCE 120 100 20 40 60 80 100 120 RESISTANCE () BUS CAPACITANCE (pF) Min. Resistance MAX. RESISTANCE RMAX = CBUS tR RMIN = IOL MIN VCC MAX =1.8k

FN8191 Rev.4.00 Page 11 of 20 January 15, 2009 Absolute Maximum Ratings Thermal Information Supply Voltage (VCC Limits) Voltage on SDA, SCL any address input http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications (Over recommended operating conditions unless otherwise stated.) SYMBOL PARAMETER TEST CONDITION LIMITS MIN (Note 6) TYP (Note 4) MAX (Note 6) UNIT RTOTAL End to end resistance tolerance -20 +20 % Power rating +25°C, each pot 50 mW RW Wiper resistance I W = (VH - VL)/RTOTAL @ V+, V- = ±3V 150 250  IW = (VH - VL)/RTOTAL @ V+, V- = ±5V 40 100  VV+ Voltage on V+ pin X9408 +4.5 +5.5 V VV- Voltage on V- pin X9408 -5.5 -4.5 V VTERM Voltage on any VH/RH, VL/RL or VW/RW pin V- V+ V Noise Ref: 1kHz -120 dBV Resolution (Note 4) 1.6 % Absolute linearity (Note 1) V(V wn/Rwn)(actual) - V(Vwn/Rwn)(expected) (Note 4) -1 +1 MI (Note 3) Relative linearity (Note 2) V(V w(n+1)/Rw(n+1)) - [V(Vw(n)/Rw(n)) + MI] (Note 4) -0.2 +0.2 MI (Note 3) Temperature coefficient of RTOTAL (Note 4) 300 ppm/°C Ratiometric Temperature Coefficient (Note 4) 20 ppm/°C CH/CL/CW Potentiometer Capacitances See Macro model 10/10/25 pF IAL VH/RH, VL/RL, VW/RW Leakage Current VIN = V- to V+. Device is in Stand- by mode. 0.1 10 µA

FN8191 Rev.4.00 Page 12 of 20 January 15, 2009 NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = RTOT/63 or [V(VH/RH) - V(VL/RL)]/63, single pot ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING NOTES: 4. Limits should be considered typical and are not production tested. 5. tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN (Note 6) TYP (Note 4) MAX (Note 6) UNIT ICC1 VCC supply current (nonvolatile write) f SCL = 400kHz, SDA = Open, Other Inputs = VSS 5m A ICC2 VCC supply current (move wiper, write, read) fSCL = 400kHz, SDA = Open, Other Inputs = VSS 250 µA ISB VCC current (standby) SCL = SDA = V CC, Addr. = VSS 3µ A ILI Input leakage current 10 µA ILO Output leakage current 10 µA VIH Input HIGH voltage V CC x 0.7 V CC +0.5 V VIL Input LOW voltage –0.5 V CC x 0.1 V VOL Output LOW voltage I OL = 3mA 0.4 V PARAMETER MIN UNIT Minimum endurance 100,000 Data changes per bit per register Data retention 100 years SYMBOL TEST TEST CONDITION TYP (Note 4) UNIT CI/O (Note 4) Input/output capacitance (SDA) V I/O = 0V 8 pF CIN (Note 4) Input capacitance (A0, A1, A2, A3, and SCL) V IN = 0V 6 pF SYMBOL PARAMETER MIN (Note 6) MAX (Note 6) UNIT tPUR (Note 5) Power-up to initiation of read operation 1 ms tPUW (Note 5) Power-up to initiation of write operation 5 ms tRVCC (Note 6) V CC Power-up Ramp 0.2 50 V/msec

FN8191 Rev.4.00 Page 13 of 20 January 15, 2009 Power-up Requirements (Power-up sequencing can affect correct recall of the wiper registers). The preferred power-on sequence is as follows: First V-, then VCC and V+, and then the potentiometer pins, VH/RH, VL/RL, and VW/RW. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC ramp rate specification should be met, and any glitches or slope changes in the V CC line should be held to <100mV if possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until VCC, V+ and V- reach their final value. A.C. Test Conditions Equivalent A.C. Load Circuit Circuit #3 SPICE Macro Model Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 1533 100PF SDA OUTPUT 10pF VH/RH RTOTAL CH 25pF CW CL 10pF VW/RW VL/RL

FN8191 Rev.4.00 Page 14 of 20 January 15, 2009 AC Timing (Over recommended operating condition) HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL PARAMETER MIN (Note 5) MAX (Note 5) UNIT fSCL Clock frequency 400 kHz tCYC Clock cycle time 2500 ns tHIGH Clock high time 600 ns tLOW Clock low time 1300 ns tSU:STA Start setup time 600 ns tHD:STA Start hold time 600 ns tSU:STO Stop setup time 600 ns tSU:DAT SDA data input setup time 100 ns tHD:DAT SDA data input hold time 30 ns tR (Note 7) SCL and SDA rise time 300 ns tF (Note 7) SCL and SDA fall time 300 ns tAA SCL low to SDA data output valid time 900 ns tDH SDA Data output hold time 50 ns TI Noise suppression time constant at SCL and SDA inputs 50 ns tBUF Bus free time (prior to any transmission) 1300 ns tSU:WPA WP, A0, A1, A2 and A3 setup time 0 ns tHD:WPA WP, A0, A1, A2 and A3 hold time 0n s NOTES: 7. This parameter is not production tested. Parameter established by characterization. SYMBOL PARAMETER TYP. (Note 4) MAX. (Note 6) UNIT tWR High-voltage write cycle time (store instructions) 5 10 ms SYMBOL PARAMETER MIN. (Note 5) MAX. (Note 6) UNIT tWRPO Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs

FN8191 Rev.4.00 Page 15 of 20 January 15, 2009 Timing Diagrams Start and Stop Timing g Input Timing Output Timing XDCP Timing (for All Load Instructions) tSU:STA tHD:STA tSU:STO SCL SDA tR (START) (STOP) tF tR tF SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA SCL SDA VWx (STOP) LSB tWRL

FN8191 Rev.4.00 Page 16 of 20 January 15, 2009 XDCP Timing (for Increment/Decrement Instruction) Write Protect and Device Address Pins Timing Applications information Basic Configurations of Electronic Potentiometers SCL SDA VWx tWRID WIPER REGISTER ADDRESS INC/DEC INC/DEC SDA SCL ... ... ... WP A0, A1 A2, A3 tSU:WPA tHD:WPA (START) (STOP) (ANY INSTRUCTION) VR +VR I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT

FN8191 Rev.4.00 Page 17 of 20 January 15, 2009 Application Circuits NONINVERTING AMPLIFIER VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 100k 10k10k 10k -12V+12V TL072 –VS VO R2R1

FN8191 Rev.4.00 Page 18 of 20 January 15, 2009 Application Circuits (continued) INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS FUNCTION GENERATOR VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB FREQUENCY µR1, R2, C AMPLITUDE µRA, RB C ATTENUATOR FILTER VS VO VO = G VS -1/2  G  +1/2 GO = 1 + R2/R1 fc = 1/(2RC) R4 All RS = 10k VS R C VO

FN8191 Rev.4.00 Page 19 of 20 January 15, 2009 Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E

0.25 CABM

H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW

0.10 CABMb

c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL MILLIMETERS TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.

FN8191 Rev.4.00 Page 20 of 20 January 15, 2009 X9408 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2009. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 4 2 4 7  0° 8° 0° 8° - Rev. 1 4/06