X9408

X9408 INTERSIL | Alldatasheet

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Technical content

Low Noise/Low Power/2-Wire Bus Quad Digitally Controlled (XDCP™) Potentiometers

FEATURES

• Four potentiometers in one package
• 64 resistor taps per potentiometer
• 2-wire serial interface
• Wiper resistance, 40Ω typical at 5V
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 1µA max (total package) CC = 2.7V to 5.5V operation V+ = 2.7V to 5.5V V- = –2.7V to -5.5V
• 1 0 kΩ, 2.5kΩ end to end resistances
• High reliability —Endurance–100,000 data changes per bit per register —Register data retention–100 years
• 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP packages
• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9408 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Poweru p recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM Interface and Control Circuitry SCL SDA R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 1 VH1/RH1 VL1/RL1 R0 R1 R2 R3 Wiper Counter Register (WCR) VH0/RH0 VL0/RL0 Data VW0/RW0 VW1/RW1 R0 R1 R2 R3 Resistor Array VH2/RH2 VL2/RL2 VW2/RW2 R0 R1 R2 R3 Resistor Array VH3/RH3 VL3/RL3 VW3/RW3 Wiper Counter Register (WCR) Wiper Counter Register (WCR) Pot 3 Pot 2 WP Pot 0VCC VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Data Sheet FN8191.2 September 19, 2005

2 FN8191.2 September 19, 2005

Ordering Information

PART NUMBER PART MARKING V CC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE X9408YP24 5 ±10% 2.5 0 to 70 24 Ld PDIP X9408YS24* 0 to 70 24 Ld SOIC (300 mil) X9408YS24I* -40 to 85 24 Ld SOIC (300 mil) X9408YV24* X9408YV 0 to 70 24 Ld TSSOP (4.4mm) X9408YV24Z* (Note) X9408YV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9408YV24I* X9408YV I -40 to 85 24 Ld TSSOP (4.4mm) X9408YV24IZ* (Note) X9408YV Z I -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) X9408WP24 10 0 to 70 24 Ld PDIP X9408WP24I -40 to 85 24 Ld PDIP X9408WS24* X9408WS 0 to 70 24 Ld SOIC (300 mil) X9408WS24I* X9408WS I -40 to 85 24 Ld SOIC (300 mil) X9408WV24* X9408WV 0 to 70 24 Ld TSSOP (4.4mm) X9408WV24Z* (Note) X9408WV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9408WV24I* X9408WV I -40 to 85 24 Ld TSSOP (4.4mm) X9408WV24IZ* (Note) X9408WV Z I -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) X9408YP24I-2.7 2.7 to 5.5 2.5 -40 to 85 24 Ld PDIP X9408YS24-2.7* 0 to 70 24 Ld SOIC (300 mil) X9408YS24I-2.7* -40 to 85 24 Ld SOIC (300 mil) X9408YV24-2.7* X9408YV F 0 to 70 24 Ld TSSOP (4.4mm) X9408YV24Z-2.7* (Note) X9408YV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9408YV24I-2.7* X9408YV G -40 to 85 24 Ld TSSOP (4.4mm) X9408YV24IZ-2.7T1 (Note) X9408YV Z G -40 to 85 24 Ld TSSOP (4.4mm) Tape and Reel (Pb-free) X9408WP24-2.7 10 0 to 70 24 Ld PDIP X9408WP24I-2.7 -40 to 85 24 Ld PDIP X9408WS24-2.7* X9408WS F 0 to 70 24 Ld SOIC (300 mil) X9408WS24I-2.7* X9408WS G -40 to 85 24 Ld SOIC (300 mil) X9408WSI-2.7 -40 to 85 24 Ld SOIC (300 mil) X9408WV24-2.7* X9408WV F 0 to 70 24 Ld TSSOP (4.4mm) X9408WV24Z-2.7* (Note) X9408WV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9408WV24I-2.7* X9408WV G -40 to 85 24 Ld TSSOP (4.4mm) X9408WV24IZ-2.7* (Note) X9408WV Z G -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products em ploy special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. X9408

3 FN8191.2 September 19, 2005 PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9408. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Device Address (A 0 - A3) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9408. A maximum of 16 devices may occupy the 2-wire serial bus. Potentiometer Pins V H/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3) The V H/RH and V L/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. V W/RW (VW0/RW0 – VW3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. Analog Supplies V+, V- The Analog Supplies V+, V- are the supply voltages for the XDCP analog section. PIN NAMES PIN CONFIGURATION Symbol Description SCL Serial Clock SDA Serial Data A0-A3 Device Address V H0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 Potentiometer Pins (terminal equivalent) VW0/RW0 - VW3/RW3 Potentiometer Pins (wiper equivalent) WP Hardware Write Protection V+,V- Analog Supplies VCC System Supply Voltage VSS System Ground NC No Connection VCC VL0/RL0 VH0/RH0 WP SDA V L3/RL3 VH3/RH3 VW3/RW3 NC A SCL V L2/RL2 VH2/RH2 DIP/SOIC X9408 VSS VW0/RW0 VL1/RL1 VH1/RH1 VW1/RW1 VW2/RW2 SDA VH2/RH2 WP VW0/RW0 VCC VL3/RL3 VH3/RH3 VW3/RW3 TSSOP X9408 VW2/RW2 12A3 VL1/RL1 VH1/RH1 VW1/RW1 NC VH0/RH0 SCL VL2/RL2 VL0/RL0 VSS X9408

slave device in all applications. byte the X9408 will respond with a final acknowledge. Figure 1. Slave Address signals or tied to VCC or VSS.

100 A3 A2 A1 A0

Figure 3. Two-Byte Instruction Sequence move one resistor segment towards the R H terminal. Figures 5 and 6 respectively. Table 1. Instruction Set

0101 A 3 A 2 A 1 A 0

1 P0 Write new value to the Wiper Counter Register pointed

1 R0 P1 P0 Transfer the contents of the Data Register pointed to

1 R0 P1 P0 Transfer the contents of the Wiper Counter Register

1 R0 0 0 Transfer the contents of the Data Registers pointed to by

1 R0 0 0 Transfer the contents of both Wiper Counter Registers

9 FN8191.2 September 19, 2005 DETAILED OPERATION All XDCP potentiometers s hare the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9408 contains four Wiper Counter Registers, one for each XDCP potentiometer. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches al ong its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register in struction (serial load); it may be written indirectly by transfer ring the contents of one of four associated data registers via the XFR Data Register instruction (paralle l load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its data register zero (DR0) upon power-up. The WCR is a volatile regist er; that is, its contents are lost when the X9408 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operati on and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions Data Registers, (6-Bit), Nonvolatile Four 6-bit Data Registers for each XDCP. (sixteen 6- bit registers in total). – {D5~D0}: These bits are for general purpose not vol- atile data storage or for storage of up to four differ- ent wiper values. The contents of Data Register 0 are automatically moved to the wiper counter regis- ter on power-up. Wiper Counter Register, (6-Bit), Volatile One 6-bit Wiper Counter Register for each XDCP. (Four 6-bit registers in total.) – {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR. D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV (MSB) (LSB) WP5 WP4 WP3 WP2 WP1 WP0 VVVVVV (MSB) (LSB) X9408

10 FN8191.2 September 19, 2005 Instruction Format Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. (2) “A3 ~ A0”: stands for the device addresses sent by the master. (3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. (4) “I”: stands for the increment operation, SDA held high during active SCL phase (high). (5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high). Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) XFR Data Register (DR) to Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) to Data Register (DR) S T A R T device type identifier device addresses S A C K instruction opcode WCR addresses S A C K wiper position (sent by slave on SDA) M A C K S T O P0101 A A A A 0 100100 P P 0 00 W P W P W P W P W P W P S T A R T device type identifier device addresses S A C K instruction opcode WCR addresses S A C K wiper position (sent by master on SDA) S A C K S T O P0101 A A A A 0 101000 P P 0 00 W P W P W P W P W P W P S T A R T device type identifier device addresses S A C K instruction opcode DR and WCR addresses S A C K wiper position/data (sent by slave on SDA) M A C K S T O P0101 A A A A 0 1011 R R P P 0 00 W P W P W P W P W P W P S T A R T device type identifier device addresses S A C K instruction opcode DR and WCR addresses S A C K wiper position/data (sent by master on SDA) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0101 A A A A 0 1100 R R P P 0 00 W P W P W P W P W P W P S T A R T device type identifier device addresses S A C K instruction opcode DR and WCR addresses S A C K S T O P0101 A A A A 0 1101 R R P P S T A R T device type identifier device addresses S A C K instruction opcode DR and WCR addresses S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0101 A A A A 0 1110 R R P P X9408

11 FN8191.2 September 19, 2005 Increment/Decrement Wiper Counter Register (WCR) Global XFR Data Register (DR) to Wiper Counter Register (WCR) Global XFR Wiper Counter Register (WCR) to Data Register (DR) SYMBOL TABLE Guidelines for Calculating Typical Values of Bus Pull-Up Resistors S T A R T device type identifier device addresses S A C K instruction opcode WCR addresses S A C K increment/decrement (sent by master on SDA) S T O P0101 A A A A 0 001000 P P D D .... I/ D D S T A R T device type identifier device addresses S A C K instruction opcode DR addresses S A C K S T O P0101 A A A A 0 0001 R R 0 00 S T A R T device type identifier device addresses S A C K instruction opcode DR addresses S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0101 A A A A 0 1000 R R 0 00 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 120 100 20 40 60 80 100 120 Resistance (Κ) Bus Capacitance (pF) Min. Resistance Max. Resistance RMAX = CBUS tR RMIN = IOL MIN VCC MAX=1.8kΩ X9408

12 FN8191.2 September 19, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on SDA, SCL or any address Any V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not imp lied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Symbol Parameter Limits Test ConditionMin. Typ. Max. Unit RTOTAL End to end resistance tolerance -20 +20 % Power rating 50 mW 25°C, each pot IW Wiper current -3 +3 mA RW Wiper resistance 150 250 Ω IW = ± 1mA @ V+, V- = ±3V 40 100 Ω IW = ± 1mA @ V+, V- = ±5V VV+ Voltage on V+ pin X9408 +4.5 +5.5 V VV- Voltage on V- pin X9408 -5.5 -4.5 V VTERM Voltage on any VH/RH, VL/RL or VW/RW pin V- V+ V Noise -120 dBV Ref: 1kHz Resolution 1.6 % See Note 4 Absolute linearity (1) -1 +1 MI (3) V(Vwn/Rwn)(actual) - V(Vwn/Rwn)(expected)(4) Relative linearity (2) -0.2 +0.2 MI (3) V(Vw(n+1)/Rw(n+1)) - V(Vw(n)/Rw(n)) + MI Temperature coefficient of RTOTAL ±300 ppm/°C See Note 4 Ratiometric Temperature Coefficient 20 ppm/°C See Note 4 CH/CL/CW Potentiometer Capacitances 10/10/25 pF See Macro model IAL VH/RH, VL/RL, VW/RW Leakage Current 0.1 10 µA V IN = V- to V+. Device is in Stand-by mode. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C+ 7 0 °C Industrial -40 °C+ 8 5 °C Device Supply Voltage (V CC) Limits X9408 5V ± 10% X9408-2.7 2.7V to 5.5V X9408

13 FN8191.2 September 19, 2005 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Notes: (1) Absolute linearity is utilized to determ ine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to deter mine the actual change in voltage between two successive tap positions when used as a potentiom- eter. It is a measure of the error in step size. (3) MI = RTOT / 63 or [V(VH/RH) – V(VL/RL)] / 63, single pot ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING Power-up Requirements (Power-up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First V-, then V CC and V+, and then the potentiometer pins, V H/RH, VL/RL, and V W/RW. Voltage should not be applied to the potentiome ter pins before V+ or V- is applied. The V CC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for proper wiper register recall. Also, V CC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until VCC, V+ and V- reach their final value. Notes: (4) This parameter is periodically sampled and not 100% tested (5) t PUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (6) This is not a tested or guaranteed par ameter and should only be used as a guidance. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit ICC1 VCC supply current (nonvolatile write) 1m A f SCL = 400kHz, SDA = Open, Other Inputs = VSS ICC2 VCC supply current (move wiper, write, read) 100 µA f SCL = 400kHz, SDA = Open, Other Inputs = VSS ISB VCC current (standby) 1 µA SCL = SDA = V CC, Addr. = VSS ILI Input leakage current 10 µA V IN = VSS to VCC ILO Output leakage current 10 µA V OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC +0.5 V VIL Input LOW voltage –0.5 V CC x 0.1 V VOL Output LOW voltage 0.4 V I OL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Unit Test Condition CI/O(4) Input/output capacitance (SDA) 8 pF V I/O = 0V CIN(4) Input capacitance (A0, A1, A2, A3, and SCL) 6 pF V IN = 0V Symbol Paramete r Min. Max. Unit tPUR(5) Power-up to initiation of read operation 1 ms tPUW(5) Power-up to initiation of write operation 5 ms tRVCC(6) VCC Power-up Ramp 0.2 50 V/msec X9408

14 FN8191.2 September 19, 2005 A.C. TEST CONDITIONS EQUIVALENT A.C. LOAD CIRCUIT Circuit #3 SPICE Macro Model AC TIMING (over recommended operating condition) HIGH-VOLTAGE WRITE CYCLE TIMING Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 1533Ω 100pF SDA Output 10pF VH/RH RTOTAL CH 25pF CW CL 10pF VW/RW VL/RL Symbol Parameter Min. Max. Unit fSCL Clock frequency 400 kHz tCYC Clock cycle time 2500 ns tHIGH Clock high time 600 ns tLOW Clock low time 1300 ns tSU:STA Start setup time 600 ns tHD:STA Start hold time 600 ns tSU:STO Stop setup time 600 ns tSU:DAT SDA data input setup time 100 ns tHD:DAT SDA data input hold time 30 ns tR SCL and SDA rise time 300 ns tF SCL and SDA fall time 300 ns tAA SCL low to SDA data output valid time 900 ns tDH SDA Data output hold time 50 ns TI Noise suppression time constant at SCL and SDA inputs 50 ns tBUF Bus free time (prior to any transmission) 1300 ns tSU:WPA WP, A0, A1, A2 and A3 setup time 0 ns tHD:WPA WP, A0, A1, A2 and A3 hold time 0 ns Symbol Parameter Typ. Max. Unit tWR High-voltage write cycle time (store instructions) 5 10 ms X9408

15 FN8191.2 September 19, 2005 XDCP TIMING Notes: (9) A device must internally provide a ho ld time of at least 300ns for the SDA si gnal in order to bridge the undefined region of the falling edge of SCL. TIMING DIAGRAMS START and STOP Timing g Input Timing Output Timing Symbol Parameter Min. Max. Unit tWRPO Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 µs tSU:STA tHD:STA tSU:STO SCL SDA tR (START) (STOP) tF tR tF SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA X9408

16 FN8191.2 September 19, 2005 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers Application Circuits VR +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysteresis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R2R1 X9408

17 FN8191.2 September 19, 2005 Application Circuits (continued) Inverting Amplifier Equivalent L-R Circuit VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C Attenuator Filter VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) R4 All RS = 10kΩ VS R C VO X9408

18 FN8191.2 September 19, 2005 XDCP Timing (for All Load Instructions) XDCP Timing (for Increment/Decrement Instruction) Write Protect and Device Address Pins Timing SCL SDA VWx (STOP) LSB tWRL SCL SDA VWx tWRID Wiper Register Address Inc/Dec Inc/Dec SDA SCL ... ... ... WP A0, A1 A2, A3 tSU:WPA tHD:WPA (START) (STOP) (Any Instruction) X9408

19 FN8191.2 September 19, 2005 PACKAGING INFORMATION 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.022 (0.56) 0.014 (0.36) 0.150 (3.81) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 0.110 (2.79) 0.090 (2.29) 1.265 (32.13) 1.230 (31.24) 1.100 (27.94) Ref. Pin 1 Index 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) Pin 1 Seating Plane 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.530 (13.46) 0.080 (2.03) 0.065 (1.65) 15° 24-Lead Plastic Dual In-Line Package Type P Typ. 0.010 (0.25) NOTE: X9408

20 FN8191.2 September 19, 2005 PACKAGING INFORMATION 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 24-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

24 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0° - 8° X 45° X9408

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8191.2 September 19, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 24-Lead Plastic, TSSOP Package Type V .169 (4.3) .026 (.65) BSC .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) ALL MEASUREMENTS ARE TYPICAL 0° - 8° X9408