X9401WV24Z-2.7

X9401_09 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• Quad - 4 Separate Pots, 64 Taps/Pot
• Nonvolatile Storage of Wiper Position
• Four Nonvolatile Data Registers for Each Pot
• 16-bytes of EEPROM Memory
• SPI Serial Interface TOTAL = 10kΩ
• Wiper Resistance = 150 Ω Typical
• Standby Current < 3µA (Total Package)
• Operating Current < 700µA max. CC = 2.7V to 5V
• 24 Ld SOIC and 24 Ld TSSOP Package
• 100 year Data Retention
• Pb-Free Available (RoHS Compliant) Block Diagram INTERFACE AND CONTROL CIRCUITRY CS SCK SO R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 1 VH1/RH1 VL1/RL1 R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) VH0/RH0 VL0/RL0 DATA VW0/RW0 VW1/RW1 R0 R1 R2 R3 RESISTOR ARRAY VH2/RH2 VL2/RL2 VW2/RW2 R0 R1 R2 R3 RESISTOR ARRAY VH3/RH3 VL3/RL3 VW3/RW3 WIPER COUNTER REGISTER (WCR) WIPER COUNTER REGISTER (WCR) POT 3 POT 2 HOLD POT 0VCC VSS WP SI CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Data Sheet FN8190.4 October 13, 2009

2 FN8190.4 October 13, 2009 Pin Descriptions Host Interface Pins SERIAL OUTPUT (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9401. CHIP SELECT (CS When CS is HIGH, the X9401 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9401, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A0 - A1) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9401. A maximum of 4 devices may occupy the SPI serial bus. Potentiometer Pins VH (VH0 - VH3)/ RH (RH0 - RH3), VL (VL0 - VL3)/RL (RL0 - RL3) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW (VW0 - VW3)/ RW (RW0 - RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Wiper Counter Registers.

Ordering Information

(V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE PKG. DWG. # X9401WS24IZ* (Note 1) X9401WS ZI 5 ±10% 10 -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9401WS24I X9401WS I -40 to +85 24 Ld SOIC (300 mil) M24.3 X9401WS24Z* (Note 1) X9401WS Z -40 to +85 24 Ld SOIC (300 mil) M24.3 X9401WV24IZ* (Note 1) X9401WV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9401WV24Z* (Note 1) X9401WV Z -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9401WS24I-2.7* (Note 2) X9401WS G 2.7 to 5.5 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9401WS24IZ-2.7* (Note) X9401WS ZG -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9401WS24Z-2.7* (Note 1) X9401WS ZF -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9401WV24-2.7 X9401WV F -40 to +85 24 Ld TSSOP (4.4mm) MDP0044 X9401WV24IZ-2.7* (Note 1) X9401WV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9401WV24Z-2.7* (Note 1) X9401WV ZF -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 *Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged pr oducts employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Not recommended for new designs. X9401

3 FN8190.4 October 13, 2009 Pinouts X9401 (24 LD SOIC) TOP VIEW X9401 (24 LD TSSOP) TOP VIEW Device Description The X9401 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9401 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9401 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V H/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. Wiper Counter Register (WCR) The X9401 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9401 is powered-down. Although the register is automatically loaded with the value in R 0 upon power-up, this may be different from the value present at power-down. The wiper position must be stored in R 0 to insure restoring the wiper position after power-up. Pin Descriptions SOIC PIN # TSSOP PIN # SYMBOL DESCRIPTION 52 3 C S Chip select 17 11 SCK Serial Clock 7, 19 1, 13 SI, S0 Serial Data 20, 8 14, 2 A 0 - A1 Device Address 3, 10, 15, 22, 2, 9, 16, 23 21, 4, 9, 16, 20, 3, 10, 17 VH0/RH0,VH1/RH1, VH2/RH2, VH3/RH3, VL0/RL0, VL1/RL1, VL2/RL2, VL3/RL3 Potentiometer end terminals 4, 11, 14, 21 22, 5, 8, 15 V W0/RW0, VW1/RW1, VW2/RW2, VW3/RW3 Wipers 62 4 W P Hardware Write Protection 18 12 HOLD Hardware Hold 11 9 V CC System Supply Voltage 12 6 V SS System Ground 13, 24 7, 18 NC No Connection VCC VL0/RL0 VH0/RH0 VW0/RW0 CS WP SI VL1/RL1 VH1/RH1 VW1/RW1 VSS NC VH3/RH3 VW3/RW3 SCK VH2/RH2 VW2/RW2 NC VL3/RL3 HOLD VL2/RL2 SI VL1/RL1 VH1/RH1 VW1/RW1 VSS NC VW2/RW2 VH2/RH2 VL2/RL2 SCK HOLD WP VW0/RW0 VH0/RH0 VL0/RL0 VCC VL3/RL3 VW3/RW3 CS NC VH3/RH3 X9401

FIGURE 3. TWO-BYTE COMMAND SEQUENCE FIGURE 4. THREE-BYTE COMMAND SEQUENCE (WRITE) FIGURE 5. THREE-BYTE COMMAND SEQUENCE (READ)

010100 A 1 A 0 I3 I2 I1 I0 0 P1 P0

FIGURE 6. INCREMENT/DECREMENT COMMAND SEQUENCE

TABLE 1. INSTRUCTION SET

1 R0 P1 P0 Transfer the contents of the Data Register pointed to by R1 - R0

1110 R 1 R0 P1 P0 Transfer the contents of the Wiper Counter Register pointed to by

0001 R 1 R0 0 0 Transfer the contents of the Data Registers pointed to by R 1 - R0

1000 R 1 R0 0 0 Transfer the contents of all Wiper Counter Registers to their

FIGURE 7. INCREMENT/DECREMENT TIMING LIMITS

8 FN8190.4 October 13, 2009 Instruction Format NOTES: 3. A1 ~ A0”: stands for the device addresses sent by the master. 4. WPx refers to wiper position data in the Counter Register 5. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). 6. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Increment/Decrement Wiper Counter Register (WCR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE WCR ADDRESSES WIPER POSITION (SENT BY X9401 ON SO) CS RISING EDGE010100A 1 A 0 1 0 0 1 00 P 1P 000W P 5 W P 4 W P 3 W P 2 W P 1 W P 0 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE WCR ADDRESSES DATA BYTE (SENT BY HOST ON SI) CS RISING EDGE0 1 0 1 0 0 A1 A0 1 0 1 0 0 0 P1 P0 0 0 WP5 WP4 WP3 WP2 WP1 WP0 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR AND WCR ADDRESSES DATA BYTE (SENT BY X9401 ON SO) CS RISING EDGE010100A 1A 01011R 1 R 0 P 1 P 0 0 0 W P 5 W P 4 W P 3 W P 2 W P 1 W P 0 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR AND WCR ADDRESSES DATA BYTE (SENT BY HOST ON SI) CS RISING EDGE HIGH- VOLTAGE WRITE CYCLE0 1 0 1 00A 1A 0 1 1 0 0 R 1R 0P 1P 000W P 5W P 4W P 3W P 2W P 1W P 0 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR AND WCR ADDRESSES CS RISING EDGE010100A 1A 01 1 0 1R 1 R 0 P 1 P 0 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR AND WCR ADDRESSES CS RISING EDGE HIGH-VOLTAGE WRITE CYCLE010100 A 1 A 0 1110R 1R 0 P 1 P 0 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE WCR ADDRESSES INCREMENT/DECREMENT (SENT BY MASTER ON SDA) CS RISING EDGE0 1 0 1 0 0 A1 A0 0 0 1 0 X X P1 P0 I/D I/D . . . . I/D I/D CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR ADDRESSES CS RISING EDGE0 1 0 1 0 0 A 1 A 0 0001 R 1 R 0 0 0 X9401

9 FN8190.4 October 13, 2009 Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Read Status CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE DR ADDRESSES CS RISING EDGE HIGH-VOLTAGE WRITE CYCLE010100A 1A 01 0 0 0 R 1 R 000 CS FALLING EDGE DEVICE TYPE IDENTIFIER DEVICE ADDRESSES INSTRUCTION OPCODE WIPER ADDRESSES DATA BYTE (SENT BY X9401 ON SO) CS RISING EDGE010100A 1 A 0 0 1 0 100010000000 W I P X9401

10 FN8190.4 October 13, 2009 Power-up and Down Requirements The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the poten- tiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC power-up spec is always in effect. Absolute Maximum Ratings Thermal Information Supply Voltage (VCC Limits) Voltage on SCK, SCL or any address input with respect to V http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications (Over recommended operating conditions unless otherwise stated.) SYMBOL PARAMETER TEST CONDITION MIN (Note 10) TYP MAX (Note 10) UNIT RTOTAL End to End resistance Tolerance -20 +20 % Power Rating +25°C, each pot 50 mW I W Wiper Current -6 +6 mA RW Wiper Resistance I W = (VH - VL)/RTOTAL VCC = 5V 150 500 Ω VTERM Voltage on any VH or VL Pin V SS VCC V Noise Ref: 1kHz -120 dBV Resolution 1.6 % Absolute Linearity (Note 7) V W(n)(actual) - VW(n)(expected) -1 +1 MI (Note 9) Relative Linearity (Note 8) V w(n+1) - [Vw(n)+ MI] -0.2 +0.2 MI (Note 9) Temperature Coefficient of RTOTAL V(RH) = VCC, V(RL) = VSS ±300 ppm/°C Ratiometric Temperature Coefficient ±20 ppm/°C CH/CL/CW Potentiometer Capacitances See Macro model 10/10/25 pF IAL RH, RL, RW Leakage Current V IN = VSS Device is in Stand-by mode. 0.1 10 µA NOTES: 7. Absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 8. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 9. MI = RTOT/63 or (V H - VL)/63, single pot. 10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. X9401

11 FN8190.4 October 13, 2009 Equivalent AC Load Circuit DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNIT ICC1 VCC Supply Current (active) f SCK = 2MHz, SO = Open, Other Inputs = VSS 700 µA ICC2 VCC Supply Current (non-volatile write) f SCK = 2MHz, SO = Open, Other Inputs = VSS 3m A ISB VCC Current (standby) SCK = SI = V SS, Addr. = VSS, CS = VCC 3µ A ILI Input Leakage Current V IN = VSS to VCC 10 µA ILO Output Leakage Current V OUT = VSS to VCC 10 µA VIH Input HIGH Voltage VCC x 0.7 V CC +0.5 V VIL Input LOW Voltage –0.5 V CC x 0.1 V VOL Output LOW Voltage I OL = 3mA 0.4 V Endurance and Data Retention PARAMETER MIN. UNIT Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Capacitance SYMBOL TEST TYP. UNIT TEST CONDITION COUT (Note 11) Output capacitance (SO) 8 pF V OUT = 0V CIN (Note 11) Input capacitance (A0, A1, SI, and SCK) 6 pF V IN = 0V Power-up Timing Input pulse levels = VCC x 0.1 to VCC x 0.9; Input rise and fall times = 10ns; Input and output timing level = VCC x 0.5. SYMBOL PARAMETER MIN. MAX. UNIT tr VCC (Note 11) VCC Power-up rate 0.2 50 V/ms tPUR (Note 12) Power-up to initiation of read operation 1 ms tPUW (Note 12) Power-up to initiation of write operation 5 ms NOTES: 11. This parameter is not 100% tested. 12. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. 1533Ω 100pF SDA OUTPUT RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACRO MODEL X9401

12 FN8190.4 October 13, 2009 AC Timing SYMBOL PARAMETER MIN. (Note 10) MAX. (Note 10) UNIT fSCK SSI/SPI clock frequency 2.0 MHz tCYC SSI/SPI clock cycle rime 500 ns tWH SSI/SPI clock high rime 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs tDIS SO output disable time 0 500 ns tV SO output valid time 150 ns tHO SO output hold time 0 ns tRO SO output rise time 50 ns tFO SO output fall time 50 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns tCS CS deselect time 2 µs tWPASU WP, A0 and A1 setup time 0 ns tWPAH WP, A0 and A1 hold time 0 ns High-voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX (Note 10) UNIT tWR High-voltage write cycle time (store instructions) 5 10 ms XDCP Timing SYMBOL PARAMETER MIN. MAX. (Note 10) UNIT tWRPO Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns X9401

13 FN8190.4 October 13, 2009 Symbol Table Timing Diagrams Input Timing Output Timing WAVEFORM INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM LO W TO HIGH WILL CHANGE FROM LOW TO HIGH MAY CHANGE FROM HIGH TO LOW WILL CHANGE FROM HIGH TO LOW DON’T CARE: CHANGES ALLO WED CHANGING: STATE NOT KNO WN N/A CENTER LINE IS HIGH IMPEDANCE ... CS SCK SI SO MSB LSB HIGH IMPEDANCE tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... X9401

14 FN8190.4 October 13, 2009 Hold Timing XDCP Timing (for All Load Instructions) XDCP Timing (for Increment/Decrement Instruction) Write Protect and Device Address Pins Timing ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO ... CS SCK SI MSB LSB VW/RW tWRL ... SO HIGH IMPEDANCE ... CS SCK SO SI ADDR tWRID HIGH IMPEDANCE VW/RW ...INC/DEC INC/DEC ... CS WP tWPASU tWPAH (ANY INSTRUCTION) X9401

15 FN8190.4 October 13, 2009 Applications information Basic Configurations of Electronic Potentiometers Application Circuits VR VW/RW +VR I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT NONINVERTING AMPLIFIER VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS VS VO VO = (1+R2/R1)VS IADJ VO (REG) = 1.25V (1+R2/R1)+IADJ R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(MAX) VLL = {R1/(R1+R2)} VO(MIN) 100KΩ 10KΩ10KΩ 10KΩ +5V TL072 –VS VO R2R1 ATTENUATOR FILTER VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) R4 ALL RS = 10KΩ VS R C VO X9401

16 FN8190.4 October 13, 2009 Application Circuits (continued) INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT VS VO R2R1 ZIN = R2 + S R2 (R1 + R3) C1 = R2 + S LEQ (R1 + R3) >> R2 VS FUNCTION GENERATOR VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB FREQUENCY µ R1, R2, C AMPLITUDE µ RA, RB C X9401

17 FN8190.4 October 13, 2009 X9401 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.020 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.5985 0.6141 15.20 15.60 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 4 2 4 7 α 0° 8° 0° 8° - Rev. 1 4/06

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8190.4 October 13, 2009 X9401 Thin Shrink Small Outline Package Family (TSSOP) N (N/2)+1 (N/2) TOP VIEW AD 0.20 C B A N/2 LEAD TIPSB E1E

0.25 CABM

H PIN #1 I.D. 0.05 eC 0.10 C N LEADS SIDE VIEW

0.10 CABMb

c SEE DETAIL “X” END VIEW DETAIL X 0° - 8° GAUGE PLANE 0.25 LA1 A SEATING PLANE MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY SYMBOL MILLIMETERS TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M -1994.