X9401WS24IZ-2.7

X9401 INTERSIL | Alldatasheet

Document overview

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Technical content

Low Noise/Low Power/SPI Bus Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP™)

FEATURES

• Quad–4 separate pots, 64 taps/pot
• Nonvolatile storage of wiper position
• Four Nonvolatile Data Registers for Each Pot
• 16-bytes of EEPROM memory
• SPI serial interface Total = 10kΩ
• Wiper resistance = 150Ω typical
• Standby current < 1µA (total package)
• Operating current < 400µA max. CC = 2.7V to 5V
• Packages–24 Ld TSSOP and SOIC
• 100 year data retention
• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9401 integrates 4 digitally controlled potentiome- ters (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 64 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvola- tile Data Registers (DR0:DR3) that can be directly writ- ten to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiom- eter or as a two-terminal variable resistor in a wide variety of applications in cluding control, parameter adjustments, and signal processing. BLOCK DIAGRAM Interface and Control Circuitry CS SCK SO R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 1 VH1/RH1 VL1/RL1 R0 R1 R2 R3 Wiper Counter Register (WCR) VH0/RH0 VL0/RL0 Data VW0/RW0 VW1/RW1 R0 R1 R2 R3 Resistor Array VH2/RH2 VL2/RL2 VW2/RW2 R0 R1 R2 R3 Resistor Array VH3/RH3 VL3/RL3 VW3/RW3 Wiper Counter Register (WCR) Wiper Counter Register (WCR) Pot 3 Pot 2 HOLD Pot 0VCC VSS WP SI CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. PRELIMINARY Data Sheet FN8190.2 September 23, 2005

2 FN8190.2 September 23, 2005

Ordering Information

MARKING V CC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE X9401WS24* X9401WS 5 ±10% 10 0 to 70 24 Ld SOIC (300 mil) X9401WS24Z* (Note) X9401WS Z 0 to 70 24 Ld SOIC (300 mil) (Pb-free) X9401WS24I* X9401WS I -40 to 85 24 Ld SOIC (300 mil) X9401WS24IZ* (Note) X9401WS Z I -40 to 85 24 Ld SOIC (300 mil) (Pb-free) X9401WV24* X9401WV 0 to 70 24 Ld TSSOP (4.4mm) X9401WV24Z* (Note) X9401WV Z 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9401WV24I* X9401WV I -40 to 85 24 Ld TSSOP (4.4mm) X9401WV24IZ* (Note) X9401WV Z I -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) X9401WS24-2.7* X9401WS F 2.7 to 5.5 0 to 70 24 Ld SOIC (300 mil) X9401WS24Z-2.7* (Note) X9401WS Z F 0 to 70 24 Ld SOIC (300 mil) (Pb-free) X9401WS24I-2.7* X9401WS G -40 to 85 24 Ld SOIC (300 mil) X9401WS24IZ-2.7* (Note) X9401WS Z G -40 to 85 24 Ld SOIC (300 mil) (Pb-free) X9401WV24-2.7* X9401WV F 0 to 70 24 Ld TSSOP (4.4mm) X9401WV24Z-2.7* (Note) X9401WV Z F 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) X9401WV24I-2.7* X9401WV G -40 to 85 24 Ld TSSOP (4.4mm) X9401WV24IZ-2.7* (Note) X9401WV Z G -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) X9401YS24I-2.7 X9401YS G 2.5 -40 to 85 24 Ld SOIC (300 mil) X9401YV24I-2.7 X9401YV G -40 to 85 24 Ld TSSOP (4.4mm) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. X9401

3 FN8190.2 September 23, 2005 PIN DESCRIPTIONS Host Interface Pins Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The SCK input is used to clock data into and out of the X9401. Chip Select (CS When CS is HIGH, the X9401 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9401, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. Device Address (A0 - A1) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initia te communication with the X9401. A maximum of 4 dev ices may occupy the SPI serial bus. Potentiometer Pins V H (VH0 - VH3), VL (VL0 - VL3), RH (RH0 - RH3), RL (RL0 - RL3) The V H/RH and V L/RL inputs are equivalent to the terminal connections on either end of a mechanical poten- tiometer. VW (VW0 - VW3), RW (RW0 - RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when LOW prevents nonvolatile writes to the Wiper Counter Registers. PIN CONFIGURATION VCC VL0/RL0 VH0/RH0 WP SI NC V L3/RL3 VH3/RH3 VW3/RW3 SO HOLD SCK V L2/RL2 VH2/RH2 SOIC X9401 VSS VW0/RW0 CS VL1/RL1 VH1/RH1 VW1/RW1 VW2/RW2 NC SI VH2/RH2 WP CS VW0/RW0 VCC NC VL3/RL3 VH3/RH3 VW3/RW3 TSSOP X9401 VW2/RW2 12HOLD VL1/RL1 VH1/RH1 VW1/RW1 SO VH0/RH0 NC SCK VL2/RL2 VL0/RL0 VSS X9401

4 FN8190.2 September 23, 2005 PIN NAMES DEVICE DESCRIPTION The X9401 is a highly integr ated microcircuit incorpo- rating four resistor arrays and their associated regis- ters and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9401 supports the SPI interface hardware con- ventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9401 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V H/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper W/RW) output. Within each individual array only one switch may be turned on at a time. These switches are cont rolled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. Wiper Counter Register (WCR) The X9401 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equiv- alent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. Th e contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruc- tion (serial load); it may be written indirectly by trans- ferring the contents of one of four associated data registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the Increment/Decre- ment instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9401 is powered- down. Although the register is automatically loaded with the value in R 0 upon power-up, this may be differ- ent from the value present at power-down. The wiper position must be stored in R 0 to insure restoring the wiper position after power-up. Data Registers Each potentiometer has four 6-bit nonvolatile data reg- isters. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the data registers can be used as memory locations for system parameters or user preference data. Data Register Detail Symbol Description SCK Serial Clock SI, SO Serial Data A0 - A1 Device Address VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 Potentiometers (terminal equivalent) V W0/RW0 - VW1/RW1 Potentiometers (wiper equivalent) WP Hardware Write Protection VCC System Supply Voltage VSS System Ground NC No Connection (MSB) (LSB) D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV X9401

tion can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command. is fixed as 0101[B] (refer to Figure 1). The remaining two bits in the slave byte must be set to 0. Figure 1. Identification Byte Format mat is shown below in Figure 2.

Figure 3. Two-Byte Command Sequence Figure 4. Three-Byte Command Sequence (Write) Figure 5. Three-Byte Command Sequence (Read) Figure 6. Increment/Decrement Command Sequence

010100 A 1 A 0 I3 I2 I1 I0 0 P1 P0

Figure 7. Increment/Decrement Timing Limits Table 1. Instruction Set

1 R0 P1 P0 Transfer the contents of the Data Register pointed to

1 R0 P1 P0 Transfer the contents of the Wiper Counter Register

1 R0 0 0 Transfer the contents of the Data Registers pointed to

1000 R 1 R0 0 0 Transfer the contents of all Wiper Counter Registers

9 FN8190.2 September 23, 2005 Instruction Format Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) CS Falling Edge device type identifier device addresses instruction opcode WCR addresses wiper position (sent by X9401 on SO) CS Rising Edge010100 A A 0 100100 P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode WCR addresses Data Byte (sent by Host on SI) CS Rising Edge010100 A A 0 101000 P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by X9401 on SO) CS Rising Edge010100 A A 0 1011 R R P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1100 R R P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses CS Rising Edge010100 A A 0 1101 R R P P X9401

10 FN8190.2 September 23, 2005 Transfer Wiper Counter Register (WCR) to Data Register (DR) Increment/Decrement Wiper Counter Register (WCR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Read Status CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1110 R R P P CS Falling Edge device type identifier device addresses instruction opcode WCR addresses increment/decrement (sent by master on SDA) CS Rising Edge010100 A A 0 0010XX P P D D .... I/ D D CS Falling Edge device type identifier device addresses instruction opcode DR addresses CS Rising Edge010100 A A 0 0001 R R 0 00 CS Falling Edge device type identifier device addresses instruction opcode DR addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1000 R R 0 00 CS Falling Edge device type identifier device addresses instruction opcode wiper addresses Data Byte (sent by X9401 on SO) CS Rising Edge010100 A A 0 010100010000000 W I P X9401

11 FN8190.2 September 23, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on SCK, SCL or any address COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specifi- cation) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) POWER-UP AND DOWN REQUIREMENTS The are no restrictions on the power-up or power-down conditions of V CC and the voltages applied to the poten- tiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC power-up spec is always in effect. Notes: (1) Absolute linearity is utilized to determ ine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to deter mine the actual change in voltage between two successive tap positions when used as a potentiom- eter. It is a measure of the error in step size. (3) MI = RTOT/63 or (V H - VL)/63, single pot Symbol Parameter Limits Test ConditionMin. Typ. Max. Unit RTOTAL End to end resistance –20 +20 % Power rating 50 mW 25 °C, each pot IW Wiper current –6 +6 mA RW Wiper resistance 150 500 Ω Wiper Current = ± 3mA VTERM Voltage on any VH or VL Pin V SS VCC VV SS = 0V Noise -120 dBV Ref: 1kHz Resolution 1.6 % Absolute linearity (1) -1 +1 MI (3) Vw(n)(actual) - Vw(n)(expected) Relative linearity (2) -0.2 +0.2 MI (3) Vw(n + 1) - [Vw(n) + MI] Temperature coefficient of RTOTAL ±300 ppm/ °C Ratiometric temp. coefficient ±20 ppm/°C CH/CL/CW Potentiometer capacitances 10/10/25 pF See Macro model IAL RH, RL, RW leakage current 0.1 10 µA V IN = VSS to VCC. Device is in stand-by mode. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C+ 7 0 °C Industrial -40 °C+ 8 5 °C Device Supply Voltage (V CC) Limits X9401 5V ± 10% X9401-2.7 2.7V to 5.5V X9401

12 FN8190.2 September 23, 2005 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING A.C. TEST CONDITIONS Notes: (4) This parameter is periodically sampled and not 100% tested (5) t PUR and t PUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are period- ically sampled and not 100% tested. (6) This is not a tested or guaranteed parameter and should be used only as a guideline. EQUIVALENT A.C. LOAD CIRCUIT Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit ICC1 VCC supply current (active) 400 µA f SCK = 2MHz, SO = Open, Other Inputs = VSS ICC2 VCC supply current (nonvola- tile write) 1m A f SCK = 2MHz, SO = Open, Other Inputs = VSS ISB VCC current (standby) 1 µA SCK = SI = V SS, Addr. = VSS, CS = VCC ILI Input leakage current 10 µA V IN = VSS to VCC ILO Output leakage current 10 µA V OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 0.5 V VIL Input LOW voltage -0.5 V CC x 0.1 V VOL Output LOW voltage 0.4 V I OL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Unit Test Condition COUT(4) Output capacitance (SO) 8 pF V OUT = 0V CIN(4) Input capacitance (A0, A1, SI, and SCK) 6 pF V IN = 0V Symbol Parameter Min. Max. Unit tr VCC(6) VCC Power-up rate 0.2 50 V/ms tPUR(5) Power-up to initiation of read operation 1 ms tPUW(5) Power-up to initiation of write operation 5 ms Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 1533Ω 100pF SDA Output RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE Macro Model X9401

13 FN8190.2 September 23, 2005 AC TIMING HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING Symbol Parameter Min. Max. Unit fSCK SSI/SPI clock frequency 2.0 MHz tCYC SSI/SPI clock cycle rime 500 ns tWH SSI/SPI clock high rime 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs tDIS SO output disable time 0 500 ns tV SO output valid time 100 ns tHO SO output hold time 0 ns tRO SO output rise time 50 ns tFO SO output fall time 50 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns tCS CS deselect time 2 µs tWPASU WP, A0 and A1 setup time 0 ns tWPAH WP, A0 and A1 hold time 0 ns Symbol Parameter Typ. Max. Unit tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Unit tWRPO Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns X9401

14 FN8190.2 September 23, 2005 SYMBOL TABLE TIMING DIAGRAMS Input Timing Output Timing WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... X9401

15 FN8190.2 September 23, 2005 Hold Timing XDCP Timing (for All Load Instructions) XDCP Timing (for Increment/Decrement Instruction) ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO ... CS SCK SI MSB LSB VW/RW tWRL ... SO High Impedance ... CS SCK SO SI ADDR tWRID High Impedance VW/RW ...Inc/Dec Inc/Dec ... X9401

16 FN8190.2 September 23, 2005 Write Protect and Device Address Pins Timing APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers CS WP tWPASU tWPAH (Any Instruction) VR VW/RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current X9401

17 FN8190.2 September 23, 2005 Application Circuits Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysteresis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 100kΩ 10kΩ10kΩ 10kΩ +5V TL072 –VS VO R2R1 Attenuator Filter VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) R4 All RS = 10kΩ VS R C VO X9401

18 FN8190.2 September 23, 2005 Application Circuits (continued) Inverting Amplifier Equivalent L-R Circuit VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C X9401

19 FN8190.2 September 23, 2005 PACKAGING INFORMATION 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 24-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

24 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0° - 8° X 45° X9401

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8190.2 September 23, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 24-Lead Plastic, TSSOP Package Type V .169 (4.3) .026 (.65) BSC .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) ALL MEASUREMENTS ARE TYPICAL 0° - 8° X9401