X9400

X9400 XICOR | Alldatasheet

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REV 1.1.4 10/11/02 Characteristics subject to change without notice. 1 of 22 www.xicor.com Low Noise/Low Power/SPI Bus X9400 Quad Digitally Controlled Potentiometers (XDCP

FEATURES

• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer operations of the potentiometer
• Wiper resistance, 40 Ω typical at 5V.
• Four non-volatile data registers for each potentiometer
• Non-volatile storage of multiple wiper position
• Power on recall. Loads saved wiper position on power up.
• Standby current < 1µA max
• System V CC : 2.7V to 5.5V operation
• Analog V : -5V to +5V
• 10K Ω , 2.5K Ω End to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per register
• Low power CMOS
• 24-lead SOIC, 24-lead TSSOP, and 24-lead XBGA packages

DESCRIPTION

The X9400 integrates four digitally controlled potentiometers (XDCPs) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI serial bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers (DR0-3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM Interface and Control Circuitry CS SCK SO R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 1 VH1/RH1 VL1/RL1 R0 R1 R2 R3 Wiper Counter Register (WCR) VH0/RH0 VL0/RL0 Data VW0/RW0 VW1/RW1 R0 R1 R2 R3 Resistor Array VH2/RH2 VL2/RL2 VW2/RW2 R0 R1 R2 R3 Resistor Array VH3/RH3 VL3/RL3 VW3/RW3 Wiper Counter Register (WCR) Wiper Counter Register (WCR) Pot 3 Pot 2 HOLD Pot 0VCC VSS WP SI A PPLICATION N OTES AVAILABLE AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135

Characteristics subject to change without notice. 2 of 22REV 1.1.4 10/11/02 www.xicor.com PIN DESCRIPTIONS Host Interface Pins Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The SCK input is used to clock data into and out of the X9400. Chip Select (CS When CS is HIGH, the X9400 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9400, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. Device Address (A A The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9400. A maximum of 4 devices may occupy the SPI serial bus. Potentiometer Pins V H H ), V L L The V H H and V L L inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. V W W The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Analog Supplies (V+, V-) The analog Supplies V+, V- are the supply voltages for the XDCP analog section. PIN CONFIGURATION VCC VL0/RL0 VH0/RH0 WP SI V L3/RL3 VH3/RH3 VW3/RW3 SO HOLD SCK V L2/RL2 VH2/RH2 SOIC X9408 VSS VW0/RW0 CS VL1/RL1 VH1/RH1 VW1/RW1 VW2/RW2 SI VH2/RH2 WP CS VW0/RW0 VCC VL3/RL3 VH3/RH3 VW3/RW3 TSSOP X9408 VW2/RW2 12HOLD VL1/RL1 VH1/RH1 VW1/RW1 SO VH0/RH0 SCK VL2/RL2 VL0/RL0 VSS 2 3 4 A B C D E F Top View–Bumps Down VW0/RW0 VL0/RL0 HOLD VL1/RL1 VCC VL3/RL3 VW3/RW3 SO SI VW1/RW1 SCK VL2/RL2 WP VH0/RH0 VH1/RH1 VH3/RH3 VH2/RH2 VSS VW2/RW2 CS A1 XBGA

The X9400 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9400 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9400 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V H/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper W/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a wiper counter register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. Wiper Counter Register (WCR) The X9400 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register or global XFR data register instructions (parallel load); it can be modified one step at a time by the increment/ decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power- up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9400 is powered- down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Data Registers Each potentiometer has four 6-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Data Register Detail Symbol Description SCK Serial Clock SI, SO Serial Data A 0-A1 Device Address VH0/RH0–VH3/RH3, VL0/RL0–VL3/RL3 Potentiometer Pins (terminal equivalent) V W0/RW0–VW1/RW1 Potentiometer Pins (wiper equivalent) WP Hardware Write Protection VCC System Supply Voltage VSS System Ground NC No Connection (MSB) (LSB) D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV

Figure 3. Instruction Byte Format potentiometers is to be affected by the instruction. to the associated Wiper Counter Register. Register to the specified associated Data Register. Registers to the associated Wiper Counter Registers. Registers to the specified associated Data Registers.

Figure 4. Two-Byte Instruction Sequence Figure 5. Three-Byte Instruction Sequence (Write) Figure 6. Three-Byte Instruction Sequence (Read) Figure 7. Increment/Decrement Instruction Sequence

010100 A 1 A 0 I3 I2 I1 I0 0 P1 P0

Figure 8. Increment/Decrement Timing Limits Table 1. Instruction Set

1101 R 1 R0 P1 P0 Transfer the contents of the Data Register pointed

1 R0 P1 P0 Transfer the contents of the Wiper Counter

1 R0 0 0 Transfer the contents of the Data Registers

1000 R 1 R0 0 0 Transfer the contents of all Wiper Counter

Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WPx refers to wiper position data in the Counter Register (3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge device type identifier device addresses instruction opcode WCR addresses wiper position (sent by X9400 on SO) CS Rising Edge010100 A A 0 100100 P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode WCR addresses Data Byte (sent by Host on SI) CS Rising Edge010100 A A 0 101000 P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by X9400 on SO) CS Rising Edge010100 A A 0 1011 R R P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1100 R R P P 0 00 W P W P W P W P W P W P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses CS Rising Edge010100 A A 0 1101 R R P P CS Falling Edge device type identifier device addresses instruction opcode DR and WCR addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1110 R R P P

Increment/Decrement Wiper Counter Register (WCR) Global Transfer Data Register (DR) to Wiper Counter Register (WCR) Global Transfer Wiper Counter Register (WCR) to Data Register (DR) Read Status CS Falling Edge device type identifier device addresses instruction opcode WCR addresses increment/decrement (sent by master on SDA) CS Rising Edge010100 A A 0 0010XX P P D D .... I/ D D CS Falling Edge device type identifier device addresses instruction opcode DR addresses CS Rising Edge010100 A A 0 0001 R R 0 00 CS Falling Edge device type identifier device addresses instruction opcode DR addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 010100 A A 0 1000 R R 0 00 CS Falling Edge device type identifier device addresses instruction opcode wiper addresses Data Byte (sent by X9400 on SO) CS Rising Edge010100 A A 0 010100010000000 W I P

Voltage on SCK, SCL or any address Any V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Device Supply Voltage (V CC) Limits X9400 5V ±10% X9400-2.7 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (RH–RL)/63, single pot Symbol Parameter Limits Test ConditionsMin. Typ. Max. Unit RTOTAL End to end resistance ±20 % Power rating 50 mW 25 °C, each pot IW Wiper current ±6 mA RW Wiper resistance 150 250 Ω Wiper Current = ± 1mA, VCC = 3V 40 100 Ω Wiper Current = ± 1mA, VCC = 5V Vv+ Voltage on V+ Pin X9400 +4.5 +5.5 V Vv- Voltage on V- Pin X9400 -5.5 -4.5 V VTERM Voltage on any VH/RH or VL/RL Pin V- V+ V Noise -120 dBV Ref: 1kHz Resolution 1.6 % Absolute linearity (1) -1 +1 MI (3) Rw(n)(actual)–Rw(n)(expected) Relative linearity (2) -0.2 +0.2 MI (3) Rw(n + 1)–[Rw(n) + MI] Temperature coefficient of RTOTAL ±300 ppm/ °C Ratiometric temp. coefficient ±20 ppm/°C CH/CL/CW Potentiometer capacitances 10/10/25 pF See Spice Macromodel IAL RH, RL, RW leakage current 0.1 10 µA V IN = VSS to VCC. Device is in stand-by mode.

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (Active) 400 µA f SCK = 2MHz, SO = Open, Other Inputs = VSS ICC2 VCC supply current (Nonvol- atile Write) 1m A f SCK = 2MHz, SO = Open, Other Inputs = VSS ISB VCC current (standby) 1 µA SCK = SI = V SS, Addr. = VSS ILI Input leakage current 10 µA V IN = VSS to VCC ILO Output leakage current 10 µA V OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 0.5 V VIL Input LOW voltage –0.5 V CC x 0.1 V VOL Output LOW voltage 0.4 V I OL = 3mA Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Unit Test Conditions COUT (4) Output capacitance (SO) 8 pF V OUT = 0V CIN (4) Input capacitance (A0, A1, SI, and SCK) 6 pF V IN = 0V Symbol Parameter Min. Max. Unit tPUR (5) Power-up to initiation of read operation 1 ms tPUW (5) Power-up to initiation of write operation 5 ms tR VCC (4) VCC Power up ramp 0.2 50 V/msec POWER UP REQUIREMENTS (Power Up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC, then the potentiometer pins, R H, R L, and R W. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The V CC ramp rate specifi- cation should be met, and any glitches or slope changes in the V CC line should be held to <100mV if possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for proper wiper register recall. Also, V CC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until V CC, V+ and V- reach their final value. EQUIVALENT A.C. LOAD CIRCUIT 1533Ω 100pF SDA Output

A.C. TEST CONDITIONS Notes: (4) This parameter is periodically sampled and not 100% tested (5) t PUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. SPICE Macro Model SYMBOL TABLE Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 10pF RH RTOTAL CH 25pF CW CL 10pF RW RL WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance AC TIMING Symbol Parameter Min. Max. Unit fSCK SSI/SPI clock frequency 2.0 MHz tCYC SSI/SPI clock cycle time 500 ns tWH SSI/SPI clock high time 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs tDIS SO output disable time 0 500 ns tV SO output valid time 100 ns tHO SO output hold time 0 ns tRO SO output rise time 50 ns tFO SO output fall time 50 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in High Z 100 ns tLZ HOLD high to output in Low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns tCS CS deselect time 2 µs tWPASU WP, A0 and A1 setup time 0 ns tWPAH WP, A0 and A1 hold time 0 ns

HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING TIMING DIAGRAMS Input Timing Output Timing Symbol Parameter Typ. Max. Unit tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Unit tWRPO Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ...

XDCP Timing (for All Load Instructions) XDCP Timing (for Increment/Decrement Instruction) ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO ... CS SCK SI MSB LSB VW/RW tWRL ... SO High Impedance ... CS SCK SO SI ADDR tWRID High Impedance VW/RW ...Inc/Dec Inc/Dec ...

Write Protect and Device Address Pins Timing CS WP tWPASU tWPAH (Any Instruction)

Basic Configurations of Electronic Potentiometers Application Circuits VR VW/RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysteresis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 100KΩ 10KΩ10KΩ 10KΩ -12V+12V TL072 –VS VO R2R1

Application Circuits (continued) Inverting Amplifier Equivalent L-R Circuit VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C Attenuator Filter VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2pRC) R4 All RS = 10kΩ VS R C VO

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.022 (0.56) 0.014 (0.36) 0.150 (3.81) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 0.110 (2.79) 0.090 (2.29) 1.265 (32.13) 1.230 (31.24) 1.100 (27.94) Ref. Pin 1 Index 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) Pin 1 Seating Plane 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.530 (13.46) 0.080 (2.03) 0.065 (1.65) 15° 24-Lead Plastic Dual In-Line Package Type P Typ. 0.010 (0.25) NOTE:

0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.598 (15.20) 0.610 (15.49) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 24-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

24 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.009 (0.22) 0.013 (0.33) 0° – 8° X 45°

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 24-Lead Plastic, TSSOP Package Type V .169 (4.3) .026 (.65) BSC .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) See Detail “A” .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) Gage Plane Seating Plane Detail A (20X) (4.16)(7.72) (1.78) (0.42) (0.65) ALL MEASUREMENTS ARE TYPICAL 0°–8°

a B A D C F E 1234 B A D C F E 1234 b Top View (Bump Side Down) Side View (Bump Side Down) Bottom View (Bump Side Up) c d e f k a j b Note: Drawing not to scale = Die Orientation mark Symbol Millimeters Inches Nominal Min. Max. Nominal Min. Max. Total Ball Count g 24 Ball Count X Axis h 4 Ball Count Y Axis i 6 Pins Pitch XAxis j 0.5 Pins Pitch Y Axis k 0.5 Edge to Ball Center (Corner) Distance Edge to Ball Center (Corner) Distance l m

Characteristics subject to change without notice. 22 of 22 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2000 Patents Pending REV 1.1.4 10/11/02 www.xicor.com

Ordering Information

X9400WZ24I-2.7 XABM X9400WZ24 XABN X9400YZ24 XABZ X9400YZ24I-2.7 XABY Device VCC Limits Blank = 5V ±10% –2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S24 = 24-Lead SOIC V24 = 24-Lead TSSOP Z24 = 24-Lead XBGA (production quantity sold in tape and reel) Potentiometer Organization Pot 0 Pot 1 Pot 2 Pot 3 W = 10K Ω 10KΩ 10KΩ 10KΩ Y = 2.5K Ω 2.5KΩ 2.5KΩ 2.5KΩ X9400 P T V Y