X93254_08 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Dual solid-state potentiometers
  • Independent Up/Down interfaces
  • 32 wiper tap points per potentiometer - Wiper position stored in nonvolatile memory and recalled on power-up
  • 31 resistive elements per potentiometer - Temperature compensated - Maximum resistance tolerance of ± 30% - Terminal voltage, 0 to V CC
  • Low power CMOS -V CC = 3V ±10% - Active current, 250µA max - Standby current, 1µA max
  • High reliability - Endurance 200,000 data changes per bit - Register data retention, 100 years TOTAL value = 50kΩ
  • 14 Ld TSSOP package VCC CS1 INC2 U/D2 RH2 VSS RL1 DNC* *Do not connect. CS2 INC1 U/D1 RH1 RL2 DNC*

Ordering Information

PART NUMBER PART MARKING V CC LIMITS (V) R TOTAL (kΩ) TEMP RANGE (°C) PACKAGE PKG DWG. # X93254UV141-3 X9325 4UVE 3 ±10% 50 -40 to +85 14 Ld TSSOP M14.173 Data Sheet February 4, 2008

2 FN8186.1 February 4, 2008 Block Diagram CONTROL AND MEMORY UP/DOWN (U/D1) INCREMENT (INC1) DEVICE SELECT (CS1) VCC (SUPPLY VOLTAGE) VSS (Ground) RH1 RL1 30k RH2 RL2 CONTROL AND MEMORY UP/DOWN (U/D2) INCREMENT (INC2) DEVICE SELECT (CS2) 30k Pin Descriptions TSSOP SYMBOL DESCRIPTION

1 DNC Do Not Connect

8 DNC Do Not Connect

10 CS 2 Chip Select 2

11 V CC Supply Voltage

12 INC 1 Increment 1

13 U/D 1 Up/Down 1

14 R H1 High Terminal 1

3 FN8186.1 February 4, 2008 Absolute Maximum Ratings Thermal Information Voltage on CS, INC, U/D, RH, RL and VCC Recommended Operating Conditions Temperature Range Supply Voltage result in failures not covered by warranty. NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (VH(n)(actual) - VH(n)(expected)) = ±1 Ml Maximum. n = 1 .. 29 only 3. 1 Ml = Minimum Increment = R TOT/31. 4. Typical values are for TA = +25°C and nominal supply voltage. 5. Limits established by characteri zation and are not production tested. 6. When performing multiple write operations, V CC must not decrease by more than 150mV from its initial value. 7. Parts are 100% tested at +25°C. Over-temperature limi ts established by characterization and are not production tested. Potentiometer Specifications Over recommended operating conditions, unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS/NOTES MIN (Note 7) TYP (Note 4) MAX (Note 7) UNIT RTOT End-to-End Resistance 37.5 50 62.5 k Ω VR RH, RL Terminal Voltages 0 V CC V Power Rating R TOTAL = 50kΩ 1m Ω (Note 5) Noise Ref: 1kHz -120 dBV (Note 5) RW Wiper Resistance (Note 5) 1000 Ω IW Wiper Current (Note 5) 0.6 mA Resolution 3% Absolute Linearity (Note 1) V H(n)(actual) - VH(n)(expected) ±1 MI (Note 3) Relative Linearity (Note 2) V H(n+1) - [VH(n)+MI ±0.5 MI (Note 3) RTOTAL Temperature Coefficient (Note 5) ±35 ppm/°C CH/CL/CW Potentiometer Capacitances See “Circuit #2 SPICE Macro Model” on page 4 10/10/25 pF (Note 5) X93254

4 FN8186.1 February 4, 2008 Test Circuit #1 Circuit #2 SPICE Macro Model DC Operating Specifications Over recommended operating conditions unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS/NOTES MIN (Note 7) TYP (Note 4) MAX (Note 7) UNIT ICC1 VCC Active Current (Increment) per DCP CS = VIL, U/D = VIL or VIH and INC = 0.4V @ max. tCY 50 250 µA ICC2 VCC Active Current (Store) (EEPROM Store) per DCP CS = VIH, U/D = VIL or VIH and INC =V IH @ max. tWR 600 µA ISB Standby Supply Current CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V 1µ A ILI CS1 or CS2 VIN = VCC ±1 µA ILI CS1 or CS2 VCC = 3V, CS = 0 60 100 150 µA ILI INC1, INC2, U/D1, U/D2 Input Leakage Current VIN = VSS to VCC )± 1 µ A VIH CS1, CS2, INC1, INC2, U/D1, U/D2 Input HIGH Voltage VCC x 0.7 V CC + 0.5 V VIL CS1, CS2, INC1, INC2, U/D1, U/D2 Input HIGH Voltage -0.5 V CC x 0.1 V CIN CS1, CS2, INC1, INC2, U/D1, U/D2 Input Capacitance VCC = 3V, VIN = VSS, TA = +25°C, f = 1MHz (Note 5) 10 pF Endurance and Data Retention PARAMETER MIN UNIT Minimum endurance 200,000 Data changes per bit Data retention 100 Years VL TEST POINT VH/RH AC Conditions of Test Input pulse levels 0V to 3V Input rise and fall times 10ns Input reference levels 1.5V CH CL 10pF 10pF RH RTOTAL CW 25pF RL AC Operating Specifications Over recommended operating conditions, unless otherwise stated. CS, INC, U/D, RH and RL are used to refer to either CS1 or CS2, etc. SYMBOL PARAMETER MIN (Note 7) TYP (Note 4) MAX (Note 7) UNIT tCl CS to INC Setup 100 ns tlD INC HIGH to U/D Change 100 ns tDI U/D to INC Setup 100 ns tlL INC LOW Period 1 µs tlH INC HIGH Period 1 µs tlC INC Inactive to CS Inactive 1 µs tCPH CS Deselect time (No Store) 250 ns tCPH CS Deselect time (Store) 10 ms X93254

5 FN8186.1 February 4, 2008 AC Timing Power-up and Power-down Requirements There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH and VL, i.e., VCC ≥ VH,VL. The VCC ramp rate specification is always in effect. Pin Descriptions In the text, CS, INC, U/D, RH and RL are used to refer to either CS1 or CS2, etc. Note: These signals can be applied independently or at the same time. RH and RL The RH and RL pins of the X93254 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is V SS and the maximum is VCC. The terminology of RH and RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input per potentiometer. Up/Down (U/D) The U/D input controls the direction of a single potentiometer’s wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the corresponding potentiometer’s counter in the direction indicated by the logic level on the corresponding potentiometer’s U/D input. Chip Select (CS) A potentiometer is selected when the corresponding CS input is LOW. Its current counter value is stored in nonvolatile memory when the corresponding CS is returned HIGH while the corresponding INC input is also HIGH. After the store operation is complete, the affected potentiometer will be placed in the low power standby mode until the potentiometer is selected once again. Principles of Operation There are multiple sections for each potentiometer in the X93254: an input control, a counter and decode section; the nonvolatile memory; and a resistor array. Each input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions, the contents of the counter can be stored in nonvolatile memory and retained for future use. Each resistor array is comprised of 31 individual resistors tCYC INC Cycle Time 2 µs tR, tF (Note 5) INC input Rise and Fall Time 500 µs tR VCC (Note 5) VCC Power-up Rate 1 50 V/ms tWR Store Cycle 51 0 m s AC Operating Specifications Over recommended operating conditions, unless otherwise stated. CS, INC, U/D, RH and RL are used to refer to either CS1 or CS2, etc. (Continued) SYMBOL PARAMETER MIN (Note 7) TYP (Note 4) MAX (Note 7) UNIT CS INC U/D tCI tIL tIH tCYC tID tDI tIC tCPH tF tR 10% 90% 90% (STORE) Note: CS, INC, U/D, RH and RL are used to refer to either CS1 or CS2, etc. X93254

6 FN8186.1 February 4, 2008 connected in series. At either end of the array and between each resistor is an electronic switch that transfers the connection at that point to the wiper. Each wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. If the wiper is moved several positions, multiple taps are connected to the wiper for t IW (INC to VW change). The 2-terminal resistance value for the device can temporarily change by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory for each potentiometer. When power is restored, the contents of the memory are recalled and each wiper is set to the value last stored. Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the potentiometer is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a 5-bit counter. The output of this counter is decoded to select one of thirty two wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever each CS transitions HIGH while the INC input is also HIGH. In order to avoid an accidental store during power-up, each CS must go HIGH with VCC during initial power-up. When left open, each CS pin is internally pulled up to VCC by an internal 30k resistor. The system may select the X93254, move any wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as previously described and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-up/down cycle recalled the previously stored data. In order to recall the stored position of the wiper on power-up, the CS pin must be held HIGH. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, or other system trim requirements. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move each wiper up and down until the proper trim is attained. Symbol Table Applications Information Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages: 1. The variability and reliability of a solid-state potentiometer 2. The flexibility of computer-based digital controls 3. The retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data Mode Selection CS INC U/D MODE L H Wiper Up L L Wiper Down H X Store Wiper Position H X X Standby Current L X No Store, Return to Standby L H Wiper Up (not recommended) L L Wiper Down (not recommended) WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X93254

7 FN8186.1 February 4, 2008 Low Voltage High Impedance Instrumentation Amplifier Micro-Power LCD Contrast Control Single Supply Variable Gain Amplifier VR Two terminal variable resistor. Variable current I U1A 10k 50k U1C GAIN = 50k 10k 1 + 50k RTOTAL U1 = LT1467 VOUT 50k U1B 10k 50k 50k 1/2 X93254 (R TOTAL) 10k 10k VIN 3.3V U1A 100k 300k U1B 1 + 100k 50k + RTOTAL U1 = LMC6042 VOUT = -3.88 –12V100k 1/2 X93254 (R TOTAL) 240k 3.3V 100k 3.3V 50k VOUT = -2.75V TO -11.6V GAIN = RTOTAL 10k 20k 3.3V 20k 3.3V VOUT U1 = LMC6042 10k VIN 1/2 X93254 (RTOTAL) X93254

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8186.1 February 4, 2008 X93254 Thin Shrink Small Outline Plastic Packages (TSSOP) α INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7 α 0o 8o 0o 8o - Rev. 2 4/06