X93254 INTERSIL | Alldatasheet

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FN8186.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X93254 Dual Digitally Controlled Potentiometers (XDCPs™)

FEATURES

  • Dual solid-state potentiometers
  • Independent Up/Down interfaces
  • 32 wiper tap points per potentiometer —Wiper position stored in nonvolatile memory and recalled on power-up
  • 31 resistive elements per potentiometer —Temperature compensated —Maximum resistance tolerance of ± 30% —Terminal voltage, 0 to V CC
  • Low power CMOS —V CC = 3V±10% —Active current, 250µA max —Standby current, 1µA max
  • High reliability —Endurance 200,000 data changes per bit —Register data retention, 100 years TOTAL value = 50kΩ
  • 14-lead TSSOP package

DESCRIPTION

The Intersil X93254 is a dual digitally controlled poten- tiometer (XDCP). The device consists of two resistor arrays, wiper switches, a control section, and nonvola- tile memory. The wiper positions are controlled by indi- vidual Up/Down interfaces. A potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switch- ing network. The position of each wiper element is controlled by a set of independent CS , U/D, and INC inputs. The position of the wiper can be stored in non- volatile memory and then be recalled upon a subse- quent power-up operation. Each potentiometer is connected as a two-terminal variable resistor and can be used in a wide variety of applications including: – Bias and Gain control – LCD Contrast Adjustment BLOCK DIAGRAM Control and Memory Up/Down (U/D1) Increment (INC1) Device Select (CS1) VCC (Supply Voltage) VSS (Ground) RH1 RL1 30K RH2 RL2 Control and Memory Up/Down (U/D2) Increment (INC2) Device Select (CS2) 30K Data Sheet March 1, 2005

2 FN8186.0 March 1, 2005 PIN CONFIGURATION X93254 ORDERING CODES PIN DESCRIPTIONS Ordering Number RTOTAL Package Temperature Range X93254UV14I-3 50kΩ 14-lead TSSOP package -40°C to +85°C TSSOP Symbol Description 1 DNC Do Not Connect. 2R L1 Low Terminal 1. 3C S 1 Chip Select 1. 4I N C 2 Increment 2. 5U / D 2 Up/Down 2. 6R H2 High Terminal 2. 7V SS Ground. 8 DNC Do Not Connect. 9R L2 Low Terminal 2. 10 CS 2 Chip Select 2. 11 V CC Supply Voltage. 12 INC 1 Increment 1. 13 U/D 1 Up/Down 1. 14 R H1 High Terminal 1. VCC CS1 INC2 U/D2 RH2 VSS X93254 TSSOP RL1 DNC* *Do not connect. CS2 INC1 U/D1 RH1 RL2 DNC* X93254

3 FN8186.0 March 1, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on CS , INC, U/D, RH, RL and VCC COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specifi- cation) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determi ne actual wiper voltage versus expected voltage = (VH(n)(actual) - VH(n)(expected)) = ±1 Ml Maximum. n = 1 .. 29 only (2) Relative linearity is a measure of the error in step size between taps = VH(n+1) - [VH(n) + Ml] = ±0.5 Ml, n = 1 .. 29 only. (3) 1 Ml = Minimum Increment = R TOT/31. (4) Typical values are for T A = 25°C and nominal supply voltage. (5) This parameter only applies to a single potentiometer. (6) This parameter is guaranteed by characterization. (7) When performing multiple write operations, V CC must not decrease by more than 150mV from its initial value. Symbol Parameter Limits Test Conditions/NotesMin. Typ. Max. Unit RTOT End to end resistance 37.5 50 62.5 k Ω (5) VR RH, RL terminal voltages 0 V CC V( 5 ) Power rating 1 mW (6) RTOTAL = 50kΩ(5) Noise -120 dBV (6) Ref: 1kHz(5) RW Wiper Resistance 1000 Ω (5) (6) IW Wiper Current 0.6 mA (5) (6) Resolution 3 % (5) Absolute linearity (1) ±1 MI (3) VH(n)(actual) - VH(n)(expected)(5) Relative linearity(2) ±0.5 MI (3) VH(n+1) - [VH(n)+MI(5) RTOTAL temperature coefficient ±35 ppm/°C (5) (6) CH/CL/CW Potentiometer capacitances 10/10/25 pF See circuit #2 (5) RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Industrial -40 °C+ 8 5 °C Supply Voltage (VCC) L i m i t s X93254 3V ± 10%(7) X93254

4 FN8186.0 March 1, 2005 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION A.C. CONDITIONS OF TEST Symbol Parameter Limits Unit Test ConditionsMin. Typ. (4) Max. ICC1 VCC active current (Increment) per DCP 50 250 µA CS = VIL, U/D = VIL or VIH and INC = 0.4V @ max. tCY(5) ICC2 VCC active current (Store) (EEPROM Store) per DCP 600 µA CS = VIH, U/D = VIL or VIH and INC = VIH @ max. tWR(5) ISB Standby supply current 1 µA CS = VCC – 0.3V, U/D and INC = VSS or VCC - 0.3V ILI CS1 or CS2 ±1 µA V IN = VCC (5) ILI CS1 or CS2 60 100 150 µA V CC = 3V, CS = 0(5) ILI INC1, INC2, U/D1, U/D2 input leakage current ±1 µA V IN = VSS to VCC(5) VIH CS1, CS2, INC1, INC2, U/D1, U/D2 input HIGH voltage VCC x 0.7 V CC + 0.5 V (5) VIL CS1, CS2, INC1, INC2, U/D1, U/D2 input HIGH voltage -0.5 V CC x 0.1 V (5) CIN CS1, CS2, INC1, INC2, U/D1, U/D2 input capacitance 10 pF V CC = 3V, VIN = VSS, TA = 25°C, f = 1MHz(6) Parameter Min. Unit Minimum endurance 200,000 Data changes per bit Data retention 100 Years Input pulse levels 0V to 3V Input rise and fall times 10ns Input reference levels 1.5V Test Circuit #1 Circuit #2 SPICE Macro Model VL Test Point VH/RH CH CL 10pF 10pF RH RTOTAL CW 25pF RL X93254

5 FN8186.0 March 1, 2005 A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified. In the table, CS, INC, U/D, RH and RL are used to refer to either CS1 or CS2, etc.) POWER-UP AND DOWN REQUIREMENTS There are no restrictions on the pow er-up or power-down conditions of V CC and the voltages applied to the potenti- ometer pins provided that VCC is always more positive than or equal to VH and VL, i.e., VCC ≥ VH,VL. The VCC ramp rate spec is always in effect. A.C. TIMING (In the diagram, CS, INC, U/D, RH and RL are used to refer to either CS1 or CS2, etc.) Symbol Parameter Limits UnitMin. Typ. (6) Max. tCl CS to INC setup 100 ns tlD INC HIGH to U/D change 100 ns tDI U/D to INC setup 100 ns tlL INC LOW period 1 µs tlH INC HIGH period 1 µs tlC INC Inactive to CS inactive 1 µs tCPH CS Deselect time (NO STORE) 250 ns tCPH CS Deselect time (STORE) 10 ms tCYC INC cycle time 2 µs tR, tF(6) INC input rise and fall time 500 µs tR VCC(6) VCC power-up rate 1 10,000 V/ms tWR Store cycle 5 10 ms CS INC U/D tCI tIL tIH tCYC tID tDI tIC tCPH tF tR 10% 90% 90% (Store) X93254

6 FN8186.0 March 1, 2005 PIN DESCRIPTIONS (In the text, CS, INC, U/D, RH and RL are used to refer to either CS1 or CS2, etc. Note: These signals can be applied independently or at the same time.) RH and RL The RH and RL pins of the X93254 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is VSS and the maximum is VCC. The terminology of RH and RL references the relative posi- tion of the terminal in relation to wiper movement direction selected by the U/D input per potentiometer. Up/Down (U/D) The U/D input controls the direction of a single potenti- ometer’s wiper movement and whether the counter is incremented or decremented. Increment (INC The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decre- ment the corresponding potentiometer’s counter in the direction indicated by the logic level on the corre- sponding potentiometer’s U/D input. Chip Select (CS) A potentiometer is selected when the corresponding CS input is LOW. Its current counter value is stored in non- volatile memory when the corresponding CS is returned HIGH while the corresponding INC input is also HIGH. After the store operation is complete the affected poten- tiometer will be placed in the low power standby mode until the potentiometer is selected once again. PRINCIPLES OF OPERATION There are multiple sections for each potentiometer in the X93254: an input control, a counter and decode section; the nonvolatile memory; and a resistor array. Each input control sect ion operates just like an up/down counter. The outp ut of this counter is decoded to turn on a single electronic switch connect- ing a point on the resistor array to the wiper output. Under the proper condition s the contents of the counter can be stored in nonvolatile memory and retained for future use. Each resistor array is com- prised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that tran sfers the connection at that point to the wiper. Each wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. If the wiper is moved seve ral positions, multiple taps are connected to the wiper for t IW (INC to V W change). The 2-terminal resistance value for the device can temporarily change by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper posi- tion stored will be maintain ed in the nonvolatile mem- ory for each potentiometer. When power is restored, the contents of the memo ry are recalled and each wiper is set to the value last stored. INSTRUCTIONS AND PROGRAMMING The INC , U/D and CS inputs control the movement of the wiper along the resi stor array. With CS set LOW the potentiometer is select ed and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a five bit counter. The output of this counter is decoded to select one of thirty two wiper positions along the resistive array. The value of the counter is stored in nonvolatile mem- ory whenever each CS transitions HIGH while the INC input is also HIGH. In order to avoid an accidental store during power-up, each CS must go HIGH with VCC dur- ing initial power-up. When left open, each CS pin is internally pulled up to VCC by an internal 30K resistor. The system may select the X93254, move any wiper and deselect the device without having to store the lat- est wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-up/down cycle recall ed the previously stored data. In order to recall the stored position of the wiper on power-up, the CS pin must be held HIGH. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user pref- erence, system parameter changes due to tempera- ture drift, or other system trim requirements. X93254

7 FN8186.0 March 1, 2005 The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move each wiper up and down until the proper trim is attained. MODE SELECTION SYMBOL TABLE CS INC U/D Mode L H Wiper Up L L Wiper Down H X Store Wiper Position H X X Standby Current L X No Store, Return to Standby L H Wiper Up (not recommended) L L Wiper Down (not recommended) WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X93254

8 FN8186.0 March 1, 2005 APPLICATIONS INFORMATION Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Low Voltage High Impedance Instrumentation Amplifier Micro-Power LCD Contrast Control VR Two terminal variable resistor. I U1A 10K 50K U1C Gain = 50K 10K 1 + 50K RTOTAL)( U1 = LT1467 VOUT 50K U1B 10K 50K 50K 1/2 X93254 (RTOTAL) 10K 10K VIN 3.3V U1A 100K 300K U1B 1 + 100K 50K + RTOTAL)( U1 = LMC6042 VOUT = -3.88 –12V100K 1/2 X93254 (RTOTAL) 240K 3.3V 100K 3.3V 50K VOUT = -2.75V to -11.6V X93254

9 FN8186.0 March 1, 2005 APPLICATIONS INFORMATION (Continued) Single Supply Variable Gain Amplifier Gain = RTOTAL 10K 20K 3.3V 20K 3.3V VOUT U1 = LMC6042 10K VIN 1/2 X93254 (RTOTAL) X93254

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8186.0 March 1, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-Lead Plastic, TSSOP, Package Code V14 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X93254