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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 12
Technical content
Features
- Solid-state potentiometer
- 3-wire serial interface
- 32 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up
- 31 resistive elements - Temperature compensated - End-to-end resistance range ±20% - Terminal voltages, -V CC to +VCC
- Low power CMOS -V CC = 3V or 5V - Active current, 3mA max. - Standby current, 500µA max.
- High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years TOTAL values = 1k, 10k, 50k
- Packages - 8 Ld SOIC, 8 Ld MSOP and 8 Ld PDIP
- Pb-free available (RoHS compliant) Block Diagram 5-BIT NONVOLATILE MEMORY STORE AND RECALL CONTROL CIRCUITRY ONE OF OUTPUTS RESISTOR ARRAY RH/VHU/D INC CS TRANSFER GATES THIRTY-TWO VCC VSS RL/VL RW/VW CONTROL UP/DOWN VCC (SUPPLY VOLTAGE) VSS (GROUND) RH/VH RW/VW RL/VL GENERAL DETAILED (U/D) INCREMENT (INC) DEVICE SELECT (CS) AND MEMORY 5-BIT UP/DOWN COUNTER TIME DECODER ACTIVE AT A
FN8177 Rev 7.00 Page 2 of 12 October 7, 2015 Pin Descriptions RH/VH and RL/VL The high (RH/VH) and low (RL/VL) terminals of the X9313 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL/VL and RH/VH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW/VW RW/VW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40 at VCC = 5V. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input.
Ordering Information
(V) RTOTAL (k) TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. # X9313UMIZ* (Note) DDB 4.5 to 5.5 50 -40 to +85 8 Ld MSOP (Pb-free) M8 .118 X9313USZ* (Note) X9313U Z 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313USIZ* (Note) X9313U ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15 X9313WMZ* (Note) DDF 10 0 to +70 8 Ld MSOP (Pb-free) M8.118 X9313WMIZ* (Note) DDE -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313WPIZ X9313WP ZI -40 to +85 8 Ld PDIP*** (Pb-free) MDP0031 X9313WSZ* (Note) X9313W Z 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313WSIZ* (Note) X9313WS ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15 X9313ZMZ* (Note) DDJ 1 0 to +70 8 Ld MSOP (Pb-free) M8.118 X9313ZMIZ* (Note) DDH -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313ZSZ* (Note) X9313 Z 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313ZSIZ* (Note) X9313ZS ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15 X9313UMZ* (Note) DDC 3 to 5.5 50 0 to +70 8 Ld MSOP M8.118 X9313UMZ-3* (Note) DDD 3 to 5.5 50 0 to +70 8 Ld MSOP M8.118 X9313UMIZ-3* (Note) 13UEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313USZ-3* (Note) X9313U ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313WMZ-3* (Note) DDG 10 0 to +70 8 Ld MSOP (Pb-free) M8.118 X9313WMIZ-3* (Note) 13WEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313WSZ-3* (Note) X9313W ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313ZMZ-3* (Note) DDK 1 0 to +70 8 Ld MSOP (Pb-free) M8.118 X9313ZMIZ-3* (Note) 13ZEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313ZSZ-3* (Note) X9313Z ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313ZSIZ-3* (Note) X9313Z ZE -40 to +85 8 Ld SOIC (Pb-free) M8.15 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. Add "T2" suffix for tape and reel. Please refer to TB347 for details on reel specifications. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
standby mode until the device is selected once again. transfers the potential at that point to the wiper. significant amount if the wiper is moved several positions. the wiper is set to the value last stored. selected and enabled to respond to the U/D and INC inputs. (depending on the state of the U/D input) a seven bit counter. wiper positions along the resistive array. changes due to temperature drift, etc. wiper up and down until the proper trim is attained. TABLE 1. PIN NAMES TABLE 2. MODE SELECTION
TABLE 2. MODE SELECTION
FN8177 Rev 7.00 Page 5 of 12 October 7, 2015 Absolute Maximum Ratings Reco mmended Operating Conditions Voltage on CS, INC, U/D, and Voltage on VH, VL, VW V = |VH - VL|: ESD Rating Temperature: Supply Voltage (VCC): Power rating: http://www.intersil.com/pbfree/Pb-FreeReflow.asp Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Potentiometer Characteristics Over recommended operating conditions, unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP MAX End-to-end Resistance Tolerance ±20 % VVH VH Terminal Voltage - VCC +VCC V VVL VL Terminal Voltage - VCC +VCC V RW Wiper Resistance I W = (VH - VL)/RTOTAL, VCC = 5V 40 100 IW Wiper Current ±4.4 mA Noise (Note 5) Ref: 1kHz -120 dBV Resolution 3% Absolute Linearity (Note 1) R W(n)(actual) - RW(n)(expected) ±1 MI (Note 3) Relative Linearity (Note 2) R W(n+1) - (RW(n)+MI) ±0.2 MI (Note 3) RTOTAL Temperature Coefficient (Note 5) ±300 ppm/°C Ratiometric Temperature Coefficient (Note 5) ±20 ppm/°C CH/CL/CW (Note 5) Potentiometer Capacitances See Circuit #3 10/10/25 pF NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (VW(n)(actual) - VW(n)(expected)) = ±1 MI maximum. 2. Relative linearity is a measure of the error in step size between taps = RW(n+1) - (RW(n) + MI) = ±0.2 MI. 3. 1 MI = minimum increment = RTOT/31.
FIGURE 1. TEST CIRCUIT #1 FIGURE 2. TEST CIRCUIT #2 FIGURE 3. CIRCUI T #3 SPICE MACRO
INC high before or concurrently with the VCC pin on power-up.
- Typical values are for TA = +25°C and nominal supply voltage.
- This parameter is not 100% tested.
FIGURE 4. AC TIMING DIAGRAM
FN8177 Rev 7.00 Page 8 of 12 October 7, 2015 Applications Information Electronic digitally controlled potentiometers (XDCP) provide three powerful application advantages: 1. The variability and reliability of a solid-state potentiometer. 2. The flexibility of computer-based digital controls. 3. The retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Basic Configurations of Electronic Potentiometers Basic Circuits VR VW/RW VR I THREE-TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO-TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT VH VL CASCADING TECHNIQUESBUFFERED REFERENCE VOLTAGE +5V -5V VW VREF VOUT OP-07 VW VW/RW +V +V X (a) (b) VOUT = VW/RW NONINVERTING AMPLIFIER VS VO VO = (1 + R2/R1)VS LM308A VOLTAGE REGULATOR Iadj VO (REG) = 1.25V (1 + R2/R1) + IADJ R2 VO (REG)VIN 317 OFFSET VOLTAGE ADJUSTMENT VS VO R2R1 100k 10k10k 10k -12V+12V TL072 COMPARATOR WITH HYSTERESIS VUL = [R1/(R1 + R2)] VO(max) VLL = [R1/(R1 + R2)] VO(min) –VS VO R2R1 LT311A +5V -5V (FOR ADDITIONAL CIRCUITS SEE AN115)
FN8177 Rev 7.00 Page 9 of 12 October 7, 2015 About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 7, 2015 FN8177.7 Added Revision History beginning with Re v 7. Added About Intersil Verbiage. Updated Ordering Information on page 2. CC for Parameter VCC Active Current to ISB Updated POD M8.118 to most current revision with changes as follows: Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36" Updated to new intersil format by adding land pattern and moving dimensions from table onto drawing. Updated POD M8.15 to most current revision with changes as follows: Changed Note 1 "1982" to "1994" Changed in Typical Recommended Land Pattern the following: 0.200 to 5.20(0.205) Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern.
FN8177 Rev 7.00 Page 10 of 12 October 7, 2015 Package Outline Drawing M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11 DETAIL "X" SIDE VIEW 2 TYPICAL RECOMMENDED LAND PATTERN TOP VIEW PIN# 1 ID 0.25 - 0.36 DETAIL "X" 0.10 ± 0.05 (4.40) (3.00) (5.80) H C
1.10 MAX
0.09 - 0.20 3°±3° GAUGE PLANE 0.25
0.95 REF
0.55 ± 0.15 B
0.08 C A-B D
3.0±0.05 0.85±010 SEATING PLANE A
0.65 BSC
3.0±0.05 4.9±0.15 (0.40) (1.40) (0.65) D SIDE VIEW 1 Dimensioning and tolerancing conform to JEDEC MO-187-AA Plastic interlead protrusions of 0.15mm max per side are not Dimensions in ( ) are for reference only. Dimensions are measured at Datum Plane "H". Plastic or metal protrusions of 0.15mm max per side are not Dimensions are in millimeters. NOTES: and AMSEY14.5m-1994. included. included. 0.10 CM
FN8177 Rev 7.00 Page 11 of 12 October 7, 2015 Package Outline Drawing M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12 DETAIL "A" TOP VIEW INDEX AREA 12 3 -C- SEATING PLANE x 45° NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. SIDE VIEW “A SIDE VIEW “B” 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 4 5 TYPICAL RECOMMENDED LAND PATTERN 2.20 (0.087) 0.60 (0.023)
FN8177 Rev 7.00 Page 12 of 12 October 7, 2015 X9313 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Plastic Dual-In-Line Packages (PDIP) MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL INCHES TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20 N 8 14 16 18 20 Reference Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1
12 N / 2
E eB eA c