X9313_07 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Solid-state potentiometer
- 3-wire serial interface
- 32 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up
- 31 resistive elements - Temperature compensated - End to end resistance range ±20% - Terminal voltages, -V CC to +VCC
- Low power CMOS -V CC = 3V or 5V - Active current, 3mA max. - Standby current, 500µA max.
- High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years TOTAL values = 1kΩ, 10kΩ, 50kΩ
- Packages - 8 Ld SOIC, 8 Ld MSOP and 8 Ld PDIP
- Pb-free plus anneal available (RoHS compliant) Block Diagram 5-BIT NONVOLATILE MEMORY STORE AND RECALL CONTROL CIRCUITRY ONE OF OUTPUTS RESISTOR ARRAY RH/VHU/D INC CS TRANSFER GATES THIRTY-TWO VCC VSS RL/VL RW/VW CONTROL UP/DOWN VCC (SUPPLY VOLTAGE) VSS (GROUND) RH/VH RW/VW RL/VL GENERAL DETAILED (U/D) INCREMENT (INC) DEVICE SELECT (CS) AND MEMORY 5-BIT UP/DOWN COUNTER TIME DECODER ACTIVE AT A Data Sheet April 18, 2007
2 FN8177.5 April 18, 2007
Ordering Information
(V) RTOTAL (kΩ) TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. # X9313UMI 13UI 4.5 to 5.5 50 -40 to +85 8 Ld MSOP M8.118 X9313UMIZ (Note) DDB -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313UP X9313UP 0 to +70 8 Ld PDIP MDP0031 X9313US* X9313U 0 to +70 8 Ld SOIC MDP0027 X9313USZ* (Note) X9313U Z 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313USI X9313U I -40 to +85 8 Ld SOIC MDP0027 X9313USIZ (Note) X9313U ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15 X9313WMZ (Note) DDF 10 0 to +70 8 Ld MSOP (Pb-free) M8.118 X9313WMI* 13WI -40 to +85 8 Ld MSOP M8.118 X9313WMIZ* (Note) DDE -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313WP X9313WP 0 to +70 8 Ld PDIP MDP0031 X9313WPZ-3 X9313WP ZD -40 to +85 8 Ld PDIP* (Pb-free) MDP0031 X9313WPI X9313WP I -40 to +85 8 Ld PDIP MDP0031 X9313WPIZ X9313WP ZI -40 to +85 8 Ld PDIP* (Pb-free) MDP0031 X9313WS* , ** X9313WS 0 to +70 8 Ld SOIC MDP0027 X9313WSZ*, ** (Note) X9313W Z 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313WSI* X9313WS I -40 to +85 8 Ld SOIC MDP0027 X9313WSIZ* (Note) X9313WS ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15 X9313ZM 313Z 0 to +70 8 Ld MSOP M8.118 X9313ZMZ (Note) DDJ 0 to +70 8 Ld MSOP (Pb-free) M8.118 X9313ZMI* , ** 13ZI 1 -40 to +85 8 Ld MSOP M8.118 X9313ZMIZ*, (Note) DDH -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313ZP X9313ZP 0 to +70 8 Ld PDIP MDP0031 X9313ZPI X9313ZP I -40 to +85 8 Ld PDIP MDP0031 X9313ZPIZ (Note) X9313ZP ZI -40 to +85 8 Ld PDIP* (Pb-free) MDP0031 X9313ZS* , ** X9313ZS 0 to +70 8 Ld SOIC MDP0027 X9313ZSZ*, ** (Note) X9313 Z 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313ZSI* X9313ZS I -40 to +85 8 Ld SOIC MDP0027 X9313ZSIZ* (Note) X9313ZS ZI -40 to +85 8 Ld SOIC (Pb-free) M8.15 X9313UM-3T1 13UD 3 to 5.5 50 0 to +70 8 Ld MSOP Tape and Reel M8.118 X9313UMZ-3T1 (Note) DDD 0 to +70 8 Ld MSOP Tape and Reel (Pb-free) M8.118 X9313UMI-3* 13UE -40 to +85 8 Ld MSOP M8.118 X9313UMIZ-3* (Note) 13UEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313US-3* , ** X9313U D 0 to +70 8 Ld SOIC MDP0027 X9313USZ-3*, ** (Note) X9313U ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313WM-3* 13WD 10 0 to +70 8 Ld MSOP M8.118 X9313WMZ-3* (Note) DDG 0 to +70 8 Ld MSOP (Pb-free) M8.118 X9313WMI-3* 13WE -40 to +85 8 Ld MSOP M8.118 X9313
3 FN8177.5 April 18, 2007 Pin Descriptions RH/VH and RL/VL The high (RH/VH) and low (RL/VL) terminals of the X9313 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL/VL and RH/VH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW/VW RW/VW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40Ω at V CC = 5V. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9313 will be placed in the low power standby mode until the device is selected once again. X9313WMIZ-3* (Note) 13WEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313WS-3* X9313W D 0 to +70 8 Ld SOIC MDP0027 X9313WSZ-3* (Note) X9313W ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313ZM-3* 13ZD 3 to 5.5 1 0 to +70 8 Ld MSOP M8.118 X9313ZMZ-3* (Note) DDK 0 to +70 8 Ld MSOP (Pb-free) M8.118 X9313ZMI-3* 13ZE -40 to +85 8 Ld MSOP M8.118 X9313ZMIZ-3* (Note) 13ZEZ -40 to +85 8 Ld MSOP (Pb-free) M8.118 X9313ZP-3 X9313ZP D 0 to +70 8 Ld PDIP MDP0031 X9313ZPZ-3 (Note) X9313ZP ZD 0 to +70 8 Ld PDIP (Pb-free)*** MDP0031 X9313ZS-3* X9313Z D 0 to +70 8 Ld SOIC MDP0027 X9313ZSZ-3* (Note) X9313Z ZD 0 to +70 8 Ld SOIC (Pb-free) M8.15 X9313ZSI-3* X9313Z E -40 to +85 8 Ld SOIC MDP0027 X9313ZSIZ-3* (Note) X9313Z ZE -40 to +85 8 Ld SOIC (Pb-free) M8.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel. Add "T2" suffix for tape and reel. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Ordering Information (Continued) PART NUMBER PART MARKING VCC RANGE (V) RTOTAL (kΩ) TEMPERATURE RANGE (°C) PACKAGE PKG. DWG. # Pinouts X9313
8 LD PDIP, 8 LD SOIC
8 LD MSOP
a significant amount if the wiper is moved several positions. and the wiper is set to the value last stored. one of thirty-two wiper positions along the resistive array. recalled the previously stored data. parameter changes due to temperature drift, etc. may be changed while CS remains LOW. move the wiper up and down until the proper trim is attained. TABLE 1. PIN NAMES TABLE 2. MODE SELECTION
5 FN8177.5 April 18, 2007 Absolute Maximum Ratings Recommended Operating Conditions Voltage on CS, INC, U/D, and Voltage on VH, VL, VW ΔV = |VH - VL|: I ESD Rating Temperature: Supply Voltage (VCC): Power rating: R http://www.intersil.com/pbfree/Pb-FreeReflow.asp Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for us e in Reflow solder processing
applications
CAUTION: Stresses above those listed under “Absolute Maximum Rati ngs” may cause permanent damage to the device. This is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Potentiometer CharacteristicsOver recommended operating conditions unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS/NOTES LIMITS UNITMIN TYP MAX End-to-end resistance tolerance ±20 % VVH VH terminal voltage - VCC +VCC V VVL VL terminal voltage - VCC +VCC V RW Wiper resistance I W = (VH - VL)/RTOTAL, VCC = 5V 40 100 Ω IW Wiper current ±4.4 mA Noise (Note 5) Ref: 1kHz -120 dBV Resolution 3% Absolute linearity (Note 1) R W(n)(actual) - RW(n)(expected) ±1 MI (Note 3) Relative linearity (Note 2) R W(n+1) - (RW(n)+MI) ±0.2 MI (Note 3) RTOTAL temperature coefficient (Note 5) ±300 ppm/°C Ratiometric temperature coefficient (Note 5) ±20 ppm/°C CH/CL/CW (Note 5) Potentiometer capacitances See Circuit #3 10/10/25 pF NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (VW(n)(actual) - VW(n)(expected)) = ±1 MI maximum. 2. Relative linearity is a measure of the error in step size between taps = R W(n+1) - (RW(n) + MI) = ±0.2 MI. 3. 1 MI = minimum increment = R TOT/31. X9313
DC Operating Characteristics Over recommended operating conditions unless otherwise stated. FIGURE 1. TEST CIRCUIT #1 FIGURE 2. TEST CI RCUIT #2 FIGURE 3. CIRCUIT #3 SPICE MACRO
before or concurrently with the VCC pin on power-up. AC Operating Characteristics Over recommended operating conditions unless otherwise stated.
- Typical values are for TA = +25°C and nominal supply voltage.
- This parameter is not 100% tested.
FIGURE 4. AC TIMING DIAGRAM
8 FN8177.5 April 18, 2007 Applications Information Electronic digitally controlled potentiometers (XDCP) provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Basic Configurations of Electronic Potentiometers Basic Circuits VR VW/RW VR I THREE-TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO-TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT VH VL CASCADING TECHNIQUESBUFFERED REFERENCE VOLTAGE +5V -5V VW VREF VOUT OP-07 VW VW/RW +V +V X (a) (b) VOUT = VW/RW NONINVERTING AMPLIFIER VS VO VO = (1 + R2/R1)VS LM308A VOLTAGE REGULATOR Iadj VO (REG) = 1.25V (1 + R2/R1) + IADJ R2 VO (REG)VIN 317 OFFSET VOLTAGE ADJUSTMENT VS VO R2R1 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 COMPARATOR WITH HYSTERESIS VUL = [R1/(R1 + R2)] VO(max) VLL = [R1/(R1 + R2)] VO(min) –VS VO R2R1 LT311A +5V -5V (FOR ADDITIONAL CIRCUITS SEE AN115) X9313
9 FN8177.5 April 18, 2007 X9313 Mini Small Outline Plastic Packages (MSOP) NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M -1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums and to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimen- sions are for reference only. L 0.25 (0.010) R 4X θ 4X θ GAUGE PLANE SEATING PLANE EE1 N TOP VIEW INDEX AREA -C- -B- 0.20 (0.008) A B C SEATING PLANE 0.20 (0.008) C 0.10 (0.004) C -A--H- SIDE VIEW b e D A -B- END VIEW0.20 (0.008) C D CL C a - H - -A - - B - - H - M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e 0.026 BSC 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N8 8 7 R 0.003 - 0.07 - - o 15o 5o 15o - α 0o 6o 0o 6o - Rev. 2 01/03
10 FN8177.5 April 18, 2007 X9313 Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05
11 FN8177.5 April 18, 2007 X9313 Small Outline Package Family (SO) GAUGE PLANE A1 L DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM CA0.004 C
0.010 BM CA
B D (N/2)1 E1E NN (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL INCHES TOLERANCE NOTESSO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M -1994
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8177.5 April 18, 2007 X9313 Plastic Dual-In-Line Packages (PDIP) MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL INCHES TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20 N 8 14 16 18 20 Reference Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. D L A e b NOTE 5 SEATING PLANE L N PIN #1 INDEXE1
12 N / 2
E eB eA c