X9279UV14I

X9279 RENESAS | Alldatasheet

Document overview

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• PDF pages: 18

Technical content

Features

• 256 Resistor Taps
• 2-Wire Serial Interface fo r Write, Read, and Transfer Operations of the Potentiometer
• Wiper Resistance, 100  Typical @ 5V
• 16 Non-volatile Data Registers for Each Potentiometer
• Non-volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on Power-up.
• Standby Current < 5µA Max CC: 2.7V to 5.5V Operation
• 5 0 k, 100k Versions of End-to-End Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
• 14 Ld TSSOP
• Low Power CMOS
• Pb-Free Available (RoHS Compliant) Functional Diagram 256-TAPS 50k and 100k RH RLRW POT VCC VSS 2-WIRE BUS WIPER INTERFACE POWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS

16 BYTES

Data Sheet September 23, 2009OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT ISL95810, ISL95811

2 FN8175.4 September 23, 2009

Ordering Information

(V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (°C) PACKAGE PKG. DWG. # X9279TV14* (Note 2) X9279 TV 5 ±10% 100 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9279TV14Z* (Note 1) X9279 TVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279TV14I* (Note 2) X9279 TVI -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9279TV14IZ* (Note 1) X9279 TVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279UV14* (Note 2) X9279 UV 50 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9279UV14Z* (Note 1) X9279 UVZ 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279UV14I* (Note 2) X9279 UVI -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9279UV14IZ* (Note 1) X9279 UVZI -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279TV14-2.7* (Note 2) X9279 TVF 2.7 to 5.5 100 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9279TV14Z-2.7* (Note 1) X9279 TVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279TV14I-2.7* (Note 2) X9279 TVG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9279TV14IZ-2.7* (Note 1) X9279 TVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279UV14-2.7* (Note 2) X9279 UVF 50 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9279UV14Z-2.7* (Note 1) X9279 UVZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 X9279UV14I-2.7* (Note 2) X9279 UVG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9279UV14IZ-2.7* (Note 1) X9279 UVZG -40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged pr oducts employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Not recommended for new designs. X9279

3 FN8175.4 September 23, 2009 Detailed Functional Diagram Circuit Level Applications

• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltag e of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DA T A RW INTERFACE AND CONTROL CIRCUITRY VCC VSS 256-TAPS 50k and 100k BANK 0 BANK 1 BANK 2 BANK 3

12 ADDITIONAL NON-VOLATILE REGISTERS

3 BANKS OF 4 REGISTERS x 8-BITS

4 FN8175.4 September 23, 2009 Pinout X9279 (14 LD TSSOP) TOP VIEW Pin Functions Pin Descriptions Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by 2-Wire master to supply 2-Wire serial clock to the X9279. DEVICE ADDRESS (A3 - A0) The Address inputs A2 - A0 are used to set the least significant 3 bits of the 8-bit slave address, address pin A3 must be connected to ground for proper operation. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9279. A maximum of 8 devices may occupy the 2-Wire serial bus. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins NO CONNECT No connect pins should be left open. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents non-volatile writes to the Data Registers. Principles Of Operation The X9279 is a integrated microcircuit incorporating a resistor array and associated registers and counter and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following:

• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description Array Description The X9279 is comprised of a resistor array (see Figure 1). The array contains, in effect, 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (see Table 1). The WCR may be written directly. These Data Registers can the WCR can be read and written by the host system. PIN TSSOP SYMBOL FUNCTION

1 NC No Connect

2 A0 Device Address for 2-Wire bus

3 NC No Connect

4 A2 Device Address for 2-Wire bus

5 SCL Serial Clock for 2-Wire bus

6 SDA Serial Data Input/Output for 2-Wire bus

8 WP Hardware Write Protect

9 A1 Device Address for 2-Wire bus

10 A3 Device Address for 2 wire-bus. Must be connected to Ground

11 R W Wiper Terminal of the Potentiometer

12 R H High Terminal of the Potentiometer

13 R L Low Terminal of the Potentiometer

14 V CC System Supply Voltage

the master can then proceed with the next operation. this is fixed as 0101[B] (refer to Table 3). The A[2:0] bits in the ID byte is the internal slave address. POT selection; since the X9279 is single POT, the P0 = 0. The format is shown in Table 4. read/write operations between the Wiper Counter Register. FIGURE 2. ACKNOWLEGE RESPONSE FROM RECEIVER

TABLE 3. IDENTIFICATION BYTE FORMAT TABLE 4. INSTRUCTION BYTE FORMAT TABLE 1. REGISTER SELECTION (R0 TO R3) TABLE 2. REGISTER BANK SELECTION (BANK 0 TO BANK 3) TABLE 5. INSTRUCTION SET

1. 1/0 = data is one or zero

decoded to select one of 256 switches along its resistor array. Register zero (DR0) upon power-up. contents are lost when the X9279 is powered-down. into the WCR. The DR0 value of Bank 0 is the default value. (DR3-DR0). These can be read or written directly by the host. non-volatile operation and will take a maximum of 10ms. Four of the seven instructions are three bytes in length.

• Read Wiper Counter Register – read the current wiper position of the potentiometer,
• Write Wiper Counter Register – change current wiper position of the potentiometer,
• Read Data Register – read the contents of the selected Data Register;
• Write Data Register – write a new value to the selected Data Register. The basic sequence of the three byte instructions is illustrated in Figure 4. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by t WRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of t WR to complete. The transfer can occur between the potentiometer and one of its four associated registers (Bank 0). Two instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9279; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the Wiper Counter Register.
• XFR Wiper Counter Register to Data Register – This transfers the contents of the Wiper Counter Register to the specified Data Register. The final command is Increment/Decrement (Figures 5 and 6). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9279 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (t HIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the R L terminal. See “Instruction Format” on page 10 for more details.

TABLE 6. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: (Used to store the current wiper position (Volatile, V) TABLE 7. DATA REGISTER, DR (8-BIT), BIT [7:0]: Used to store wiper positions or data (Non-volatile, NV)

0 A2 A0

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS

10 FN8175.4 September 23, 2009 Instruction Format Read Wiper Counter Register (WCR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Wiper Position (Sent by X9279 on SDA) M A C K S T O P 0 1 0 1 0A 2A 1A 0 10010000 W C WC WC WC WC WC WC WC Write Wiper Counter Register (WCR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Wiper Position (Sent by Master on SDA) S A C K S T O P 0101 0 A 2 A 1 A 0 1 0 1 0 0 0 0 0 W C WC WC WC WC WC WC WC Read Data Register (DR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Wiper Position (Sent by X9279 on SDA) M A C K S T O P 0 1 0 1 0A 2A 1A 0 1011R BR AP 1 P 0 W C WC WC WC WC WC WC WC Write Data Register (DR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Wiper Position (Sent by Master on SDA) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0A 2A 1A 0 1100R BR AP 1 P 0 W C WC WC WC WC WC WC WC Transfer Wiper Counter Register (WCR) to Data Register (DR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K S T O P High-Voltage Write Cycle 0 1 0 1 0A 2A 1A 0 1110 R B R A 00 Transfer Data Register (DR) to Wiper Counter Register (WCR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K S T O P 0101 0 A 2 A 1 A 0 1 1 0 1R B R A0 0 Increment/Decrement Wiper Counter Register (WCR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Increment/Decrement (Sent by Master on SDA) S T O P 0 1 0 10A 2A 1A 0 00100000 I / DI / D .... I / D I / D NOTES: 4. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. 5. “A3 ~ A0”: stands for the device addresses sent by the master. 6. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. 7. “I”: stands for the increment operation, SDA held high during active SCL phase (high). 8. “D”: stands for the decrement operation, SDA held low during active SCL phase (high). X9279

11 FN8175.4 September 23, 2009 Absolute Maximum Ratings Thermal Information Voltage on SCL, SDA any Address Input I Operating Conditions Temperature Range Supply Voltage VCC Limits (Note 13) Thermal Resistance (Typical, Note 9) JA (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 9. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Characteristics Operating Conditions over recommended industrial (2.7V) unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS RTOTAL End-to-End Resistance T version 100 k  RTOTAL End-to-End Resistance U version 50 k  End-to-End Resistance Tolerance ±20 % RW Wiper Resistance @ V = 3V I W = (VRH - VRL)/RTOTAL 300  RW Wiper Resistance @ V = 5V I W = (VRH - VRL)/RTOTAL 150  VTERM Voltage on any RH or RL Pin V SS = 0V V SS VCC V Noise Ref: 1V -120 dBV Hz Resolution 0.4 % Absolute Linearity (Note 10) R w(n)(actual) - Rw(n)(expected) (Note 14) ±1 MI (Note 12) Relative Linearity (Note 11) R w(n + 1) - [Rw(n) + MI] (Note 14) ±0.2 MI (Note 12) Temperature Coefficient of RTOTAL ±300 ppm/°C Ratiometric Temp. Coefficient ±20 ppm/°C CH/CL/CW Potentiometer Capacitances See Macro model 10/10/25 pF NOTES: 10. Absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 11. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 12. MI = RTOT / 255 or (R H - RL)/255, single pot 13. During power-up V CC > VH, VL, and VW. X9279

12 FN8175.4 September 23, 2009 SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ICC1 VCC Supply Current (Active) f SCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) 3m A ICC2 VCC Supply Current (Non-volatile Write) fSCL = 400kHz; VCC = +6V; SDA = Open (for 2-Wire, Active, Non-volatile Write State only) 5m A ISB VCC Current (Standby) V CC = +6V; VIN = VSS or VCC; SDA = VCC (for 2-Wire, Standby State only) 5µ A ILI Input Leakage Current V IN = VSS to VCC 10 µA ILO Output Leakage Current V OUT = VSS to VCC 10 µA VIH Input HIGH Voltage V CC x 0.7 V CC + 1 V VIL Input LOW Voltage -1 V CC x 0.3 V VOL Output LOW Voltage I OL = 3mA 0.4 V Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 years Capacitance SYMBOL TEST TYP UNITS TEST CONDITIONS CIN/OUT Input /Output capacitance (SDA) 8 pF V OUT = 0V CIN Input capacitance (SCL, WP, A2, A1 and A0) 6 pF V IN = 0V Power-Up Timing SYMBOL PARAMETER MIN MAX UNITS tr VCC (Note 15) VCC Power-up rate 0.2 50 V/ms tPUR (Note 16) Power-up to initiation of read operation 1 ms tPUW (Note 16) Power-up to initiation of write operation 50 ms NOTES: 15. This parameter is not 100% tested. 16. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 X9279

13 FN8175.4 September 23, 2009 Equivalent AC Load Circuit 1533 100pF SDA PIN RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACROMODEL3V 867 100pF SDA PIN AC Timing SYMBOL PARAMETER MIN MAX UNITS fSCL Clock Frequency 400 kHz tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time 0 ns tI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1200 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns High Voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNITS tWR High-voltage write cycle time (store instructions) 5 10 ms XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs X9279

14 FN8175.4 September 23, 2009 Symbol Table Timing Diagrams Start and Stop Timing Input Timing Output Timing WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance tSU:STA tHD:STA tSU:STO SCL SDA tR (START) (STOP) tF tR tF SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA X9279

15 FN8175.4 September 23, 2009 XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing Applications information Basic Configurations of Electronic Potentiometers SCL SDA VWx (STOP) LSB tWRL SDA SCL ... ... ... WP A0, A1 tSU:WPA tHD:WPA (START) (STOP) (ANY INSTRUCTION) VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current X9279

16 FN8175.4 September 23, 2009 Application Circuits NON-INVERTING AMPLIFIER VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERISIS ATTENUATOR FILTER VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 100k 10k10k 10k -12V+12V TL072 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) –VS VO R2R1 VS VO VO = G VS -1/2  G  +1/2 R4 R1 = R2 = R3 = R4 = 10k GO = 1 + R2/R1 fc = 1/(2RC) VS R C VO X9279

17 FN8175.4 September 23, 2009 INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT FUNCTION GENERATOR Application Circuits (Continued) VS VO R2R1 VO = G VS G = - R2/R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS R2C1 ZIN – R2 RA RB Frequency  R1, R2, C Amplitude  RA, RB C X9279

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8175.4 X9279 Thin Shrink Small Outline Plastic Packages (TSSOP) INDEX AREA D N 123 -B- 0.10(0.004) C AM BS e -A- b M -C- A SEATING PLANE 0.10(0.004) c E 0.25(0.010) BM M L 0.25 0.010 GAUGE PLANE NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen- sion at maximum material condition. Minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. (Angles in degrees) 0.05(0.002) M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 N1 4 1 4 7  0o 8o 0o 8o - Rev. 2 4/06