X9279TV14I-2.7

X9279 XICOR | Alldatasheet

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REV 1.1.7 2/6/03 Characteristics subject to change without notice. 1 of 24 www.xicor.com X9279 Single Digitally-Controlled (XDCP TM ) Potentiometer

FEATURES

• 256 Resistor Taps
• 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer
• Wiper Resistance, 100 Ω typical @ 5V
• 16 Nonvolatile Data Registers for Each Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power On Recall. Loads Saved Wiper Position on Power Up.
• Standby Current < 5µA Max CC : 2.7V to 5.5V Operation
• 50K Ω , 100K Ω versions of End to End Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
• 14-Lead TSSOP, 16-Lead CSP (Chip Scale Package)
• Low Power CMOS

DESCRIPTION

The X9279 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-Wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Single Supply / Low Power / 256-tap / 2-Wire Bus A PPLICATION N OTES AND D EVELOPMENT S YSTEM A V A I L A B L E AN99 • AN115 • AN124 •AN133 • AN134 • AN135 FUNCTIONAL DIAGRAM 256-taps 50KΩ and 100KΩ RH RLRW POT VCC VSS 2-Wire Bus wiper Interface Power On Recall Wiper Counter Register (WCR) Data Registers

16 Bytes

Characteristics subject to change without notice. 2 of 24REV 1.1.7 2/6/03 www.xicor.com DETAILED FUNCTIONAL DIAGRAM DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW INTERFACE AND CONTROL CIRCUITRY VCC VSS 256-taps 50KΩ and 100KΩ Bank 0 Bank 1 Bank 2 Bank 3 12 additional nonvolatile registers

3 Banks of 4 registers x 8-bits

CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication systems
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems

Characteristics subject to change without notice. 3 of 24REV 1.1.7 2/6/03 www.xicor.com PIN CONFIGURATION PIN ASSIGNMENTS Pin TSSOP Pin CSP Symbol Function

1 B2, B3 NC No Connect

2 A4 A0 Device Address for 2-Wire bus.

3 C2, C3 NC No Connect

4 B4 A2 Device Address for 2-Wire bus. 5 C4 SCL Serial Clock for 2-Wire bus. 6 D4 SDA Serial Data Input/Output for 2-Wire bus. 7D 3 V SS System Ground. 8D 2 W P Hardware Write Protect 9 D1 A1 Device Address for 2-Wire bus. 10 C1 A3 Device Address for 2 wire-bus.

11 B1 R

W Wiper Terminal of the Potentiometer.

12 A1 R

H High Terminal of the Potentiometer.

13 A2 R

L Low Terminal of the Potentiometer.

14 A3 V

System Supply Voltage. VCC RL VSS 7 8 RW SCL TSSOP RH X9279 NC NC SDA WP A0 V CC RL RH A2 NC NC R W SCL NC NC A3 SDA VSS WP A1 A B C D 4321 CSP

Characteristics subject to change without notice. 4 of 24REV 1.1.7 2/6/03 www.xicor.com PIN DESCRIPTIONS Bus Interface Pins S ERIAL D ATA I NPUT UTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. S ERIAL C LOCK (SCL) This input is used by 2-Wire master to supply 2-Wire serial clock to the X9279. D EVICE A DDRESS (A2 - A0) The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9279. A maximum of 8 devices may occupy the 2- Wire serial bus. Potentiometer Pins R H , R L The R H and R L pins are equivalent to the terminal connections on a mechanical potentiometer. R W The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins S YSTEM S UPPLY V OLTAGE CC AND S UPPLY G ROUND SS The V CC pin is the system supply voltage. The V SS pin is the system ground. Other Pins N O C ONNECT No connect pins should be left open. This pins are used for Xicor manufacturing and testing purposes. H ARDWARE W RITE P ROTECT I NPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers.

Characteristics subject to change without notice. – Resistor Array Description. – Serial Interface Description. – Instruction and Register Description. switch may be turned on at a time. Power Up and Down Recommendations. Figure 1. Detailed Potentiometer Block Diagram

slave device in all applications. while SCL is HIGH. See Figure 2. byte the X9279 will respond with a final acknowledge. Figure 2. Acknowledge Response from Receiver

The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9279 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9279 is still busy with the write operation no ACK will be returned. If the X9279 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. FLOW 1: ACK Polling Sequence INSTRUCTION AND REGISTER DESCRIPTION Device Addressing: Identification Byte ( ID and A) The first byte sent to the X9279 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device ID for the X9279; this is fixed as 0101[B] (refer to Table 1). The A[2:0] bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A2-A0 input pins. The slave address is externally specified by the user. The X9279 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9279 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A2-A0 inputs can be actively driven by CMOS input signals or tied to V CC or VSS. Instruction Byte (I) The next byte sent to the X9279 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode I [2:0]. The RB and RA bits point to one of the four Data Registers. P0 is the POT selection; since the X9279 is single POT, the P0=0. The format is shown in Table 2. Register Bank Selection (RB, RA, P1, P0) There are 16 registers organized into four banks. Bank 0 is the default bank of registers. Only Bank 0 registers can be used for Data Register to Wiper Counter Register operations. Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for 2-Wire write and read operations. The Data Registers in Banks 1, 2, and 3 cannot be used for direct read/write operations between the Wiper Counter Register. Nonvolatile Write Command Completed EnterACK Polling Issue START Issue Slave Address ACK Returned? Further Operation? Issue Instruction Issue STOP No Yes Yes Proceed Issue STOP No Proceed

Table 1. Identification Byte Format Table 2. Instruction Byte Format

Table 3. Instruction Set instruction (see Instruction section for more details). Register zero (DR0) upon power-up. value of Bank 0 is the default value. parameters or user preference data.

Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV). Four of the seven instructions are three bytes in length. associated registers (Bank 0). Register to the Wiper Counter Register. Register to the specified Data Register. See Instruction format for more details. Figure 3. Two-Byte Instruction Sequence

0 A2 A0

Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Wiper Position (Sent by X9279 on SDA) M A C K S T O P0 1 0 1 0A 2 A 1 A 0 10010000 W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Wiper Position (Sent by Master on SDA) S A C K S T O P0101 0 A 2 A 1 A 0 1 0100000 W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Wiper Position (Sent by X9279 on SDA) M A C K S T O P0101 0 A 2 A 1 A 0 1 0 1 1 R B R A P 1 P 0 W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Wiper Position (Sent by Master on SDA) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0A 2 A 1 A 0 1100R B R AP 1 P 0 W C R W C R W C R W C R W C R W C R W C R W C R S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0 A 2 A 1 A 0 1110R BR A00

Transfer Data Register (DR) to Wiper Counter Register (WCR) Increment/Decrement Wiper Counter Register (WCR) Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. (2) “A3 ~ A0”: stands for the device addresses sent by the master. (3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. (4) “I”: stands for the increment operation, SDA held high during active SCL phase (high). (5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high). S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K S T O P01010 A 2 A 1 A 0 1 1 0 1 R B R A 0 0 S T A R T Device Type Identifier Device Addresses S A C K Instruction Opcode DR/Bank Addresses S A C K Increment/Decrement (Sent by Master on SDA) S T O P0 1 0 10 A 2 A 1 A 0 00100000 I / D I / D .... I / D I / D

Voltage on SCL, SDA any address input COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C +70 °C Industrial –40 °C +85 °C Device Supply Voltage (V CC)(4) Limits X9279 5V ±10% X9279-2.7 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH – RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units RTOTAL End to End Resistance 100 k Ω T version RTOTAL End to End Resistance 50 k Ω U version End to End Resistance Tolerance ±20 % Power Rating 50 mW 25 °C, each pot I W Wiper Current ±3 mA RW Wiper Resistance 300 Ω IW = ± 3mA @ VCC = 3V RW Wiper Resistance 150 Ω IW = ± 3mA @ VCC = 5V VTERM Voltage on any RH or RL Pin V SS VCC VV SS = 0V Noise -120 dBV / Hz Ref: 1V Resolution 0.4 % Absolute Linearity (1) ±1 MI (3) Rw(n)(actual) – Rw(n)(expected) (5) Relative Linearity (2) ±0.2 MI (3) Rw(n + 1) – Rw(n) + MI Temperature Coefficient of RTOTAL ±300 ppm/ °C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitances 10/10/25 pF See Macro model

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING A.C. TEST CONDITIONS Notes: (6) This parameter is not 100% tested (7) t PUR and t PUW are the delays required from the time the (last) power supply (V CC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (active) 3m A f SCL = 400KHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and ICC2 VCC supply current (nonvolatile write) 5m A f SCL = 400KHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) ISB VCC current (standby) 5 µAV CC = +6V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) ILI Input leakage current 10 µAV IN = VSS to VCC ILO Output leakage current 10 µAV OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage –1 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA VOH Output HIGH voltage Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Units Test Conditions CIN/OUT (6) Input / Output capacitance (SDA) 8 pF V OUT = 0V CIN (6) Input capacitance (SCL, WP, A2, A1 and A0) 6 pF V IN = 0V Symbol Parameter Min. Max. Units tr VCC (6) VCC Power-up rate 0.2 50 V/ms tPUR (7) Power-up to initiation of read operation 1 ms tPUW (7) Power-up to initiation of write operation 50 ms Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5

EQUIVALENT A.C. LOAD CIRCUIT AC TIMING HIGH-VOLTAGE WRITE CYCLE TIMING Symbol Parameter Min. Max. Units fSCL Clock Frequency 400 kHz tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time 0 ns TI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1200 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns Symbol Parameter Typ. Max. Units tWR High-voltage write cycle time (store instructions) 5 10 ms 1533Ω 100pF SDA pin RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE Macromodel3V 867Ω 100pF SDA pin

Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance

tSU:STA tHD:STA tSU:STO SCL SDA tR (START) (STOP) tF tR tF SCL SDA tHIGH tLOW tCYC tHD:DATtSU:DAT tBUF SCL SDA tDHtAA

XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing SCL SDA VWx (STOP) LSB tWRL SDA SCL ... ... ... WP A0, A1 tSU:WPA tHD:WPA (START) (STOP) (Any Instruction)

Basic Configurations of Electronic Potentiometers Application Circuits VR RW +VR I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO VO = (1+R2/R1)VS Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R2R1 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 100KΩ 10KΩ10KΩ 10KΩ -12V+12V TL072 –VS VO R2R1

Application Circuits (continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) VS VO R2R1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R4 R1 = R2 = R3 = R4 = 10kΩ VS R C VO = G VS G = - R2/R1 R2C1 ZIN – R2 RA RB frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0∞ – 8∞ .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X)

Ball Matrix: 4321 A A0 Vcc RL RH B A2 NC NC RW C SCL NC NC A3 D SDA Vss WP A1 Package Dimensions Symbol Millimeters Min Nominal Max Package Width a 2.593 2.623 2.653 Package Length b 2.771 2.801 2.831 Package Height c 0.644 0.677 0.710 Body Thickness d 0.444 0.457 0.470 Ball Height e 0.200 0.220 0.240 Ball Diameter f 0.300 0.320 0.340 Ball Pitch – Width j 0.5 Ball Pitch – Length k 0.5 Ball to Edge Spacing – Width l 0.537 0.562 0.587 Ball to Edge Spacing – Length m 0.626 0.651 0.676 16-Bump Chip Scale Package (CSP B16) Package Outline Drawing f m j l k b a d e e c Top View (Marking Side) Bottom View (Bumped Side) Side View Side View A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 9279TRB YWW I LOT #

Characteristics subject to change without notice. 24 of 24 LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale onl y. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ©Xicor, Inc. 2003 Patents Pending REV 1.1.7 2/6/03 www.xicor.com

ORDERING INFORMATION

Blank = 5V ±10% –2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package V14 = 14-Lead TSSOP B = 16-Lead CSP Potentiometer Organization Pot T = 100K Ω U = 50K Ω X9279 P T V Y