X9271UVI

X9271 INTERSIL | Alldatasheet

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Technical content

FN8174.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9271 Single Supply/Low Power/256-Tap/SPI Bus Single Digitally-Controlled (XDCP™) Potentiometer

FEATURES

• 256 Resistor Taps  SPI Serial Interface for write, read, and transfer operations of the potentiometer  Wiper Resistance, 100Ω typical @ VCC = 5V  16 Nonvolatile Data Registers  Nonvolatile Storage of Multiple Wiper Positions  Power-on Recall. Loads Saved Wiper Position on Power-up.  Standby Current < 3µA Max CC : 2.7V to 5.5V Operation 5 0 kΩ, 100kΩ versions of End to End Resistance  100 yr. Data Retention  Endurance: 100,000 Data Changes per Bit per Register  14-Lead TSSOP  Low Power CMOS

DESCRIPTION

The X9271 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM 50kΩ and 100kΩ R H R LR W POT VCC VSS SPI Bus Power-on Recall Wiper Counter Register (WCR) Data Registers

16 Bytes

Data Sheet March 31, 2005

2 FN8174.1 March 31, 2005 DETAILED FUNCTIONAL DIAGRAM CIRCUIT LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier  Provide programmable dc reference voltages for comparators and detectors  Control the volume in audio circuits  Trim out the offset voltage error in a voltage amplifier circuit  Set the output voltage of a voltage regulator  Trim the resistance in Wheatstone bridge circuits  Control the gain, characteristic frequency and Q-factor in filter circuits  Set the scale factor and zero point in sensor signal conditioning circuits  Vary the frequency and duty cycle of timer ICs  Vary the dc biasing of a pin diode attenuator in RF circuits  Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS  Adjust the contrast in LCD displays  Control the power level of LED transmitters in communication systems  Set and regulate the DC biasing point in an RF power amplifier in wireless systems  Control the gain in audio and home entertainment systems  Provide the variable DC bias for tuners in RF wireless systems  Set the operating points in temperature control systems  Control the operating point for sensors in industrial systems  Trim offset and gain errors in artificial intelligent systems R 0 R 1 R 2 R 3 WIPER COUNTER REGISTER (WCR) R H R L DATA R W INTERFACE AND CONTROL CIRCUITRY VCC VSS Bank 0 R 0 R 1 R 2 R 3 Bank 1 R 0 R 1 R 2 R 3 Bank 2 R 0 R 1 R 2 R 3 Bank 3 12 additional nonvolatile registers

3 Banks of 4 registers x 8-bits

50kΩ and 100kΩ Power-on Recall X9271

3 FN8174.1 March 31, 2005 PIN CONFIGURATION PIN ASSIGNMENTS VCC R L VSS 7 8 R W SCK CS TSSOP R H X9271 NC SI HOLD WP TSSOP Symbol Function 1 SO Serial Data Output. 2 A0 Device Address. 3 NC No Connect. 4C S Chip Select. 5 SCK Serial Clock. 6 SI Serial Data Input. SS System Ground. 8W P Hardware Write Protect. 9 A1 Device Address. 10 HOLD Device select. Pause the serial bus. 11 R W Wiper Terminal of the Potentiometer. 12 R H High Terminal of the Potentiometer. 13 R L Low Terminal of the Potentiometer. 14 V CC System Supply Voltage. X9271

4 FN8174.1 March 31, 2005 PIN DESCRIPTIONS Bus Interface Pins S ERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. S ERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. S ERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9271. H OLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. CMOS level input. D EVICE ADDRESS (A1 - A0) The address inputs are used to set the the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9271. C HIP SELECT (CS) When CS is HIGH, the X9271 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9271, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins R H , RL The R H and RL pins are equivalent to the terminal connections on a mechanical potentiometer. R W The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Supply Pins S YSTEM SUPPLY VOLTAGE (VCC ) AND SUPPLY G ROUND (VSS ) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins H ARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. N O CONNECT . No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes. X9271

at a time by the Increment/ Decrement instruction. Register zero (DR0) upon power-up. different from the value present at power-down. DR0 value of Bank 0 is the default value. parameters or user preference data. WIP: Write In Progress status bit, read only. Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV). Table 3. Status Register, SR (WIP is 1-bit)

between the Wiper Counter Register. Table 4. Identification Byte Format

Table 5. Instruction Byte Format Five of the eight instructions are three bytes in length. instruction is the only unique format (See Figure 4). Register to the associated Wiper Counter Register. thereby, providing a fine tuning capability to the host. one resistor segment towards the RL terminal. See Instruction format for more details.

11 FN8174.1 March 31, 2005 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Wiper Position (Sent by X9271 on SO) CS Rising Edge010100 A 1 A 0 10010000 W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) CS Rising Edge01010 0 A 1 A 0 10100000 W C R W C R W C R W C R W C R W C R W C R W C R CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge0 1 0 100 A 1 A 0 1011 R B R A P 1 P 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0 0 A 1A 0 1 1 0 0R BR AP 1 P 0 D 7D 6D 5D 4D 3D 2D 1D 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 1 0 100A 1A 01110R B R A 0 0 X9271

12 FN8174.1 March 31, 2005 Transfer Data Register (DR) to Wiper Counter Register (WCR) Increment/Decrement Wiper Counter Register (WCR) Read Status Register (SR) Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master. (2) WCRx refers to wiper position data in the Wiper Counter Register (2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). (3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). (4) “X:”: Don’t Care. CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses CS Rising Edge01010 0A 1 A 01 1 0 1 R BR A00 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Increment/Decrement (Sent by Master on SDA) CS Rising Edge0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge01010 0A 1A 0 010100010000000 W I P X9271

13 FN8174.1 March 31, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on SCK any address input COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power-up VCC > VH , VL, and VW . Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units R TOTAL End to End Resistance 100 k Ω T version R TOTAL End to End Resistance 50 k Ω U version End to End Resistance Tolerance ±20 % Power Rating 50 mW 25 °C, each pot IW Wiper Current ±3 mA R W Wiper Resistance 300 Ω IW = ± 3mA @ VCC = 3V R W Wiper Resistance 150 Ω IW = ± 3mA @ VCC = 5V VTERM Voltage on any RH or RL Pin V SS VCC VV SS = 0V Noise -120 dBV /√Hz Ref: 1V Resolution 0.4 % Absolute Linearity(1) ±1 MI (3) R w(n)(actual) - R w(n)(expected)(5) Relative Linearity(2) ±0.2 MI (3) R w(n + 1) - Rw(n) + MI Temperature Coefficient of R TOTAL ±300 ppm/ °C Ratiometric Temp. Coefficient 20 ppm/°C C H /CL/CW Potentiometer Capacitancies 10/10/25 pF See Macro model RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Commercial 0 °C+ 7 0 °C Industrial -40 °C+ 8 5 °C Device Supply Voltage (V CC )(4) Limits X9271 5V ± 10% X9271-2.7 2.7V to 5.5V X9271

14 FN8174.1 March 31, 2005 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING A.C. TEST CONDITIONS Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC -) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Symbol Parameter Limits Test ConditionsMin. Typ. Max. Units ICC1 VCC supply current (active) 400 µAf SCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS ICC2 VCC supply current (nonvolatile write) 15 m A f SCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS ISB VCC current (standby) 3 µAS C K = S I = VSS , Addr. = VSS , CS = VCC = 6V ILI Input leakage current 10 µAV IN = VSS to VCC ILO Output leakage current 10 µAV OUT = VSS to VCC VIH Input HIGH voltage V CC x 0.7 V CC + 1 V VIL Input LOW voltage -1 V CC x 0.3 V VOL Output LOW voltage 0.4 V I OL = 3mA VOH Output HIGH voltage V CC - 0.8 V I OH = -1mA, VCC ≥ +3V VOH Output HIGH voltage V CC - 0.4 V I OH = -0.4mA, VCC ≤ +3V Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years Symbol Test Max. Units Test Conditions C IN/OUT(6) Input / Output capacitance (SI) 8 pF V OUT = 0V C OUT (6) Output capacitance (SO) 8 pF V OUT = 0V C IN(6) Input capacitance (A0, CS, WP, HOLD, and SCK) 6p F V IN = 0V Symbol Parameter Min. Max. Units tr VCC (6) VCC Power-up rate 0.2 50 V/ms tPUR (7) Power-up to initiation of read operation 1 ms tPUW (7) Power-up to initiation of write operation 50 ms Input Pulse Levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level V CC x 0.5 X9271

15 FN8174.1 March 31, 2005 EQUIVALENT A.C. LOAD CIRCUIT AC TIMING Symbol Parameter Min. Max. Units fSCK SSI/SPI clock frequency 2.5 MHz tCYC SSI/SPI clock cycle time 500 ns tWH SSI/SPI clock high time 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs tDIS SO output disable time 0 250 ns tV SO output valid time 200 ns tHO SO output hold time 0 ns tRO SO output rise time 100 ns tFO SO output fall time 100 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns tCS CS deselect time 2 µs tWPASU WP , A0 setup time 0 ns tWPAH WP , A0 hold time 0 ns 1462Ω 100pF SO pin R H 10pF C L C L R W R TOTAL C W 25pF 10pF R L SPICE Macromodel 2714Ω 1382Ω 100pF SO pin 1217Ω X9271

16 FN8174.1 March 31, 2005 HIGH-VOLTAGE WRITE CYCLE TIMING XDCP TIMING SYMBOL TABLE Symbol Parameter Typ. Max. Units tWR High-voltage write cycle time (store instructions) 5 10 ms Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Lo w to High Will change from Lo w to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X9271

17 FN8174.1 March 31, 2005 TIMING DIAGRAMS Input Timing Output Timing Hold Timing ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ... ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO X9271

18 FN8174.1 March 31, 2005 XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing ... CS SCK SI MSB LSB VWx tWRL ... SO High Impedance CS WP tWPASU tWPAH (Any Instruction) X9271

19 FN8174.1 March 31, 2005 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers Application Circuits VR RW +V R I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Noninverting Amplifier Voltage Regulator Offset Voltage Adjustment Comparator with Hysterisis VS VO R 2 R 1 VO = (1+R2/R1)VS R 1 R 2 Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 VS VO R 2R 1 VUL = {R1/(R1+R 2)} VO (max) RL L = {R1/(R1+R 2)} VO (min) 100kΩ 10kΩ10kΩ 10kΩ -12V+12V TL072 –VS VO R 2R 1 X9271

20 FN8174.1 March 31, 2005 Application Circuits (continued) Attenuator Filter Inverting Amplifier Equivalent L-R Circuit VS VO R 3 R 1 VO = G VS -1/2 ≤ G ≤ +1/2 G O = 1 + R2/R1 fc = 1/(2πRC) VS VO R 2R 1 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 VS Function Generator R 2 R 4 R 1 = R2 = R3 = R4 = 10kΩ VS R 2 R 1 R C VO = G VS G = - R2/R1 R 2C 1 R 1 R 3 ZIN – R 2 R 1 R A R B frequency ∝ R1, R2, C amplitude ∝ RA, RB C VO X9271

21 FN8174.1 March 31, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X9271

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8174.1 March 31, 2005

ORDERING INFORMATION

Blank = 5V ± 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package V = 14-Lead TSSOP Potentiometer Organization Pot U = 50k Ω T = 100k Ω X9271 V T VY X9271