X9271UV14Z-2.7T1

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Document overview

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Technical content

Features

• 2 5 6 R e s i s t o r T a p s
• SPI Serial Interface for Write, Read, and Transfer Operations of Potentiometer
• Wiper Resistance, 100Ω typical at VCC = 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall; Loads Saved Wiper Position on Power-up
• Standby Current <3µA Max
• V CC = 2.7V to 5.5V Operation
• 50kΩ End-to-End Resistance
• 100-yr Data Retention
• Endurance: 100,000 Data Changes per Bit per Register
• 14-Lead TSSOP
• Low-power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant) Functional Diagram 50kΩ RH RLRW POT VCC VSS SPI BUS POWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS

16 Bytes

256 TAPS

FN8174 Rev 5.00 Page 2 of 19 October 15, 2015 Pin Configuration X9271

14 LD TSSOP

Ordering Information

(Notes 2, 3) PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP. RANGE (°C) PACKAGE Pb-Free PKG. DWG. # X9271UV14IZ (Note 1) X9271 UVZI 5 ±10% 50 -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9271UV14Z (Note 1) X9271 UVZ 5 ±10% 50 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9271UV14Z-2.7 (No longer available, recommended replacement: X9271UV14IZ-2.7T1) X9271 UVZF 2.7 to 5.5 50 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9271UV14Z-2.7T1 (No longer available, recommended replacement: X9271UV14IZ-2.7T1) X9271 UVZF 2.7 to 5.5 50 0 to +70 14 Ld TSSOP (4.4mm) M14.173 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for X9271. For more information on MSL please see Tech Brief TB363. VCC RL VSS RW SCK CS RH NC SI HOLD WP Pin Descriptions PIN NUMBER PIN NAME FUNCTION

1 SO Serial Data Output

2 A0 Device Address

3 NC No Connect

5S C K S e r i a l C l o c k

6 SI Serial Data Input

8W P Hardware Write Protect

9 A1 Device Address

10 HOLD Device Select. Pause the serial bus.

11 R W Wiper Terminal of Potentiometer

12 R H High Terminal of Potentiometer

13 R L Low Terminal of Potentiometer

14 V CC System Supply Voltage

FN8174 Rev 5.00 Page 3 of 19 October 15, 2015 Detailed Functional Diagram Circuit-Level Applications

• Vary the gain of a voltage amplifier.
• Provide programmable DC reference voltages for comparators and detectors.
• Control the volume in audio circuits.
• Trim out the offset voltage error in a voltage amplifier circuit.
• Set the output voltage of a voltage regulator.
• Trim the resistance in Wheatstone bridge circuits.
• Control the gain, characteristic frequency, and Q-factor in filter circuits.
• Set the scale factor and zero point in sensor signal conditioning circuits.
• Vary the frequency and duty cycle of timer ICs.
• Vary the DC biasing of a pin diode attenuator in RF circuits.
• Provide a control variable (I, V, or R) in feedback circuits. System-Level Applications
• Adjust the contrast in LCD displays.
• Control the power level of LED transmitters in communication systems.
• Set and regulate the DC biasing point in an RF power amplifier in wireless systems.
• Control the gain in audio and home entertainment systems.
• Provide the variable DC bias for tuners in RF wireless systems.
• Set the operating points in temperature control systems.
• Control the operating point for sensors in industrial systems.
• Trim offset and gain errors in artificial intelligence systems. R0 R1 R2 R3 Wiper Counter Register (WCR) RH RL DA T A RW Interface and Control Circuitry VCC VSS Bank 0 R0 R1 R2 R3 Bank 1 R0 R1 R2 R3 Bank 2 R0 R1 R2 R3 Bank 3

12 Additional Nonvolatile Registers

3 Banks of 4 Registers x 8 Bits

50kΩPower-on Recall

FN8174 Rev 5.00 Page 4 of 19 October 15, 2015 Pin Descriptions Bus Interface Pins SERIAL OUTPUT (SO) The Serial Output (SO) is the serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT (SI) The Serial Input (SI) is the serial data input pin. All operational codes, byte addresses, and data to be written to the potentiometers and potentiometer registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The Serial Clock (SCK) input is used to clock data into and out of the X9271. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is under way, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. CMOS level input. DEVICE ADDRESS (A1 - A0) The Device Address (A1 - A0) inputs are used to set the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9271. CHIP SELECT (CS When Chip Select (CS) is HIGH, the X9271 is deselected, the SO pin is at high impedance and (unless an internal write cycle is under way) the device is in standby state. CS LOW enables the X9271, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin (RW) is equivalent to the wiper terminal of a mechanical potentiometer. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The System Supply Voltage (VCC) pin is the system supply voltage. The Supply Ground (VSS) pin is the system ground. Other Pins HARDWARE WRITE PROTECT INPUT (WP) The Hardware Write Protect Input (WP) pin, when LOW, prevents nonvolatile writes to the data registers. NO CONNECT No Connect pins should be left floating. These pins are used for Intersil manufacturing and testing purposes. Principles of Operation Device Description SERIAL INTERFACE The X9271 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three-state outputs. This can help to reduce system pin count. ARRAY DESCRIPTION The X9271 is composed of a resistor array (Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R H and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array, only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The eight bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (Table 1). POWER-UP AND POWER-DOWN RECOMMENDATIONS There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins, provided that VCC is always more positive than or equal to VH, VL, and VW; i.e., VCC  VH, VL, VW. The VCC ramp rate specification is always in effect.

select one of 256 switches along its resistor array (Table 1).

1. It can be written directly by the host via the Write Wiper

Counter Register instruction (serial load).

1. It can be written indirectly by transferring the contents of

Register instruction (parallel load).

1. It can be modified one step at a time by the Increment/
2. It is loaded with the contents of its Data Register zero (DR0)

The potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host (Table 2). WIP: Write In Progress status bit; read only.

• WIP = 1 indicates that a high-voltage write cycle is in progress.
• WIP = 0 indicates that no high-voltage write cycle is in progress SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 SERIAL BUS INPUT PARALLEL BUS INPUT COUNTER REGISTER INC/DEC LOGIC UP/DN CLKMODIFIED SCK UP/DN RH RL RW 8 8 C O U N T E R D E C O D E IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH WIPER (WCR) BANK_0 Only (DR0) (DR1) (DR2) (DR3)

FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]:

The A1 - A0 bits in the ID byte are the internal slave address. the data register to Wiper Counter Register operations. TABLE 2. DATA REGISTER, DR (8-BIT), DR[7:0]: Used to store TABLE 3. STATUS REGISTER, SR (WIP is 1-bit) TABLE 5. REGISTER SELECTION (DR0 TO DR3) TABLE 6. REGISTER BANK SELECTION (BANK 0 TO BANK 3) TABLE 7. INSTRUCTION BYTE FORMAT

1. Set to P0 = 0 for potentiometer operations.

FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS TABLE 8. INSTRUCTION SET R e a d W i p e r C o u n t e r R e g i s t e r 10010 0 01 / 0 R ead contents of Wiper Counter Register. W r i t e W i p e r C o u n t e r R e g i s t e r 10100 0 01 / 0 W r i t e n e w v a l u e t o W i p e r Counter Register. RB - RA (Bank 0 only) to Wiper Counter Register. pointed to by RB-RA (Bank 0 only). R e a d S t a t u s ( W I P B i t ) 01010 0 0 1 R ead status of internal write cycle by checking WIP bit.

FN8174 Rev 5.00 Page 10 of 19 October 15, 2015 Read Data Register (DR) Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) (Notes 5, 6) Increment/Decrement Wiper Counter Register (WCR) (Notes 5, 6, 7, 8, 9) Read Status Register (SR) (Note 5) CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge0 1 0 100A 1 A 01011R B R A P 1 P 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 1 0 100A 1A 01110 R B R A 0 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses CS Rising Edge0 1 0 100 A 1 A 0 1101R B R A 0 0 CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Increment/Decrement (Sent by Master on SDA) CS Rising Edge0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D CS Falling Edge Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) CS Rising Edge01010 0A 1 A 0 010100010000000 W I P NOTES: 5. “A1 ~ A0”: stands for the device addresses sent by the master. 6. WCRx refers to wiper position data in the Wiper Counter Register. 7. “I”: stands for the increment operation. SI held HIGH during active SCK phase (high). 8. “D”: stands for the decrement operation. SI held LOW during active SCK phase (high). 9. “X:”: Don’t Care.

FN8174 Rev 5.00 Page 11 of 19 October 15, 2015 Absolute Maximum Ratings Thermal Information Voltage on SCK, any Address Input, Supply Voltage (VCC) Limits: Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Characteristics Across recommended industrial operating conditions unless otherwise specified. SYMBOL PARAMETER LIMITS TEST CONDITIONS MIN (Note 17)T Y P MAX (Note 17)U N I T S RTOTAL End to End Resistance 50 kΩ U version End to End Resistance Tolerance ±20 % Power Rating 50 mW +25°C, each pot I W Wiper Current ±3 mA RW Wiper Resistance 300 WI W = ± 3mA at VCC = 3V RW Wiper Resistance 150 WI W = ± 3mA at VCC = 5V VTERM Voltage on any RH or RL Pin VSS VCC VV SS = 0V Noise -120 dBV Hz Ref: 1V Resolution 0.4 % Absolute Linearity (Note 10) ±1 MI (Note 12) Rw(n)(actual) - Rw(n)(expected) (Note 14) Relative Linearity (Note 11) ±0.2 MI (Note 12) Rw(n + 1) - [Rw(n) + MI] (Note 14) Temperature Coefficient of RTOTAL ±300 ppm/ C Ratiometric Temp. Coefficient 20 ppm/°C CH/CL/CW Potentiometer Capacitance 10/10/25 pF See macro model NOTES: 10. Absolute linearity is used to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 11. Relative linearity is used to determine actual change in volt age between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 12. MI = RTOT / 255 or (R H - RL) / 255, single pot. 13. During power-up, V CC > VH, VL, and VW.

FN8174 Rev 5.00 Page 12 of 19 October 15, 2015 Endurance and Data Retention Capacitance Power-Up Timing A.C. Test Conditions NOTES: 15. This parameter is not 100% tested. 16. t PUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and are not 100% tested. 17. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. D.C. Operating Characteristics Across the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER LIMITS TEST CONDITIONS MIN (Note 17)T Y P MAX (Note 17)U N I T S ICC1 VCC Supply Current (Active) 400 µA f SCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS ICC2 VCC Supply Current (Nonvolatile Write) 15 m A f SCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS ISB VCC Current (Standby) 3 µA SCK = SI = V SS, Addr. = VSS, CS = VCC = 6V ILI Input Leakage Current 10 µA V IN = VSS to VCC ILO Output Leakage Current 10 µA V OUT = VSS to VCC VIH Input HIGH Voltage V CC x 0.7 V CC + 1 V VIL Input LOW Voltage -1 V CC x 0.3 V VOL Output LOW Voltage 0.4 V I OL = 3mA VOH Output HIGH Voltage V CC - 0.8 V I OH = -1mA, VCC  +3V VOH Output HIGH Voltage V CC - 0.4 V I OH = -0.4mA, VCC  +3V PARAMETER MIN. (Note 17) UNITS Minimum Endurance 100,000 Data changes per bit per register Data Retention 100 Years SYMBOL TEST MAX. (Note 17) UNITS TEST CONDITIONS CIN/OUT (Note 15) Input / Output Capacitance (SI) 8 pF V OUT = 0V COUT (Note 15) Output Capacitance (SO) 8 pF V OUT = 0V CIN (Note 15) Input Capacitance (A0, CS , WP, HOLD, and SCK) 6 pF V IN = 0V SYMBOL PARAMETER MIN. (Note 17) MAX. (Note 17) UNITS tr VCC (Note 15)V CC Power-up Rate 0.2 50 V/ms tPUR (Note 16) Power-up to Initiation of Read Operation 1 ms tPUW (Note 16) Power-up to Initiation of Write Operation 50 ms INPUT PULSE LEVELS V CC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Level V CC x 0.5

FN8174 Rev 5.00 Page 13 of 19 October 15, 2015 Equivalent A.C. Load Circuit 1462Ω 100pF SO pin RH 10pF CL CL RW RTOTAL CW 25pF 10pF RL SPICE MACROMODEL 2714Ω 1382 100pF SO pin 1217 AC Timing SYMBOL PARAMETER MIN MAX UNITS fSCK SSI/SPI Clock Frequency 2.5 MHz tCYC SSI/SPI Clock Cycle Time 500 ns tWH SSI/SPI Clock High Time 200 ns tWL SSI/SPI Clock Low Time 200 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SI, SCK, HOLD and CS Input Setup Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI SI, SCK, HOLD and CS Input Rise Time 2 µs tFI SI, SCK, HOLD and CS Input Fall Time 2 µs tDIS SO Output Disable Time 0 250 ns tV SO Output Valid Time 200 ns tHO SO Output Hold Time 0 ns tRO SO Output Rise Time 100 ns tFO SO Output Fall Time 100 ns tHOLD HOLD Time 400 ns tHSU HOLD Setup Time 100 ns tHH HOLD Hold Time 100 ns tHZ HOLD Low to Output in High Z 100 ns tLZ HOLD High to Output in Low Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 10 ns tCS CS Deselect Time 2 µs tWPASU WP, A0 Setup Time 0 ns tWPAH WP, A0 Hold Time 0 ns High-voltage Write Cycle Timing SYMBOL PARAMETER TYP MAX UNITS tWR High-voltage Write Cycle Time (Store Instructions) 5 10 ms

FN8174 Rev 5.00 Page 14 of 19 October 15, 2015 Timing Diagrams Input Timing Output Timing XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRPO Wiper Response Time After Third (Last) Power Supply is Stable 5 1 0µ s tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 5 10 µs Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance ... CS SCK SI SO MSB LSB High Impedance tLEAD tHtSU tFI tCS tLAGtCYC tWL ... tRItWH ... CS SCK SO SI ADDR MSB LSB tDIStHOtV ...

FN8174 Rev 5.00 Page 15 of 19 October 15, 2015 Hold Timing XDCP Timing (for All Load Instructions) Write Protect and Device Address Pins Timing ... CS SCK SO SI HOLD tHSU tHH tLZtHZ tHOLD tRO tFO ... CS SCK SI MSB LSB VWx tWRL ... SO High Impedance CS WP tWPASU tWPAH (Any Instruction)

FN8174 Rev 5.00 Page 18 of 19 October 15, 2015 X9271 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 15, 2015 FN8174.5 - Updated Ordering Information Table on page 2. - Added Revision History. - Added About Intersil Verbiage.

FN8174 Rev 5.00 Page 19 of 19 October 15, 2015 Package Outline Drawing M14.173

14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)

Rev 3, 10/09 DETAIL "X"SIDE VIEW TYPICAL RECOMMENDED LAND PATTERN TOP VIEW B A 814 C PLANE SEATING 0.10 C 0.10 CBA H PIN #1 I.D. MARK 5.00 ±0.10 4.40 ±0.10 0.25 +0.05/-0.06 6.40

0.20 C B A

0.05 0°-8° GAUGE PLANE SEE 0.90 +0.15/-0.10 0.60 ±0.15 0.09-0.20

1.00 REF

0.65

1.20 MAX

0.25

0.05 MIN

0.15 MAX

(1.45) (5.65) (0.65 TYP) (0.35 TYP) DETAIL "X" 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. NOTES: END VIEW